Development of a High-Performance, FPGA-Based Virtual Anemometer for Model-Based MPPT of Wind Generators
Abstract
:1. Introduction
- A more comprehensive analysis of past works on virtual sensors has been provided, and several new references have been added;
- The training algorithm for the GNG ANN has been described;
- The interaction between the main processing platform and the virtual anemometer coprocessor is better described with the help of a new figure;
- The reuse factor of VHDL components that exploit resource sharing has been explicitly stated;
- The code of the chosen parallel sorting algorithm has been added;
- The compatibility of the virtual anemometer FPGA design with application-specific integrated circuit (ASIC) and system-on-chip (SoC) implementations has been highlighted; in particular, it has been shown that even the low-end, commercial SoCs have an adequate number of resources to implement the virtual anemometer.
2. Models of Horizontal and Vertical Axis Wind Turbines
2.1. Horizontal Axis Wind Turbine
2.2. Vertical Axis Wind Turbine
3. The GNG Artificial Neural Network
3.1. Training Phase
- Start with two neurons a and b with random weights wa and wb in ℜn;
- Present an input signal ξ belonging to the training dataset;
- Find the nearest neuron s1 and the second nearest neuron s2;
- Increment the age of all edges emanating from s1;
- Add the squared distance between the input signal and the nearest neuron in the input space to a local counter variable:
- Move s1 in its direct topological neighbors towards ξ by fractions εb and εn, respectively, of the total distance:
- If s1 and s2 are connected by an edge, set the age of this edge to zero; if such an edge does not exist, create it;
- Remove edges with an age larger than amax; if this results in points with no emanating edges, remove them;
- If the number of input data presented so far is an integer multiple of a parameter λ, create a new neuron as follows:
- Determine the neuron q with the maximum accumulated error;
- Insert a new neuron r halfway between q and its neighbor f, and remove the original edge between q and f;
- Decrease the error variables of q and f multiplying them by a constant α; initialize the error variable of r with the new value of the error variable of q;
- Decrease all error variables multiplying them by a constant d;
- If a stopping criterion (e.g., net size or performance criterion) is not yet fulfilled, then go to step 2.
3.2. Recalling Phase
- Present the input vector ;
- Compute the K Euclidean distances Dk between the vector and the weights wi,k of the K neurons of the GNG;
- Sort the Dk’s in ascending order and consider the corresponding first P neurons;
- Compute the estimated output y by:
4. FPGA Implementation of the Virtual Anemometer
4.1. SPI Communication Interface and Protocol
4.2. GNG ANN Implementation
- The inputs/outputs of the ANN are 10-bit integers as the data width of most ADCs commonly used within control systems;
- The weights of the ANN are also 10-bit integers, and they are stored in a ROM that is implemented using some of the dedicated memory blocks inside the FPGA chip;
- Hardware multipliers are used for computing blocks Δx2 and Δy2 of Figure 5;
- Fixed point arithmetic is used; the related precision varies from 10 bit to 32 bit; in particular, Figure 5 indicates the used datatype as a triplet (s,b,f), where s = sign bit, b = total number of bits, f = number of fractional bits;
- The final weighted sum is computed considering the eight neurons closest to the input data;
- True parallel implementation was chosen for blocks u−1, u1/u2, sqrt(u);
- Resource sharing is enforced for blocks u2 and for the sorting component with a reuse factor equal to 32;
- For this latter component a fast, parallel sorting algorithm, i.e., bitonic sort [38], has been chosen; this algorithm was implemented to select the eight smallest values among 16 input numbers; hence, the obtained VHDL component processes the distances from the input point to all neurons in blocks of 16 on several consecutive clock cycles; the bitonic sort algorithm, written as Matlab code, is shown in Algorithm 1.
Algorithm 1. Matlab code of Bitonic Sort algorithm. |
% this function implements bitonic sort algorithm |
% in ascending order for 16 input elements |
function outVec = bitonicSorter(inVec) |
outVec = bitonicSort16(inVec); |
end |
function out = bitonicSort16(in) |
out(1:8) = bitonicSort8(in(1:8), true); |
out(9:16) = bitonicSort8(in(9:16), false); |
out = bitonicMerge16(out, true); |
end |
function out = bitonicSort8(in, direction) |
out(1:4) = bitonicSort4(in(1:4), true); |
out(5:8) = bitonicSort4(in(5:8), false); |
out = bitonicMerge8(out, direction); |
end |
function out = bitonicSort4(in, direction) |
out(1:2) = bitonicSort2(in(1:2), true); |
out(3:4) = bitonicSort2(in(3:4), false); |
out = bitonicMerge4(out, direction); |
end |
function out = bitonicSort2(in, direction) |
out = bitonicMerge2(in, direction); |
end |
function out = bitonicMerge16(in, direction) |
for i = 1:8 |
tmp = compare([in(i); in(i + 8)], direction); |
out(i) = tmp(1); |
out(i+8) = tmp(2); |
end |
out(1:8) = bitonicMerge8(out(1:8), direction); |
out(9:16) = bitonicMerge8(out(9:16), direction); |
end |
function out = bitonicMerge8(in, direction) |
for i = 1:4 |
tmp = compare([in(i); in(i + 4)], direction); |
out(i) = tmp(1); |
out(i+4) = tmp(2); |
end |
out(1:4) = bitonicMerge4(out(1:4), direction); |
out(5:8) = bitonicMerge4(out(5:8), direction); |
end |
function out = bitonicMerge4(in, direction) |
for i = 1:2 |
tmp = compare([in(i); in(i + 2)], direction); |
out(i) = tmp(1); |
out(i+2) = tmp(2); |
end |
out(1:2) = bitonicMerge2(out(1:2), direction); |
out(3:4) = bitonicMerge2(out(3:4), direction); |
end |
function out = bitonicMerge2(in, direction) |
out = compare([in(1); in(2)], direction); |
end |
function out = compare(in, direction) |
if direction == (in(1) > in(2)) |
out = [in(2); in(1)]; |
else |
out = in; |
end |
end |
5. Experimental Validation
6. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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Resource Count | Used by the Proposed Design | Available on Altera Cyclone III EP3C25F324 | Available on Xilinx Zynq Z-7007S |
---|---|---|---|
Logic elements/Prog. logic cells | 22,148 | 24,624 | 23,552 |
Registers/Flip-Flops | 2265 | 24,624 | 28,800 |
Memory bits/Block RAM | 6528 | 608,256 | 1,887,436 |
Embedded multipliers/DSP slices | 32 | 132 | 66 |
Parameter | Value |
---|---|
R [m] | 2.50 |
λopt | 7 |
Cpmax | 0.45 |
n | 4.86 |
Generator rated power [kW] | 5.5 |
Generator rated speed [rpm] | 1500 |
Model coefficients | c1 = 0.5176, c2 = 116, c3 = 0.4, c4 = 5, c5 = 21, c6 = 0.0068 |
Parameter | Value |
---|---|
R [m] | 0.75 |
λopt | 2 |
Cpmax | 0.15 |
n | 1 |
Generator rated power [kW] | 1.0 |
Generator rated speed [rpm] | 415 |
Model coefficients | a1 = −25.6815, a2 = 87.6095, a3 = 8.0646, a4 = 0.048076 |
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La Tona, G.; Luna, M.; Di Piazza, M.C.; Pucci, M.; Accetta, A. Development of a High-Performance, FPGA-Based Virtual Anemometer for Model-Based MPPT of Wind Generators. Electronics 2020, 9, 83. https://doi.org/10.3390/electronics9010083
La Tona G, Luna M, Di Piazza MC, Pucci M, Accetta A. Development of a High-Performance, FPGA-Based Virtual Anemometer for Model-Based MPPT of Wind Generators. Electronics. 2020; 9(1):83. https://doi.org/10.3390/electronics9010083
Chicago/Turabian StyleLa Tona, Giuseppe, Massimiliano Luna, Maria Carmela Di Piazza, Marcello Pucci, and Angelo Accetta. 2020. "Development of a High-Performance, FPGA-Based Virtual Anemometer for Model-Based MPPT of Wind Generators" Electronics 9, no. 1: 83. https://doi.org/10.3390/electronics9010083
APA StyleLa Tona, G., Luna, M., Di Piazza, M. C., Pucci, M., & Accetta, A. (2020). Development of a High-Performance, FPGA-Based Virtual Anemometer for Model-Based MPPT of Wind Generators. Electronics, 9(1), 83. https://doi.org/10.3390/electronics9010083