# CRM PFC Converter with New Valley Detection Method for Improving Power System Quality

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## Abstract

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## 1. Introduction

_{zcd}) for the SFL. However, though maximizing the efficiency, this method inevitably causes an error in the accurate calculation of the switching point, i.e., the valley point, owing to the change in the LC resonance frequency. In addition, it is difficult to obtain a high power factor using this method because the switching frequency is limited in light-load and low-input-voltage conditions, such as SFL. Previous works [17,18,19] have analyzed interleaving CRM boost PFC and CRM Totem-Pole PFC. The interleaving method has an advantage, as it allows the efficiency to be improved to some degree in the full-load range. However, switching losses increase because the switching frequency increases rapidly in the light-load condition. Therefore, problems such as metal oxide semiconductor field effect transistors (MOSFETs) being damaged relatively frequently, have been reported. Furthermore, the cost increases, because more switches, gate drivers, and controllers are required due to the parallel structure. For this reason, the industry considers interleaving CRM PFC above 300 W, but it is common to use a single CRM PFC that can be implemented with low cost under 300 W.

_{VAL}” changes from negative to positive, to enable an error-free valley point detection. Furthermore, based on the collected information, the reference signal for the ON-time extension is then generated in the current signal generator. Consequently, the proposed method can reduce the switching loss by suppressing the increase in the switching frequency, and can improve the reduced power factor due to the fixed ON-time, using the extended ON-time strategy at light-load conditions. In addition, the problem of MOSFETs getting damaged in light-load conditions can be addressed by turning the gate on at zero current voltage using a timer, in this method. The actual circuit with the proposed strategy was implemented and tested on a 240 W SMPS for a 55-inch smart TV. In order to prove the superiority of the new valley detection method using the proposed ON-time extension technique, the two existing methods, i.e., fixed ON-time method, denoted “conventional#1” [20]; and existing valley detection method, denoted “conventional#2” [21], were selected as the comparison group. The experimental results were then derived, based on the comparison. Experimental results demonstrated an efficiency improvement of 2.1%, compared with the conventional CRM PFC; and a power factor improvement of 34.9%, compared with the switching frequency limiting strategy under a 20% load condition.

## 2. Description for Conventional CRM boost PFC

_{in}), where the switch ON-time (T

_{on}) is a constant value to retain the output voltage (V

_{out}) at a target value, and the average value of the inductor current (I

_{L}) in a switching cycle, i.e., the input current of the PFC converter is proportional to V

_{in}, as shown in Figure 2 [20,21,22,23,24]. It was observed that the CRM boost PFC shows a reduced power conversion efficiency, because the switching frequency was increased significantly at the low-input-voltage or light-load condition.

#### 2.1. Switching Frequency Limit Method

_{on}, it is typical to limit the switching frequency, as shown in Figure 3. The timing to turn the switch ON is delayed until a predetermined time passes from the previous point when the switch is turned ON, even though I

_{L}returns to zero [5,25]. In this method, switching is reduced, but the average I

_{L}in a period also changes with the switching frequency. Therefore, it is difficult to reduce the limit of the switching frequency without degrading the power factor. Furthermore, switching with a low peak of I

_{L}is reduced, but still occurs when V

_{in}is low. Such switching only consumes energy without contributing any energy transfer from the input to the output, as the energy stored in the inductor is insufficient to change the parasitic capacitance of the drain of the switch or to conduct the diode.

#### 2.2. Existing Valley Switching Method

_{L}returns to zero, the drain–source voltage of the switch (V

_{ds}) starts to decrease due to the resonance between the inductance of the inductor (L) and the drain–source parasitic capacitance of the switch (C

_{oss}). Therefore, turning the switch ON at a valley of V

_{ds}is better than when I

_{L}returns to zero after a current through the diode stops, for efficiency.

_{L}reaches zero is widely used. The timer must be set depending on the resonant frequency from one converter to another; therefore, a pin for the setting is often assigned when such controllers are fabricated in ICs. However, the resonant frequency changes even in a converter, depending on the input voltage of the converter, because C

_{oss}contains the parasitic capacitance of a P–N junction in the MOSFET switch, which depends on the voltage applied to it. Furthermore, if we realize valley switching using the timer, even when a frequency limit function delays the timing for the switch to turn ON again, as shown in Figure 3, the timing of the valley must be estimated from the moment I

_{L}returns to zero after the current through the diode stops. The error of the timer against the resonant frequency accumulates. Therefore, this method is not practical when the number of valleys to be skipped before the switch turns ON is large.

## 3. Proposed Valley Detection Strategies with ON-Time Extension

#### 3.1. Realization of Proposed Method

_{sw}) satisfies Equation (1).

_{L}is the inductor current, T

_{sw}is the switching period, T

_{ono}is the ON-time before it is extended, V

_{in}is the input voltage, and L is the inductance.

_{ramp}), which begins to increase at the moment the switch turns ON. An error amplifier amplifies the difference between the voltage feedback signal from the PFC converter (V

_{FB}) and a predetermined reference voltage (V

_{ref}), and generates an output voltage (V

_{ea}). V

_{ramp}is compared with V

_{ea}, and the current sense signal from the PFC converter (V

_{CS}) is compared with a voltage corresponding to the predetermined minimum level of the inductor current (V

_{csmin}). An OFF trigger signal to turn the switch OFF is generated if V

_{CS}is larger than V

_{csmin}when V

_{ramp}reaches V

_{ea}, similar to conventional CRM boost PFC converters.

_{CS}reaches V

_{csmin}, that is, when the ON-time is extended. After the switch turns OFF, the point where the inductor current returns to zero (T

_{zcd}) is detected, by comparing V

_{CS}with a voltage corresponding to the state (T

_{zcd}), which is typically slightly lower than zero. An ON trigger signal to turn the switch ON is generated by a current signal generator, capacitor, reset switch, and comparator. To realize extended ON-time, the reference current signal (I

_{int}), which is the output of the current signal generator as shown in Figure 7, should be defined first; this signal should be defined by each section, according to the levels of V

_{ramp}and V

_{ea}, as shown in Figure 8. I

_{int}for each mode in Figure 8 is described as follows:

_{int}is the output current generated by the current signal generator, K is constant value which can be selected for easy circuit implementation, V

_{ramp}is ramp signal voltage, V

_{ea}is the generated output voltage, T

_{zcd}is the time when the inductor current returns to zero, and T

_{sw}is switching period. Here, for brevity, it is assumed that the ramp signal starts at 0 V.

#### 3.2. Description of ON-Time Extension

_{int}. When the ON-time is extended, the voltage stored in the capacitor is larger than zero at the moment when the switch turns OFF, and is reduced by I

_{int}($-K\xb7{V}_{ea}$) subsequently. Finally, it reaches zero, and the comparator generates the ON trigger signal.

_{L}and V

_{ramp}continue increasing. Simultaneously, the capacitor integrates I

_{int}, which is proportional to twice that of the difference between V

_{ramp}and V

_{ea}. The switch is turned off when I

_{L}reaches a predetermined level (I

_{Lmin}). Subsequently, I

_{L}decreases and returns to zero. During that time, the value of V

_{ramp}remains the previous value at the moment the switch turns OFF, and I

_{int}is proportional to the difference between V

_{ramp}and V

_{ea}. After I

_{L}reaches zero (in fact, I

_{L}remains in resonance with a small amplitude, owing to the parasitic capacitance in this region; however, it is omitted for a simple illustration), the capacitor is discharged by I

_{int}, which is a constant value depending on V

_{ea}. When the voltage stored in the capacitor reaches zero, the switch is turned ON again, and the same operation in the previous period repeats. Here, it can be confirmed that the length of a period (T

_{sw}) decided by integrating I

_{int}satisfies Equation (1), which describes a desirable operation. Additionally, the voltage between the switches remain in resonance in the time period when I

_{L}remains in resonance; and T

_{sw}can be adjusted within a range of cycles of resonant frequency, by combining techniques typically employed in conventional PFC converters. For minimizing loss, it is better to delay the timing to turn ON the switch from T

_{sw}, as calculated by Equation (1), to the next valley of V

_{d}, where the loss from turning the switch ON is the smallest.

## 4. Circuit Implementations and Design Considerations

_{d}in detail are examined, and the actual implementation circuitry for each method is described.

#### 4.1. Proposed Valley Detect Method with Current Sense Voltage

_{CS}crosses zero, from positive to negative. In this case, no additional external component is necessary, but the V

_{CS}in the resonant region of V

_{d}is typically small, and noise should be considered. Figure 9a shows a circuit to detect the zero-cross of V

_{CS}, where an offset cancel topology is employed to avoid the effect transistor mismatch in detecting small voltages. When valley detection is not required, the switches controlled by DET

_{b}turn ON, and the voltage corresponding to the condition V

_{CS}= 0 is stored to the capacitor C

_{hold}. In detecting the valley, the switch controlled by DET turns ON, and the voltage depending on V

_{CS}is compared with the voltage stored in C

_{hold}. We can adjust the gain from V

_{CS}to the voltage for the comparison, with resistors R

_{csin}and R

_{csa}. By verifying the moment that the comparator output changes from high to low during the detection, we can detect the moment that V

_{CS}crosses zero, from positive to negative.

#### 4.2. Proposed Valley Detect Method with Divided Drain Voltage

_{d}using two capacitors, i.e., C1 and C2, as shown in Figure 10, and to sense the moment that the differentiation of the divided voltage V

_{VAL}changes from negative to positive. One of the two capacitors (C2) is often used in practical applications to reduce EMI noise, and only one low-voltage capacitor (C1) is necessary in this case. The value of the capacitors for the divided voltage should not exceed the input range of the circuit receiving it. Figure 9b shows a valley detection circuit with the divided voltage of V

_{d}. Part of the circuit is the same as that shown in Figure 9a, and a differentiator is additionally included. Owing to the capacitor C

_{div}connected between the input and the node with near constant voltage maintained by the source-follower transistors, the current proportional to dV

_{VAL}/dt is generated, and converted to the voltage fed to the comparator. When valley detection is not required, the switches controlled by DET

_{b}turn ON; the voltage corresponding to when the current proportional to dV

_{VAL}/dt is equal to zero is stored in capacitor C

_{hold}. In detecting the valley, the switch controlled by DET turns ON, and the current–voltage proportional to dV

_{VAL}/dt is compared with the voltage stored in C

_{hold}. By verifying the moment when the comparator output changes from low to high during the detection, we can detect the moment when the differentiation of VAL changes from negative to positive.

## 5. Simulation and Experimental Results

#### 5.1. Simualtion Results

_{CS}’ and ‘V

_{VAL}’.

_{in}conditions, i.e., 300 and 100 V, in a light-load condition. To verify the effect of delay for the current detection, the low-pass filters for V

_{cs}is changed in the ranges of 50 Ω—47 pF and 39 Ω—5 nF. The simulation results in Figure 12 and Figure 13 correspond to the valley detection circuits with V

_{cs}and V

_{VAL}, respectively.

_{L}is almost the same even if V

_{in}decreases from 300 V to 100 V, and only switching frequency decreases; from which we can confirm that the proposed control method in light-load conditions operates properly. Moreover, we can confirm that the switch always turns ON near the valley of V

_{d}in both valley detection circuits.

_{L}on V

_{in}increases, because slope of I

_{L}depends on V

_{in}, and a larger slope results in a larger extension owing to the delay of the low-pass filter. When the peak value of I

_{L}increases, owing to delay of the low-pass filter, the switching frequency decreases to cancel its effect.

_{d}, when a valley detection circuit with V

_{cs}is employed; however, it does not change, owing to the delay of the low-pass filter, when a valley detection circuit with V

_{VAL}is employed.

#### 5.2. Experimental Results

_{ac}and an output power of 40 W (400 V/0.1 A). Figure 15a shows the time-extended inductor current waveform shown in Figure 8, with the current sense voltage valley detection circuit shown in Figure 9a. As shown, the delay in switching ON is calculated by calculating t

_{sw}, satisfying Equation (1). Figure 15b shows the inductor current of the existing CRM boost PFC. The switching frequency in the zero-crossing region at a 40 W load is 130 kHz and shows a typical CRM boost PFC inductor current waveform, similar to that shown in Figure 2. Figure 15c shows the inductor current when the proposed valley switching technique is applied. The switching frequency is reduced to 76 kHz through the new valley detector method and the ON-time is extended, as shown in Figure 6 and Figure 8, even under the same load condition.

_{ds}voltage while resonating, which may reduce the efficiency. In terms of power factor, due to its fast switching in light-load and low-input-voltage conditions, the conventional#1 method achieves a higher power factor than the conventional#2 method. As a result, the power factor of the conventional#1 method was measured at 0.85 and 0.93 at 5 W and 40 W, respectively, while that of the proposed method was 0.95 and 0.985 under the same conditions, respectively. All the test conditions were controlled identically, and the comparison experiment was conducted after changing only the conventional#1 method to conventional#2 method. The efficiency of the conventional#2 method was 97% at 40 W and 48% at 1 W, which was 0.7% and 4% lower than that of the proposed method, respectively. However, this indicates that the conventional#2 method is relatively better than the conventional#1 method, in terms of efficiency. This result is because of the reduction in switching losses due to the limited switching frequency of 150 kHz, especially in light-load and low-input-voltage conditions. Compared with the proposed method, the efficiency drop in the conventional#2 method increases as the load decreases. The analysis indicates that the reason for this result is the switching ON time limit of the conventional#2 method at light-loads and low-input-voltages. Compared with the proposed method, the power factor of the conventional#2 method shows a significantly larger difference under an 80 W load; moreover, a power factor difference of 0.581 is observed at 1 W. These results can be attributed to the large current distortion caused by the switching limitation of the conventional#2 controller in light-load and low-input-voltage conditions.

## 6. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## Abbreviations

C_{oss} | Drain–source parasitic capacitance of the switch |

CRM | Critical mode |

I_{L} | Inductor current |

I_{int} | Signal generator generates an output current |

K | Constant value |

LC | Inductance and capacitance |

MOSFET | Metal oxide semiconductor field effect transistor |

PFC | Power factor correction |

SMPS | Switch mode power supply |

T_{on} | Switch ON-time |

T_{ono} | ON-time before it is extended |

T_{sw} | Switching period |

T_{zcd} | Inductor current returns to zero |

V_{cs} | Current sense voltage |

V_{csmin} | Minimum level of the inductor current |

V_{ds} | Drain–source voltage of the switch |

V_{ea} | Generates an output voltage |

V_{FB} | Voltage feedback signal |

V_{in} | Input voltage |

V_{out} | Output voltage |

V_{ramp} | Ramp signal voltage |

V_{ref} | Reference voltage |

V_{VAL} | Differentiation of the divided voltage |

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**Figure 7.**Circuit diagram of PFC control with proposed valley detection method with ON-time extension.

**Figure 9.**The proposed valley detection circuit: (

**a**) current sense voltage circuit; (

**b**) divided drain voltage circuit.

**Figure 12.**Simulation results of valley detection from current sense voltage (V

_{CS}): (

**a**) inductor current and drain–source voltage (Vin = 300 V, LPF = 50 Ω × 47 pF); (

**b**) inductor current and drain–source voltage (Vin = 100 V, LPF = 50 Ω × 47 pF); (

**c**) inductor current and drain–source voltage (Vin = 300 V, LPF = 39 Ω × 5 nF); (

**d**) inductor current and drain–source voltage (Vin = 100 V, LPF = 39 Ω × 5 nF).

**Figure 13.**Simulation results of valley detection from divided drain voltage (V

_{VAL}): (

**a**) inductor current and drain–source voltage (Vin = 300 V, LPF = 50 Ω × 47 pF); (

**b**) inductor current and drain–source voltage (Vin = 100 V, LPF = 50 Ω × 47 pF); (

**c**) inductor current and drain–source voltage (Vin = 300 V, LPF = 39 Ω × 5 nF); (

**d**) inductor current and drain–source voltage (Vin = 100V, LPF = 39 Ω × 5 nF).

**Figure 15.**Key experimental waveform: (

**a**) ON-time extended inductor current with new valley detection from current sense voltage (V

_{CS}); (

**b**) inductor current and drain–source voltage with conventional method; (

**c**) inductor current and drain–source voltage with proposed valley detection method.

**Figure 16.**Comparison results of efficiency and power factor: (

**a**) efficiency for full load range; (

**b**) light-load efficiency from 1 W to 80 W; (

**c**) power factor for full load range.

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**MDPI and ACS Style**

Cho, K.-S.; Lee, B.-K.; Kim, J.-S.
CRM PFC Converter with New Valley Detection Method for Improving Power System Quality. *Electronics* **2020**, *9*, 38.
https://doi.org/10.3390/electronics9010038

**AMA Style**

Cho K-S, Lee B-K, Kim J-S.
CRM PFC Converter with New Valley Detection Method for Improving Power System Quality. *Electronics*. 2020; 9(1):38.
https://doi.org/10.3390/electronics9010038

**Chicago/Turabian Style**

Cho, Kwang-Seung, Byoung-Kuk Lee, and Jong-Soo Kim.
2020. "CRM PFC Converter with New Valley Detection Method for Improving Power System Quality" *Electronics* 9, no. 1: 38.
https://doi.org/10.3390/electronics9010038