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A Cache Fill and Migration Policy for STT-RAM-Based Multi-Level Hybrid Cache in 3D CMPs

College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 211106, China
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Electronics 2019, 8(6), 639; https://doi.org/10.3390/electronics8060639
Received: 10 May 2019 / Revised: 27 May 2019 / Accepted: 4 June 2019 / Published: 6 June 2019
(This article belongs to the Section Computer Science & Engineering)
Recently, in 3D Chip-Multiprocessors (CMPs), a hybrid cache architecture of SRAM and Non-Volatile Memory (NVM) is generally used to exploit high density and low leakage power of NVM and a low write overhead of SRAM. The conventional access policy does not consider the hybrid cache and cannot make good use of the characteristics of both NVM and SRAM technology. This paper proposes a Cache Fill and Migration policy (CFM) for multi-level hybrid cache. In CFM, data access was optimized in three aspects: Cache fill, cache eviction, and dirty data migration. The CFM reduces unnecessary cache fill, write operations to NVM, and optimizes the victim cache line selection in cache eviction. The results of experiments show that the CFM can improve performance by 24.1% and reduce power consumption by 18% when compared to conventional writeback access policy. View Full-Text
Keywords: hybrid cache architecture; 3D CMP; NVM; cache fill; data migration hybrid cache architecture; 3D CMP; NVM; cache fill; data migration
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Ge, F.; Wang, L.; Wu, N.; Zhou, F. A Cache Fill and Migration Policy for STT-RAM-Based Multi-Level Hybrid Cache in 3D CMPs. Electronics 2019, 8, 639.

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