Next Article in Journal
Defect Estimation in Non-Destructive Testing of Composites by Ultrasonic Guided Waves and Image Processing
Next Article in Special Issue
Electronic Circuit with Controllable Negative Differential Resistance and its Applications
Previous Article in Journal
A Simplified Methodology to Evaluate Circuit Complexity: Doherty Power Amplifier as a Case Study
Article Menu
Issue 3 (March) cover image

Export Article

Electronics 2019, 8(3), 314; https://doi.org/10.3390/electronics8030314

Article
Low Cost Test Pattern Generation in Scan-Based BIST Schemes
1
School of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, China
2
School of Information and Engineering, Jimei University, Fujian 361021, China
3
Department of Chemical and Materials Engineering, National University of Kaohsiung, No. 700, Kaohsiung University Rd., Nan-Tzu District, Kaohsiung 811, Taiwan
*
Author to whom correspondence should be addressed.
Received: 26 January 2019 / Accepted: 8 March 2019 / Published: 12 March 2019

Abstract

:
This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.
Keywords:
test pattern generation; built-in self-test; broadcast circuit; low cost

1. Introduction

Nowadays VLSI testing is always used to ensure the correctness and reliability of the finished chip [1], but we encountered some problems during VLSI testing. In the process of chip testing, the test power consumption is two to four times greater compared with the normal power consumption [2,3]. This excessive power consumption will limit the stability of the circuit and it will also increase the cost of packaging [4]. In consideration of the economics of design for testability, we need to balance the cost and interest [5]. Therefore, this paper aims to find a low-cost test pattern generation method based on our previous work multiple single-input change (MSIC)-TPG [6].
The built-in self-test (BIST) method can effectively reduce the difficulty and complexity of VLSI testing. The BIST technology can be roughly divided into two categories: logic BIST (LBIST) and memory BIST (MBIST) [7,8]. The test pattern generation method proposed in this paper is based on the LBIST method. The traditional LBIST technology is based on the pseudo-random test patterns generated by the linear feedback shift register (LFSR) [9]. This will lead to a large test power consumption during the test. To solve this problem, a method of MSIC test pattern generation combining a pseudo-random sequence with a low-transition sequence has been proposed in paper [6]. It can consider both high fault coverage and low power consumption [10,11]. However, this method increases the area of circuits. To overcome the limitations, a novel low-cost BIST architecture using test pattern broadcast circuits called broadcast-based multiple single input charge (BMSIC)-TPG has been developed. This method reduces the area overhead, and it scores well in power consumption and fault coverage.
The rest of this paper is organized as follows. In Section 2, the proposed BMSIC-TPG scheme is presented. The mathematical features of the new BMSIC sequences is described in Section 3. In Section 4, the performance of the BMSIC sequences are analyzed. Conclusions are given in Section 5.

2. BMSIC-TPG Structure

2.1. BMSIC-TPG

The BMSIC-TPG structure includes a clock control module, an original scan chain generation module, and a broadcast module [12,13,14,15], as shown in Figure 1. The square A is the clock control module, which is used to generate a slow clock (CLK1) and a fast clock (CLK2). CLK1 is used to drive LFSR to update seed vectors [16], and CLK2 is used to drive reconstructed Johnson counter to update Johnson vectors and generate the vector J [17]. The square B is the original scan chain generation module, which is composed of the LFSR, the reconfigurable Johnson counter, and the exclusive OR (XOR) network [18]. The LFSR is used to generate the seed vector. The reconfigurable Johnson counter is used to generate the Johnson vector, and the XOR network generates the original scan chain vector by bitwise XOR operation of the seed vector S and the vector J. The square C is the broadcast module, which will broadcast m original scan chains to 4m broadcast scan chains [14]. The specific circuit is shown in Figure 3.
Suppose that there are m scan chains before broadcast and M scanning chains after broadcast, and each scanning chain has l scanning cells in a full scan design. The bits of seed vector S generated by LFSR is m. The bits of the vector J generated by reconfigurable Johnson counter is L.
Through many mathematical analyses and experiments, we know the solution to optimize the configuration of BMSIC-TPG is L = l , which is called the test convention constraint. Due to test pattern generation algorithm, the test pattern generator is constrained to have L m , which is called the test generation constraint, and must be satisfied compared with the test convention constraint. The test convention constraint is an optimal to generate the test pattern under the premise of satisfying the test generation constraint. Obviously, the two constraints are satisfied if L m . The configuration is the optimal configuration if L = l . If l < m , it just satisfies the test generation constraint L m (in this article L = m ). According to these constraints and the broadcast of test patterns we studied, we can find M = 4 m , the bits of the seed vector is m, the bits of the Johnson vector is L ( L = l ) , this is the premise of the follow-up contents. The above analysis result is also easy to understand. Under the premise that L m , the filling of the scan chain is realized by cyclic shifting of the updated current Johnson vector. The period of the cyclic shift is L. If L < l , the cyclic shift of the Johnson vector needs several shifting cycles, and the filling value will correspondingly appear repetitive parts. So the possibility of transition between adjacent bits of vectors generated after encoding will increase. If L = l , the cyclic shift of the Johnson vector is exactly a shift period, and the filled value is just all the bits of the Johnson vector. So this configuration can ensure low possibility of transition. If L > l , the cyclic shift of the Johnson vector is less than one shift period, and the filling value is part of the bits of Johnson vector. Thus, the possibility of transition will decrease. But this configuration will increase the area of the circuits. In this paper, the bits of seed vector and Johnson vector are always equal which is called the same scan configuration.

2.2. LFSR Structure and Johnson Counter Structure

The LFSR is composed of multiple shift registers and XOR gates connected in a certain way. The m-bit linear feedback shift register can generate ( 2 m 1 ) different states at most [19]. If the m-bit linear feedback shift register generates ( 2 m 1 ) different states and begins to repeat periodically, the ( 2 m 1 ) different states of the sequence is called the maximum length sequence, which is also known as the M sequence.
Because the number of transitions between adjacent bits of the test vector is positively correlated with the power consumption of the test [20], the Johnson counter can generate Johnson vectors that has low transition properties between adjacent vectors and adjacent bits of the same vector. The Johnson sequence is a single input change sequence (SIC). The vector generated by the next clock in the sequence is a one-bit change from the previous clock generation vector. Johnson sequences consist of a series of “0” and a series of “1”. So we choose a Johnson counter to reduce power consumption. But a simple Johnson counter can not complete the data shift loading process. We reconstruct the Johnson counter according to the test pattern generation method.
The L-bit reconfigurable Johnson counter is shown in Figure 2. When the mode is set to one, the counter implements the counting function. Under this mode, the initialization of all flip-flops will be completed after running L clocks if the Rst signal is set to zero. If the Rst signal is set to one, the counter implements the normal counting function. When the mode is set to zero, the counter implements a shift function and feeds the last bit of the counted vector back to the first bit. The adjacent bit of each Johnson vector jumps to zero or one, so the sequence generated by the reconfigurable Johnson counter still holds the single-hop characteristic.

2.3. XOR Network

The XOR network generates the original scan chain vector by bitwise XOR operation of the seed vector S which is generated by the LFSR and the vector J which is generated by the reconfigurable Johnson counter. The LFSR generates an m-bit seed vector S = [ S 0 , S 1 , S 2 , , S m 1 ] . The reconfigurable Johnson counter generates a L-bit vector J = [ J 0 , J 1 , J 2 , , J L 1 ] . The result of the bit-wise XOR operation is X = [ X 1 , X L + 1 , X 2 L + 1 , , X ( m 1 ) L + 1 ] .

2.4. Broadcaster

A broadcaster [12,13,14] distributes test patterns from a MSIC-TPG [6] module to fill multiple scan chains in a minimally constrained manner. The specific structure is shown in Figure 3. The broadcast circuit extends the original scan chains from two to eight. S 1 and S 2 are original scan chains. B 0 and B 1 are broadcast vectors which are generated by the two-bit LFSR. The post-broadcast seed vectors S 11 , S 12 , S 13 , S 14 and S 21 , S 22 , S 23 , S 24 to be applied to the scan chains are generated by bit-XOR the original scan chains S 1 and S 2 and the broadcast vectors B 0 and B 1 . Suppose the number of original scan chains is m, so the number of seed vectors after broadcast is M and M = 4 m .

2.5. The Process of BMSIC-TPG

What follows are the operation mode of the BMSIC-TPG.
  • Clock control module generates CLK1 and CLK2. CLK1 drives the LFSR to update the seed vector, and CLK2 drives the reconfigurable Johnson counter to update the J vector and enables the scan to move in.
  • Original scan chain generation module is made up of the LFSR, reconfigurable Johnson counter, and XOR network. The LFSR generates the S vector. The reconfigurable Johnson counter generates the J vector. The XOR network operates the bit-XOR between the S vector and the J vector to generate the original scan chain data.
  • Broadcast module is used to extend the original scan chain.

3. BMSIC-TPG Mathematical Features

3.1. Periodicity

Since the seed vectors, broadcast vectors, and original scan chain vectors before the broadcast are all periodic and the XOR operation is a linear operation, the BMSIC test pattern is also assumed to have periodic characteristics [6]. Suppose the seed vector is S = [ S 0 , S 1 , S 2 , , S m 1 ] . The vector J is J = [ J 0 , J 1 , J 2 , , J L 1 ] , and the broadcast vector B is B = [ B 0 , B 1 ] . Then at time t, S, J, and B can be expressed as:
S ( t , x ) = S 0 ( t ) x 0 + S 1 ( t ) x 1 + + S m ( t ) x m J ( t , x ) = J 0 ( t ) x 0 + J 1 ( t ) x 1 + + J L 1 ( t ) x L 1 B ( t , x ) = B 0 ( t ) x 0 + B 1 ( t ) x 1 .
According to the generation algorithm, the original input test vector consists of parts or all bits of the seed vector or multiplexing of seed vectors, which can be expressed as:
V i n ( t , x ) = S 0 ( t ) x 0 + S 1 ( t ) x 1 + + S m 1 ( t ) x m 1 + S 0 ( t ) x m + S 1 ( t ) x m + 1 + + S m 1 ( t ) x 2 m 1 + + S h ( t ) x N 1 .
In Equation (2), 1 h m and h is an integer. The specific value depends on the number of the original inputs N and the number of seed vectors m. At the same time, the k-th original scan chain vector can be expressed as:
C k ( t , x ) = [ i = 0 L 1 S k 1 ( t ) x i J k ( t , x ) ] x N + ( k 1 ) L .
The vector in Equation (3) represents the J vector applied to the k-th scan chain.
Assume that the two pre-broadcast original scan chain vectors S 1 , S 2 of the broadcaster shown in Figure 3 are denoted as C q ( t , x ) , C q + 1 ( t , x ) . The test vector of the i-th scan chain after broadcasting is V i ( t , x ) , then the eight scan chain vectors S 11 , S 12 , S 13 , S 14 , S 21 , S 22 , S 23 , S 24 after broadcasting can be expressed as:
S 11 = V 4 q 3 ( t , x ) = C q ( t , x ) j = 1 L B 1 ( t ) x j S 12 = V 4 q 2 ( t , x ) = C q ( t , x ) j = 1 L [ B 0 ( t ) B 1 ( t ) ] x j S 13 = V 4 q 1 ( t , x ) = C q ( t , x ) S 14 = V 4 q 3 ( t , x ) = C q ( t , x ) j = 1 L B 0 ( t ) x j S 21 = V 4 q + 1 ( t , x ) = C q + 1 ( t , x ) j = 1 L B 0 ( t ) x j S 22 = V 4 q + 2 ( t , x ) = C q + 1 ( t , x ) S 23 = V 4 q + 3 ( t , x ) = C q + 1 ( t , x ) j = 1 L [ B 0 ( t ) B 1 ( t ) ] x j S 24 = V 4 q + 4 ( t , x ) = C q + 1 ( t , x ) j = 1 L B 1 ( t ) x j .
Considering the above, the ω complete scan chain vector loaded into the circuit under test can be expressed as:
P ( ω ) = P ( t ω , x ) = V i n ( t ω , x ) + i = 1 M V i ( t ω , x ) .
Bit-XOR the ω th test pattern with the dth test pattern can be expressed as:
P ( ω ) P ( d ) = V i n ( t ω , x ) V i n ( t d , x ) + i = 1 M [ V i ( t ω , x ) V i ( t d , x ) ] .
Only if S ( t ω , x ) = S ( t d , x ) , B ( t ω , x ) = B ( t d , x ) , and l = 1 m C l ( t ω , x ) = l = 1 m C l ( t d , x ) are established at the same time, then P ( ω ) P ( d ) = 0 is established. It is known that the period of seed vector S is T S = 2 m 1 . The period of the broadcast vector B is T B = 2 2 1 = 3 . It is known from the literature [6] that the period of original scan chain vector S before broadcast is T M S I C = ( 2 m 1 ) 2 L . So the BMSIC test pattern is also periodic, and the period is the least common multiple of the period of seed vector, the broadcast vector and the original scan chain vector. It can be expressed as:
T B M S I C = ( 2 m 1 ) 2 L ( T M S I C % 3 = 0 ) ( 2 m 1 ) 6 L ( T M S I C % 3 0 ) .
From Equation (7), the period of the BMSIC test pattern is related to the number of bits of the seed vector and the J vector. Under the same configuration, the T B M S I C is larger than the T M S I C [6]. The greater the period of the test pattern is, the better the pseudo-randomness of the test pattern sample is, and the higher the fault coverage is. The number of bits in the seed vector S and J vectors directly affects the hardware overhead. The exponential relationship and multiple relationship of the Equation (7) make it possible to obtain a test pattern with large period and good pseudo-randomness with fewer vector bits, so BMSIC test patterns can reduce hardware overhead on the premise of achieving satisfactory fault coverage.

3.2. Transition

The number of transitions between adjacent bits of the test pattern is positively correlated with the power consumption of the test [20], so it can be used to quantitatively analyze the transition properties of the BMSIC test pattern. We take some test patterns under different scanning configurations as the samples and count the transition numbers for the BMSIC test generation method. We have obtained some statistical laws after our analysis. The results are shown in Table 1, and the “transition period” indicates how many test patterns the transition characteristics will repeat. “Pattern transitions” indicates the total transitions of a single test pattern.
We can make a conclusion from Table 1: (1) the transitions of per test pattern repeats with L for the transition period. (2) If L = m , the transition of one pattern is zero, and the transition of L 1 patterns is 8 ( m 1 ) . (3) If L > m , the transition of one pattern is zero. The transition of m patterns is 8 ( m 1 ) + 4 , and the transition of ( L m 1 ) patterns is 8 m . The above conclusion is derived because the BMSIC test pattern needs to satisfy both the test generation constraints and the test convention constraints. The average transition between the adjacent slices of the BMSIC test pattern is calculated as Equation (8), which is almost equivalent to the average transition of the MSIC [4] test pattern (shown in Equation (9)).
C B M S I C _ a v e = 8 ( m 1 ) L ( L = m ) 8 m ( L 1 ) 4 m L ( L 1 ) ( L > m ) .
C M S I C _ a v e = 2 ( M 1 ) L ( L = m ) 2 M ( L 1 ) M L ( L 1 ) ( L > m ) .

3.3. Randomness

The random sequence can detect most of the faults in CUT. Therefore, this paper discusses the randomness of the “0”, “1” distribution of BMSIC test patterns that have been generated to evaluate its capability to detect faults. The generated test pattern is evaluated from the scanning moving direction and the test pattern direction respectively according to the scanning test scheme and the scanning design technique.
As shown in Figure 4a, the randomness of scan moving direction is to calculate the probability of “0” or “1” of a given scan chain under each test pattern, which reflects the randomness of the same test pattern between its scan units on this scan chain. However, the randomness of scan moving direction does not reflect the randomness of the same scanning unit in the designated scan chain being filled with “0” or “1” under different test patterns, thus introducing the randomness of test pattern direction as shown in Figure 4b. The randomness of test pattern direction is to calculate the probability of “0” or “1” being filled in different test patterns for each scan unit in the specified scan chain, which reflects the difference between test patterns. We take 10,000 BMSIC test patterns and each test pattern has 32 scan chains as the samples and choose one chain to study. Then compare with LFSR and MSIC test patterns in the same configuration to reflect the performance of randomness. Other chains also has the similar result. The probability distribution of logic “0” in the scan moving direction is shown in Figure 5. It can be concluded BMSIC has a large fluctuation in randomness and has periodicity. The probability distribution of logic “0” in the test pattern direction is shown in Figure 6. It can be concluded the randomness of the test sequence arranged from good to bad is MSIC, BMSIC and LFSR, but the distributions are basically between 0.495 and 0.505, all have good randomness. So we consider the BMSIC test patterns have good fault detection capability.
The above analysis shows that BMSIC test patterns are good in randomness. Although it is based on a statistical approximation, it is necessary to evaluate the fault detection capability of test pattern. Therefore, it is speculated that BMSIC test patterns can achieve satisfactory fault coverage.

4. BMSIC-TPG Performance Analysis

BMSIC test patterns had low power consumption and low area overhead and it can achieve satisfactory fault coverage from theoretical analysis. This section verifies its fault coverage, power consumption, and area cost performance through the specific simulation experiments and performance estimates. The circuit under test (CUT) in the experiment are five circuits in ISCAS’89 series, using Nangate 45 nm process library. The synthesis of CUT were carried out with DFT_Compiler of Synopsys. Test generation and test application were carried out with Perl. The fault simulation was carried out with TetraMAX. The power consumption simulation was carried out with the Synopsys Design Analyzer and Prime Power. Because the BMSIC-TPG proposed in this paper was designed to overcome the drawback of the previous method [6], we compare the performance of BMSIC with our previous method [6].

4.1. Fault Simulation

The fault simulation results of the BMSIC test generation method are shown in Table 2. DFF represents the number of scanning units in the circuit under test. Chain represents the number of scan chains. Depth represents the number of scanning units per scan chain. TL represents the number of test patterns, and SFC and TFC represent stuck fault coverage and transition fault coverage respectively.
We used DFT_Compiler of synopsys to synthesize the CUT, Perl to implement test patterns generation algorithm to achieve test generation, test application, and TetraMAX to complete the fault simulation, the results are shown in Table 2. Comparing with the literature [6], BMSIC test program can achieve higher fault coverage under the same configuration. Comparing with the literature [21], we needed less test patterns to achieve high fault coverage. At the same time, we found that the same CUT under different test generation configuration resulted in different fault coverage, indicating that the fault coverage is related to test generation configuration.

4.2. Power Consumption Simulation

The power simulation results of the BMSIC test generation method are shown in Table 3. The test frequency was 100 MHz, and the power supply voltage was 1.1 V. Table 3 shows the total power consumption and peak power consumption caused by the three test generation methods: LFSR, MSIC, and BMSIC. From Table 3, the BMSIC test pattern generation circuit has obvious advantages in terms of the total power consumption and the peak power consumption compared with the LFSR generation method. The MSIC generation method was better in power consumption compared with BMSIC generation method. But the difference is not particularly obvious.

4.3. Area Overhead Evaluation

The hardware area cost of the three test patterns are shown in Table 4. The unit is the area of a two-input XOR gate. The “reduction” indicates the percentage reduction in area of BMSIC compared with MSIC. From the analysis of Table 4, BMSIC method had a great advantage in an equivalent scan configuration, and it can reduce the area overhead by about 50% in the best case.

5. Conclusions

This paper proposes a low-cost test pattern generation method BMSIC-TPG based on our previous work MSIC-TPG, which can take into account both low power consumption and satisfactory fault coverage [6]. The hardware overhead of the proposed MSIC-TPG is reduced by inserting a broadcaster between the MSIC-TPG module and the CUT. The inserted broadcaster is responsible for distributing test patterns from a MSIC-TPG module to fill a larger number of scan chains. By the introduction of the broadcaster, one original scan chain can be split into several shorter scan chains in a balanced way. Analysis results show that BMSIC sequences have the favorable features of uniform distribution and low input transition density. Compared with MSIC-TPG, experimental results show that in most cases, hardware overhead is reduced by 50% and fault coverage is higher. This is achieved with a little increase in test power and no increase in test length to hit a target fault coverage. For the larger CUT, the performance of the proposed BMSIC-TPG in area overhead is better.

Author Contributions

Conceptualization, G.Z. and F.L.; formal analysis, Y.Y.; funding acquisition, F.L.; investigation, S.W.; methodology, S.W.; project administration, C.-F.Y.; resources, C.-F.Y.; validation, G.Z.; writing—original draft, Y.Y.; writing—review and editing, F.L. and Y.Y.

Funding

This research was partly supported by the Core Electronic Devices, High-end General Chips and Basic Software Products Projects of China (2017ZX01030204) and the National Natural Science Foundation of China under Grant 61474093.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Takahashi, Y.; Maeda, A. Multi Domain Test: Novel test strategy to reduce the Cost of Test. In Proceedings of the 29th VLSI Test Symposium, Dana Point, CA, USA, 1–5 May 2011; pp. 303–308. [Google Scholar]
  2. Dutta, A.; Kundu, S.; Chattopadhyay, S. Thermal Aware Don’t Care Filling to Reduce Peak Temperature and Thermal Variance during Testing. In Proceedings of the 2013 22nd Asian Test Symposium, Jiaosi Township, Taiwan, 8–21 November 2013; pp. 25–30. [Google Scholar]
  3. Puczko, M. Low power test pattern generator for BIST. In Proceedings of the 2015 Selected Problems of Electrical Engineering and Electronics (WZEE), Kielce, Poland, 7–19 September 2015; pp. 1–6. [Google Scholar]
  4. Bushnell, M.; Agrawal, V. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits; Springer Publishing Company, Incorporated: New York City, NY, USA, 2013. [Google Scholar]
  5. Lei, S.C.; Shao, Z.B.; Liang, F. VLSI Testing; Publishing House of Electronic Industry: Beijing, China, 2008. [Google Scholar]
  6. Liang, F.; Zhang, L.; Lei, S.; Zhang, G.; Gao, K.; Liang, B. Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2013, 21, 614–623. [Google Scholar] [CrossRef]
  7. McLaurin, T. Periodic Online LBIST Considerations for a Multicore Processor. In Proceedings of the 2018 IEEE International Test Conference in Asia (ITC-Asia), Harbin, China, 15–17 August 2018; pp. 37–42. [Google Scholar]
  8. Shirur, Y.J.M.; Bhimashankar, B.C.; Chakravarthi, V.S. Performance analysis of low power microcode based asynchronous P-MBIST. In Proceedings of the 2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI), Kochi, India, 10–13 August 2015; pp. 555–560. [Google Scholar]
  9. Datta, D.; Datta, B.; Dutta, H.S. Design and implementation of multibit LFSR on FPGA to generate pseudorandom sequence number. In Proceedings of the 2017 Devices for Integrated Circuit (DevIC), Kalyani, India, 23–24 March 2017; pp. 346–349. [Google Scholar]
  10. Seo, S.; Lee, Y.; Lee, J.; Kang, S. A scan shifting method based on clock gating of multiple groups for low power scan testing. In Proceedings of the Sixteenth International Symposium on Quality Electronic Design, Santa Clara, CA, USA, 2–4 March 2015; pp. 162–166. [Google Scholar]
  11. Xiang, D.; Wen, X.; Wang, L. Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2017, 25, 942–953. [Google Scholar] [CrossRef]
  12. Lee, K.J.; Chen, J.J.; Huang, C.H. Broadcasting test patterns to multiple circuits. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 1999, 18, 1793–1802. [Google Scholar]
  13. Jeníček, J.; Novák, O.; Chloupek, M. Advanced scan chain configuration method for broadcast decompressor architecture. In Proceedings of the 2011 9th East-West Design Test Symposium (EWDTS), Sevastopol, Ukraine, 9–12 September 2011; pp. 140–143. [Google Scholar]
  14. Gu, X.; Sheu, B.; Wang, Z.; Wang, L.; Wu, S.; Wen, X.; Jiang, Z. VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. IEEE Des. Test Comput. 2008, 25, 122–130. [Google Scholar]
  15. Chen, J.; Lee, K. Test Stimulus Compression Based on Broadcast Scan With One Single Input. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 2017, 36, 184–197. [Google Scholar] [CrossRef]
  16. Pomeranz, I. Computing Seeds for LFSR-Based Test Generation From Nontest Cubes. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2016, 24, 2392–2396. [Google Scholar] [CrossRef]
  17. Singh, S.; Kaur, S.; Kaur, R.; Kaler, R.S. Photonic processing of all-optical Johnson counter using semiconductor optical amplifiers. IET Optoelectron. 2017, 11, 8–14. [Google Scholar] [CrossRef]
  18. Stoev, I.I.; Borodzhieva, A.N.; Mutkov, V.A. FPGA Implementation of Johnson Counters Applied in the Educational Process. In Proceedings of the 2018 IEEE 24th International Symposium for Design and Technology in Electronic Packaging (SIITME), Iasi, Romania, 25–28 October 2018; pp. 99–103. [Google Scholar]
  19. Touba, N.A. Survey of Test Vector Compression Techniques. IEEE Des. Test Comput. 2006, 23, 294–303. [Google Scholar] [CrossRef]
  20. Girard, P.; Landrault, C.; Pravossoudovitch, S.; Severac, D. Reducing power consumption during test application by test vector ordering. In Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187), ISCAS ’98, Monterey, CA, USA, 31 May–3 June 1998; Volume 2, pp. 296–299. [Google Scholar]
  21. Nourani, M.; Tehranipoor, M.; Ahmed, N. Low-Transition Test Pattern Generation for BIST-Based Applications. IEEE Trans. Comput. 2008, 57, 303–315. [Google Scholar] [CrossRef][Green Version]
Figure 1. Broadcast-based multiple single input charge (BMSIC)-TPG structure.
Figure 1. Broadcast-based multiple single input charge (BMSIC)-TPG structure.
Electronics 08 00314 g001
Figure 2. L-bit reconfigurable Johnson counter structure.
Figure 2. L-bit reconfigurable Johnson counter structure.
Electronics 08 00314 g002
Figure 3. Broadcast circuit.
Figure 3. Broadcast circuit.
Electronics 08 00314 g003
Figure 4. (a) Scan moving direction randomness analysis diagram. (b) Test pattern direction randomness analysis diagram.
Figure 4. (a) Scan moving direction randomness analysis diagram. (b) Test pattern direction randomness analysis diagram.
Electronics 08 00314 g004
Figure 5. Scan moving direction Logic “0” probability distribution.
Figure 5. Scan moving direction Logic “0” probability distribution.
Electronics 08 00314 g005
Figure 6. Test pattern direction Logic “0” Probability distribution.
Figure 6. Test pattern direction Logic “0” Probability distribution.
Electronics 08 00314 g006
Table 1. Transition of the broadcast-based multiple single input charge (BMSIC)-TPG.
Table 1. Transition of the broadcast-based multiple single input charge (BMSIC)-TPG.
Seed Vector BitsJohnson Vector BitsTransition PeriodPattern NumbersPattern Transitions
88810
756
8171710
860
864
8202010
860
1164
10101010
990
10363610
1076
2580
10444410
1076
3380
Table 2. Comparison of fault coverage of the three test generation methods.
Table 2. Comparison of fault coverage of the three test generation methods.
CUTDFFChainDepthTLLFSRMSIC [6]BMSIC
SFCTFCSFCTFCSFCTFC
S13207638322010,00091.4480.7590.5174.391.4274.02
361810,00092.0180.3386.6371.1192.673.57
401610,00095.2484.0589.2270.8293.5277.71
S15850534321710,00093.985.5592.0178.3689.4575.12
361510,00093.8285.5591.2376.7991.7977.01
401410,00094.6986.5990.1173.1993.5980.60
S359321728404410,00099.5597.0497.3486.2899.9795.99
483610,00099.6096.6699.9493.9999.9892.04
563110,00099.5696.3497.7788.799.9894.53
S384171636404110,00093.4883.6783.6959.1184.6560.4
483510,00093.6883.1885.3361.6885.2261.58
563010,00093.6682.8784.3461.0983.4652.74
S385841426403610,00095.9990.5193.3976.697.3281.31
483010,00096.0190.9995.3682.498.0084.67
562610,00097.1792.1595.2382.1198.1690.04
Table 3. Comparison of power simulation results of the three test generation methods.
Table 3. Comparison of power simulation results of the three test generation methods.
CUTDFFChainDepthPrimepower
Total ( μ W )Peak ( μ W )
LFSRMSIC [6]BMSICLFSRMSIC [6]BMSIC
S132076383220116.61105.89107.786891.835535.755582.29
3618116.39104.75107.726818.385737.825617.09
4016116.59104.51108.207337.725536.475617.74
S158505343217109.2696.499.316633.735137.785429.68
3615108.5995.1399.416518.925026.075396.98
4014109.0994.899.136656.535442.835345.9
S3593217284044320.86276.83272.2620,835.317,317.119,303.6
4836322.54275.91277.2521,014.814,695.919,864.5
5631322.22274.54282.0721,380.525,411.320,922.4
S3841716364041347.57280.81286.9820,349.817,630.417,503.9
4835347.32282.52286.9220,578.517,081.916,952.8
5630346.68280.41289.1719,97917,425.517,150.1
S3858414264036335.26286.89292.921,125.515,583.218,163.6
4830335.46287.13293.9520,058.915,768.917,835.2
5626335.43285.67291.3920,011.916,110.715,692.3
Table 4. Area Overhead Comparison of the three test generation methods.
Table 4. Area Overhead Comparison of the three test generation methods.
CUTChainDepthLFSRMSIC [6]BMSICReduction (%)
SLAreaSLAreaSLArea
S13207322032094323221882013139.9
3618360103363624391813146.09
40164001164040271101613350.92
S15850321732094323221881712244.04
3615360103363624391512249.79
40144001164040271101412753.14
S3593240444001164044283104421225.09
48364801394848325123620736.31
56315601615656378143120944.71
S3841740414001164041274104120425.55
48354801394848325123520536.92
56305601615656378143020645.5
S3858440364001164040271103619029.89
48304801394848325123019041.54
56265601615656378142619548.41

© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
Electronics EISSN 2079-9292 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top