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Low Cost Test Pattern Generation in Scan-Based BIST Schemes

School of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, China
School of Information and Engineering, Jimei University, Fujian 361021, China
Department of Chemical and Materials Engineering, National University of Kaohsiung, No. 700, Kaohsiung University Rd., Nan-Tzu District, Kaohsiung 811, Taiwan
Author to whom correspondence should be addressed.
Electronics 2019, 8(3), 314;
Received: 26 January 2019 / Revised: 28 February 2019 / Accepted: 8 March 2019 / Published: 12 March 2019
(This article belongs to the Special Issue Intelligent Electronic Devices)
PDF [1014 KB, uploaded 14 March 2019]
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This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage. View Full-Text
Keywords: test pattern generation; built-in self-test; broadcast circuit; low cost test pattern generation; built-in self-test; broadcast circuit; low cost

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Zhang, G.; Yuan, Y.; Liang, F.; Wei, S.; Yang, C.-F. Low Cost Test Pattern Generation in Scan-Based BIST Schemes. Electronics 2019, 8, 314.

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