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Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications

Department of information and communication, Chaoyang University of Technology, Taichung 41349, Taiwan
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Electronics 2019, 8(12), 1429; https://doi.org/10.3390/electronics8121429
Received: 7 November 2019 / Revised: 22 November 2019 / Accepted: 26 November 2019 / Published: 30 November 2019
(This article belongs to the Section Circuit and Signal Processing)
In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz. View Full-Text
Keywords: multiplier; latch-adder; low voltage; low power multiplier; latch-adder; low voltage; low power
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Lin, J.-F.; Chan, C.-Y.; Yu, S.-W. Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications. Electronics 2019, 8, 1429.

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