# A Millimeter-Wave Fundamental Frequency CMOS-Based Oscillator with High Output Power

^{1}

^{2}

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## Abstract

**:**

## 1. Introduction

_{max}) where unilateral power gain becomes unity [18,19,20].

_{max}of the CMOS technology, generates a low output power of −4.8 dBm at the 2nd harmonic frequency of 239 GHz. However, the generated output power from the harmonic oscillator is low. Another oscillator in [29] generates an output power of −3.8 dBm at the 2nd harmonic frequency of 163.5 GHz at a typical supply voltage of 1.2 V. However, the maximum output power of 1 dBm at 164.6 GHz was measured at the supply voltage of 2 V, which is much higher than the typical supply voltage guaranteed in a 65 nm CMOS process, which can cause voltage stress and raise reliability problems in active devices. In [25], another approach, a fundamental frequency cross-coupled oscillator (XCO) with a capacitive-load-reduction-circuit (CLRC) technique, was presented to address the limitations of the CMOS technology. This approach improves the oscillation frequency by suppressing the effect of the load capacitance on the oscillation frequency. Moreover, a differential to single (DTS) transformer is adopted at the output port of the presented topology to enhance the output power.

## 2. The Proposed Millimeter-Wave Oscillator

_{1}–M

_{2}), an inductor L

_{tank}, and two buffer transistors (M

_{3}–M

_{4}). In the conventional XCO, the buffer transistors are directly connected to the main resonant tank, so the parasitic capacitance C

_{GS}at the gate terminals of buffer transistors decrease the fundamental oscillation frequency. Figure 1b shows the schematic the XCO with CLRC [25]. In the XCO with CLRC, the CLRC comprises the gates of buffer transistors that are connected to the main resonant tank through a transformer. The transformer in the CLRC couples with the signal from a primary winding L

_{1}to a secondary winding L

_{2}, by a coupling factor k

_{1}. The function of CLRC is to suppress the effect of the load capacitance on the fundamental oscillation frequency [25]. The DTS transformer is constructed by L

_{3}and L

_{4}, at the output port to improve the output power by converting two differential signals into one single-ended signal. As a result, the oscillation frequency and the output power of the XCO with CLRC are higher than that of the conventional XCO.

_{5}–M

_{6}) and an inductor L

_{g}that is connected at the gate terminals of M

_{5}and M

_{6}. Resistors are connected to the center taps of L

_{2}and L

_{g}to guarantee the differential mode operation by suppressing the common mode operation of the proposed oscillator. These resistors also protect transistors from breakdown by limiting the inrush current flowing from a power supply to the gates of the transistors at the turn-on moment.

_{g}is half of L

_{g}in the proposed oscillator. The FSNR circuit provides a selective characteristic depending on the oscillation frequency [12]. Figure 2b shows a small signal equivalent circuit of the half-circuit FSNR. A parasitic capacitance C

_{gs}and a dependent current source g

_{m}V

_{1}are the only components accounted for in the small-signal equivalent circuit of a transistor to simplify the analysis and to obtain meaningful and tractable equations. The calculation of the input impedance looking at the source terminal of the transistor of the half circuit FSNR is based on the small-signal equivalent circuit in Figure 2b. The calculated input impedance of this circuit has two solutions. When the oscillation frequency of oscillator ω is lower than $\sqrt{2/LgCgs}$, the input impedance of the half circuit FSNR, shown in Figure 2c, is equivalent to a capacitor in parallel with a lossy resistance. Due to the lossy resistance, the total equivalent negative resistance is decreased, so the output power is decreased. In contrast, when $\omega >\sqrt{2/LgCgs}$, the input impedance of the half-circuit FSNR is equivalent to an inductor in parallel with a negative resistance as shown in Figure 2d. The solution in the case of $\omega >\sqrt{2/LgCgs}$ is preferred because it provides a high oscillation frequency and a high output power that are crucial in the mm-wave oscillator design.

_{tank}is the total inductance value of the oscillator tank, C

_{tank}is the total capacitance value of the oscillator tank, and C

_{L}is the total load capacitance. From Figure 3b, the oscillation frequency of the XCO witch CLRC is:

_{1}is the total inductance value of the oscillator tank, L

_{2}is the total inductance value at the gate of the buffer transistor, and mutual conductance ${M}_{1}={k}_{1}\sqrt{{L}_{1}{L}_{2}}$ with k

_{1}being the coupling factor between L

_{1}and L

_{2}. From Figure 3c, the oscillation frequency of the proposed oscillator is:

_{gs}is the gate-source capacitance of transistors (M

_{5}–M

_{6}), L

_{g}is the inductor at the gate terminal of transistors (M

_{5}–M

_{6}).

_{g}from Equations (1)–(3) with g

_{m}= 8 mS, C

_{tank}= C

_{L}= 10 fF, C

_{gs}= 9 fF, L

_{tank}= L

_{1}= L

_{2}= 40 pH, and M

_{1}= 20 pH. In Figure 4a, the oscillation frequency of the proposed oscillator decreases with an increase of L

_{g}. As can be seen in Figure 4a, the oscillation frequency of the proposed oscillator is 230 GHz at L

_{g}= 80 pH which is 62% and 87% higher than the oscillation frequency of the XCO with CLRC (142 GHz) and the conventional XCO (123 GHz), respectively. The circuit simulation was also carried out to verify the validity of the theory and the simulation results are plotted in Figure 4a. A BSIM4 model transistor was used in the circuit simulation. The simulation results agree with the theory equation about the trend of the oscillation frequency of the prosed oscillator with the change of L

_{g}. The simulated oscillation frequency of the proposed oscillator is lower and decreases more rapidly than the calculated oscillation frequency. This discrepancy is due to the simplification in the small-signal equivalent model of transistor. Nonetheless, the simulation results still show that the proposed oscillator has a higher oscillation frequency than that of the others, overall, in the simulated range of L

_{g}. To operate around 200 GHz, an inductance value smaller than 100 pH of L

_{g}was selected.

_{m}while that of the proposed oscillator is −2/g

_{m}‖2(1−C

_{gs}L

_{g}ω

^{2})/g

_{m}. An additional negative resistance 2(1−C

_{gs}L

_{g}ω

^{2})/g

_{m}generated from the FSNR circuit gives rise to a better start-up condition and higher output power in the proposed oscillator. The circuit simulation was performed to verify the negative conductance improvement of the proposed oscillator. The simulated negative conductance of three structures with an identical oscillation frequency of 200 GHz is shown in Figure 4b. At 200 GHz target frequency, the negative resistance of the conventional XCO and XCO with CLRC is −2.2 mS and −2.9 mS, respectively, whereas the negative resistance of the proposed oscillator is −11.3 mS, as shown in Figure 4b. Therefore, the negative resistance of the proposed oscillator is almost 4 times higher than that of the XCO with CLRC, and five times higher than that of the conventional XCO.

_{1}is 35 and Q-factor of L

_{2}is 43. When the space between the primary inductor L

_{1}and secondary inductor L

_{2}is 3 μm, the coupling factor k

_{1}is 0.4. The gate inductor L

_{g}is also implemented on the UTM metal layer with an inductance value of 88 pH and a Q-factor of 34. The DTS transformer is implemented as a vertical stack structure to maximize the coupling factor, and, thus, the DTS transformer has a high coupling factor k

_{2}of 0.73. A capacitor with the capacitance value of 5 fF is implemented at the output port of the DTS transformer to maximize the output power transferred to the output load.

## 3. Measurement Results

^{2}. The area of the output pad is designed smaller than the power pads (V

_{DD}and V

_{C}) and ground pads (GND) to minimize parasitic capacitance and loss due to coupling with the lossy substrate.

_{DD}was increased from 1.4 to 2.8 V. At V

_{DD}= 2.8 V, the measured oscillation frequency was 10 GHz lower than the simulated oscillation frequency because of the extrapolation model of active devices at mm-wave frequency range.

_{DD}= 2.8 V and V

_{C}= 1 V. At V

_{DD}= 2.8 V, the voltage across each transistor was approximately 1.4 V because of the stack structure. Figure 9b shows the effect of voltage supply on output power. The measured output power increased from 0.254 to 0.6 mW and the simulated output power increased from 1.1 to 5.9 mW when V

_{DD}increased from 1.4 to 2.8 V. The large discrepancy between the measured output power and the simulated output power was due to the extrapolation model of active devices at mm-wave frequency range.

## 4. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 1.**Schematics of (

**a**) the conventional XCO; (

**b**) the XCO with CLRC; (

**c**) the proposed oscillator.

**Figure 2.**(

**a**) The FSNR circuit; (

**b**) its equivalent small-signal circuit, equivalent circuit of FSNR with; (

**c**) capacitive reactance, and; (

**d**) inductive reactance.

**Figure 3.**Small signal equivalent circuits of: (

**a**) conventional XCO; (

**b**) XCO with CLRC; (

**c**) proposed oscillator.

**Figure 4.**(

**a**) Calculation and simulation results of oscillation frequency with various inductance values of L

_{g}; and (

**b**) simulation results of the negative transconductance of conventional XCO, XCO with CLRC, and the proposed oscillator.

**Figure 9.**(

**a**) Measured oscillation frequency and simulated oscillation frequency; (

**b**) measured output power and simulated output power of the proposed oscillator with the change of voltage supply V

_{DD}.

[27] | [28] | [29] | [25] | This Work | |
---|---|---|---|---|---|

Technology | 0.13 μm SiGe | 65 nm CMOS | 65 nm CMOS | 65 nm CMOS | 65 nm CMOS |

Harmonic | 2nd Harmonic | 2nd Harmonic | 2nd Harmonic | Fundamental | Fundamental |

Frequency (GHz) | 190.5 | 239 | 164.6 | 219 | 190 |

P_{out} (dBm) | −2.1 | −4.8 | 1 | −3 | −2.2 |

# cores | 1 | 1 | 1 | 1 | 1 |

DC Power (mW) | 183/294 | 18.5 | 88 | 24 | 100 |

DC-to-RF eff. (%) | 0.22 | 1.79 | 1.43 | 2 | 0.6 |

Area (mm^{2}) | 0.64 | 0.18 | 0.1 | 0.105 | 0.1 |

Measurement | Probe | Probe | Probe | Probe | Probe |

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**MDPI and ACS Style**

Nguyen, T.D.; Park, H.; Hong, J.-P.
A Millimeter-Wave Fundamental Frequency CMOS-Based Oscillator with High Output Power. *Electronics* **2019**, *8*, 1228.
https://doi.org/10.3390/electronics8111228

**AMA Style**

Nguyen TD, Park H, Hong J-P.
A Millimeter-Wave Fundamental Frequency CMOS-Based Oscillator with High Output Power. *Electronics*. 2019; 8(11):1228.
https://doi.org/10.3390/electronics8111228

**Chicago/Turabian Style**

Nguyen, Thanh Dat, Hangue Park, and Jong-Phil Hong.
2019. "A Millimeter-Wave Fundamental Frequency CMOS-Based Oscillator with High Output Power" *Electronics* 8, no. 11: 1228.
https://doi.org/10.3390/electronics8111228