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An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell

1
Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
2
School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, Beijing 100049, China
3
Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230026, China
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(10), 1129; https://doi.org/10.3390/electronics8101129
Received: 29 August 2019 / Revised: 29 September 2019 / Accepted: 4 October 2019 / Published: 7 October 2019
(This article belongs to the Section Microelectronics and Optoelectronics)
In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed CSLAs reduced power consumption by 68.4–72.2% with a slight delay increase for different bit widths. As the dual carry adder had much fewer transistors than the two regular full adders, the area of the proposed CSLAs was reduced by 45.8–51.1%. The area-power-delay product of the proposed CSLA improved 5.1×–6.73× compared with the regular CSLA. View Full-Text
Keywords: carry select adder; low power; area efficient; hybrid logic carry select adder; low power; area efficient; hybrid logic
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MDPI and ACS Style

You, H.; Yuan, J.; Tang, W.; Qiao, S. An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell. Electronics 2019, 8, 1129.

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