Area Efficient Dual-Fed CMOS Distributed Power Amplifier
AbstractIn this paper, an area-efficient 4-stage dual-fed distributed power amplifier (DPA) implemented in a 0.35 μm Complementary Metal Oxide Semiconductor (CMOS) process is presented. To effectively reduce the area of the circuit, techniques such as using multilevel inductors and closely-placing conventional spiral inductors are employed. Additionally, a novel technique based on stacking inductors one on top of others is implemented. Based on these techniques, a 32% area reduction is achieved compared to a conventional design without a noticeable performance degradation. This reduction could be further exploited as the number of stages of the dual-fed DPA increases. View Full-Text
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Pino, J.D.; Khemchandani, S.L.; Mateos-Angulo, S.; Mayor-Duarte, D.; San-Miguel-Montesdeoca, M. Area Efficient Dual-Fed CMOS Distributed Power Amplifier. Electronics 2018, 7, 139.
Pino JD, Khemchandani SL, Mateos-Angulo S, Mayor-Duarte D, San-Miguel-Montesdeoca M. Area Efficient Dual-Fed CMOS Distributed Power Amplifier. Electronics. 2018; 7(8):139.Chicago/Turabian Style
Pino, Javier D.; Khemchandani, Sunil L.; Mateos-Angulo, Sergio; Mayor-Duarte, Daniel; San-Miguel-Montesdeoca, Mario. 2018. "Area Efficient Dual-Fed CMOS Distributed Power Amplifier." Electronics 7, no. 8: 139.
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