The fault-tolerant capability and effectiveness of the proposed strategy, i.e., STFCL with PR based on RHC, is carried out by analyzing and comparing it with conventional PI and crowbar FRT strategies. A three-phase PVS is subjected with asymmetrical faults that occur at PCC and 19 km from PCC. The faults at the grid are imposed for 150 ms, which are applied at 0.1 s. For better understanding, the fault of PI with FRT and PR with FRT is cleared at 0.3 s, to avoid congestion at the single point 0.25 s. The behavior and comparison of the proposed approach with conventional approaches are graphically discussed, and also analyzed through performance measures as noted below.
3.1. Single-Phase to Ground Fault
The single-phase to ground (S–G) fault is applied on the PCC and distribution line. The results of fault that occur at the PCC and distribution line are depicted in
Figure 8a,b respectively. The figure shows the response of different control strategies and FRT schemes on DC link voltage. The response of PR and PR with STFCL is the same in pre-fault, during fault, and post-fault conditions. However, the response of a PR with FRT controller alone and PI with FRT shows the emergence of transients during fault clearance. The PCC fault shows little influence of DC link voltage. Only the control strategy without FRT can keep the DC link voltage at the reference value. Similarly, all the different control strategies and FRT schemes show the same response in the case of fault occurring in the distribution line. However, in this case the DC link voltage is subjected to oscillation with a larger amplitude, as compared to fault occurred at PCC. However, the proposed strategy of PR with STFCL is reluctant to fault. Hence, this reduces the amplitude of oscillation occurring in DC link voltage during fault, as shown in
Figure 8b.
Performance evaluation of the proposed strategy with other configurations is carried out in
Table 1 for DC link voltage (
VDC). In the performance evaluation in
Table 1, three control measures—i.e., integral absolute error (IAE), integral square error (ISE), and integral time-weighted absolute error (ITAE) are calculated for all cases, which gives a very precise and exact comparison between the different combinations of controllers and FRT strategies. The lower values of ITAE, ISE and IAE authenticate the higher efficiency. The PI + STFCL and PR + STFCL strategies give better performances when compared with PI + FRT and PR + FRT, as tabulated in
Table 1 for
VDC.
Figure 9a,b shows the simulated response for the PR with RHC controller, with FRT and STFCL schemes, respectively. These responses are presented for fault occurring at PCC. The response of the PR controller accompanied with an FRT scheme shows oscillation during fault, followed by current spike at fault clearance. However, the inductive effect of STFCL opposes the change in current, hence the response of the
Id current results in low-amplitude oscillations. Similarly,
Figure 9c,d shows the response of the
d-axis current during the occurrence of fault at the distribution line.
Figure 9c depicts the response of
Id in the case of a PR controller with FRT, while
Figure 9d shows the response of
Id in the case of a PR controller with STFCL. Both the responses of
Id currents are the same during fault, except the amplitude of oscillation. The STFCL has ability to dampen the oscillation, as compared to FRT. Hence, the oscillation occurring in the case of STFCL has a lower amplitude, comparatively. The reactive component
Iq from
Figure 9e at PCC results in smooth and spike-free responses with the proposed PR with RHC controller with STFCL strategy. However, the conventional FRT strategy with any of the controllers give spikes after fault clearance. The statement is same for faults at 19 km at the distribution line from PCC, as depicted in
Figure 9f.
Performance evaluation of the proposed strategy with other configurations is carried out in
Table 2 for the active component of the current (
Id).
Table 2 authenticates the better performance of the proposed strategy and controller for
Id.
Moreover, performance evaluations for reactive current components for all possible configurations are depicted by
Table 3. The PI with STFCL and PR with STFCL strategy gives better performances when compared with the PI with FRT and PR with FRT strategies, as tabulated in
Table 3 for
Iq.
Figure 10 depicts grid power behavior during S–G fault, which shows a stable and oscillation-free power response with STFCL along with PR, except for minor oscillations at fault occurring and clearing time. However, with FRT strategies, any of the controllers have an increase in power response, with approximately 35% spikes after fault clearance for 0.05 s, as cleared from
Figure 10a. So far, at a 19 km distance, the case is the same as for STFCL, but a little wavy for the crowbar, as compared to PCC shown by
Figure 10b.
Figure 11 depicts the grid current and voltage for both configuration of controllers and FRT strategies. By simulation results, it was found that high fault currents are optimized to nominal values along and enhancing the voltage drop during fault. Where STFCL gives optimized and ripple-free behavior, the crowbar strategy gives spikes at the PCC, as shown by
Figure 11a,b. Whereas for 19 km from the PCC, current wave form depletes from the reference after fault clearance, STFCL maintains its reference, as illustrated by
Figure 11c. The grid voltage for 19 km gives some value instead of zero, as in the PCC, due to the line resistance shown by
Figure 11d.
Figure 12 depicts the grid frequency response during S–G fault, which clearly shows that the oscillations in frequency account for approximately 0.4% of the rated frequency with crowbar as the FRT strategy throughout the fault time at the PCC. However, with STFCL along PR as a controller, the oscillations are limited to 0.2%, and only at fault entering time, as in
Figure 12a. It is also depicted that STFCL responds well with PR, as compared to PI. Although at a distance of 19 km from PCC, these variations increase to approximately double, as in the PCC shown by
Figure 12b.
The impact of crowbar and STFCL strategies are illustrated by
Figure 13 at the PV side, which clearly highlights the spikes for 0.05 s as fault clearing surges. The PV side parameter likes PV power, current, and voltage, for the STFCL strategy gives a smooth and transient-free response throughout operation at the PCC. The response is approximately same for 19 km distance as in PCC.
3.2. Phase-to-Phase Fault
The DC link voltage spikes less in response during phase-to-phase (P–P) fault clearing time with the proposed STFCL strategy in combination with a PR controller, and without rising at fault duration. Unlike all other configurations, as depicted by
Figure 14, the response is same at 19 km of distance from the PCC as at the PCC.
As mentioned above, in single phase to ground(P–G) fault the reference frame current components i.e.,
Id and
Iq have approximately the same response with respect to location of fault; the case is same for P–P. So here, information needed to analyze the effects with respect to fault type at the PCC is given by
Figure 15. The conventional crowbar strategy with PR controller gives high oscillations during fault duration, along with a fault-clearing surge for 0.05 s after the fault is cleared. However, comparatively the proposed STFCL with PR strategy has fewer oscillations during fault, delaying fault clearing spikes instead for an instant. Moreover, the proposed strategy gives smooth and surge-free responses in during P–P fault as well, as depicted by
Figure 15c.
The active grid power during P–P fault falls near 20% of the rated value; however, with the STFCL strategy and PR as a controller, this deficiency remains approximately 10%, with an increasing spike for 0.04 s and then attaining its reference value. Moreover, with the crowbar strategy an increase of 20% can be seen by
Figure 16 during the fault time, along with alternating spikes for 0.07 s after fault clearance at 0.3 s. However, grid power is less effected with respect to distance, as shown by comparing
Figure 16a,b.
Figure 17 presents grid voltage and current wave form, comparing the LVRT improvement through the proposed STFCL, including a PR controller with the crowbar strategy as FRT. During P–P fault time, the crowbar topology with any of the controller faces a phase shift of 80 degrees at grid voltage and current. However, the proposed topology is free of any surges or phase shifts. Furthermore, grid voltage and current have negligible variations at 19 km of distance from the PCC.
The distortion in frequency to achieve LVRT capability by inducing FRT strategy during P–P fault is there for the total fault time. However, this distortion with the proposed STFCL in combination with a PR controller is approximately half that of the conventional FRT (crowbar) strategy, as depicted by
Figure 18a at the PCC and 18b at 19 km away from the PCC.
The effectiveness of the proposed strategy is proved at PV side parameters, i.e., power, current, and voltage. The mentioned parameters are optimized to nominal values, without any disturbances at the entering and clearing of P–P fault through STFCL with a PR controller at the PCC. Except for the STFCL strategy, all the remaining combinations result in dips and rises at entering and clearing time of fault, as
Figure 19 shows clearly.