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Open AccessArticle

Input-Aware Implication Selection Scheme Utilizing ATPG for Efficient Concurrent Error Detection

Department of Computer Engineering, Chosun University, 309 Pilmun-daero, Gwangju 61452, Korea
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Electronics 2018, 7(10), 258; https://doi.org/10.3390/electronics7100258
Received: 19 September 2018 / Revised: 8 October 2018 / Accepted: 16 October 2018 / Published: 17 October 2018
(This article belongs to the Section Microelectronics and Optoelectronics)
Recently, concurrent error detection enabled through invariant relationships between different wires in a circuit has been proposed. Because there are many such implications in a circuit, selection strategies have been developed to select the most valuable implications for inclusion in the checker hardware such that a sufficiently high probability of error detection ( P d e t e c t i o n ) is achieved. These algorithms, however, due to their heuristic nature cannot guarantee a lossless P d e t e c t i o n . In this paper, we develop a new input-aware implication selection algorithm with the help of ATPG which minimizes loss on P d e t e c t i o n . In our algorithm, the detectability of errors for each candidate implication is carefully evaluated using error prone vectors. The evaluation results are then utilized to select the most efficient candidates for achieving optimal P d e t e c t i o n . The experimental results on 15 representative combinatorial benchmark circuits from the MCNC benchmarks suite show that the implications selected from our algorithm achieve better P d e t e c t i o n in comparison to the state of the art. The proposed method also offers better performance, up to 41.10%, in terms of the proposed impact-level metric, which is the ratio of achieved P d e t e c t i o n to the implication count. View Full-Text
Keywords: reliability; implications; concurrent error detection; probability of error detection; implication reduction; fault tolerance reliability; implications; concurrent error detection; probability of error detection; implication reduction; fault tolerance
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MDPI and ACS Style

Hassan, A.S.; Afzaal, U.; Arifeen, T.; Lee, J.A. Input-Aware Implication Selection Scheme Utilizing ATPG for Efficient Concurrent Error Detection. Electronics 2018, 7, 258. https://doi.org/10.3390/electronics7100258

AMA Style

Hassan AS, Afzaal U, Arifeen T, Lee JA. Input-Aware Implication Selection Scheme Utilizing ATPG for Efficient Concurrent Error Detection. Electronics. 2018; 7(10):258. https://doi.org/10.3390/electronics7100258

Chicago/Turabian Style

Hassan, Abdus S.; Afzaal, Umar; Arifeen, Tooba; Lee, Jeong A. 2018. "Input-Aware Implication Selection Scheme Utilizing ATPG for Efficient Concurrent Error Detection" Electronics 7, no. 10: 258. https://doi.org/10.3390/electronics7100258

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