Power Control Strategy for Efficiency Optimization in Parallel DC-DC Conveters

Abstract

A new control method for efficiency optimization in systems composed of parallel converters is presented in this paper. The proposed methodology considers the individual efficiency surfaces for given ratings of power and voltage and determines the optimum operating point for each converter such that the global system efficiency is maximized throughout the entire operating spectrum. Furthermore, a supervisory control strategy is proposed to manage the power-sharing of the converters according to the optimal surfaces provided by the methodology, enabling a performance enhancement for the system by improving its efficiency. Different approaches can be used to implement the active current sharing (ACS) scheme, and in-depth discussions are provided to guide the designer through the tradeoffs to achieve the desired transient and steady-state behavior for the system. Experimental results show that under light load operation, an improvement of 8.5% is achieved in comparison with a conventional technique of equal power-sharing. This points out that the proposed strategy is especially applicable and can significantly improve the performance of systems powered by batteries or renewable sources.

1. Introduction

The consolidation of distributed generation into modern power grids has motivated the development of control techniques that provide enhanced performance, reliability, modularity, robustness, and efficiency. Owing to the variability in environmental conditions, renewable energy systems are often subject to wide operating conditions of voltage, current, and processed power. To maximize generation and improve return on investments, the interface converter features a maximum power point tracking (MPPT) algorithm [1]. However, these converters typically process a fraction of their rated power throughout their lifespans. For this reason, these parts of the efficiency curve receive greater weighting in figures of merit, such as the European or CEC efficiency [2].

Several converter topologies have been developed with soft switching and other techniques aimed at reducing losses and volume for several classes of applications [3,4,5,6]. However, achieving high efficiency over a wide operating range, particularly over large load ranges, remains a major concern. Parallel-operated converters have become another approach for improving the global system efficiency [7,8,9]. Additionally, this configuration facilitates redundancy, scalability, and increased reliability by utilizing semiconductors with reduced losses in modules with fractional power ratings [10].

One common method for paralleling converters is to add interleaved parallel branches (phases) [11,12]. In this approach, one or more circuit branches are replicated in parallel to reduce the overall device effort, switching losses, and current ripple. Usually, in these cases, all branches have the same ratings and control is implemented to ensure that the power processed by each branch is the same. The modulation techniques for these systems can be modified to achieve different specific objectives, such as reducing the source or load current ripple [13,14]. For parallel-connected inverters, one should also consider the circulating current between converters, a problem that naturally arises from component mismatches, among other reasons. Methods to reduce these effects and improve the energy quality provided for loads were presented in [15,16,17].

The droop method is frequently employed to parallelize converters. Simple, effective, and without requiring physical means of communication, this method shares the power demand among all converters, which is often proportional to their power ratings [18,19]. The droop method can be easily adapted to various power levels and systems built using completely distinct topologies. The applications of this method vary from power sharing in converters fed by a single source to modules powered by multiple sources, as in the case of microgrids [20]. In addition to droop-based approaches, distributed control strategies have also been proposed for parallel converters supplied by multiple sources, focusing on voltage regulation and balanced current sharing without centralized coordination [21].

Beyond droop-based techniques, several alternative control strategies have been proposed to overcome its limitations and improve power sharing among parallel converters. Active approaches were presented in [22] to ensure that the power shared between multiple converters is proportional to their ratings, thereby correcting the inaccuracies of the droop method. In [23], a distributed control strategy for a parallel resonant CLLC Dual Active Bridge (DAB) converter is proposed for independent control of power flow in an attempt to compensate for parametric deviations and achieve a balanced current sharing. A wireless master–slave method was presented in [24] to avoid physical connections for communication. The authors also presented a stability analysis that considered communication delays. In [25], authors evaluate the transient performance in systems of parallel converters and propose an improved virtual impedance control strategy to mitigate the unbalances caused by load steps. However, these methods focus only on addressing the power-sharing problem.

Parallel configurations also allow the use of a minimum number of converters to supply load demand in an attempt to reduce losses. In this sense, a supervisory system that enables appropriate power-sharing among converters is a design concern. This power management should allow the system to achieve optimal efficiency over its entire operating range. However, only few studies have addressed this issue.

A method of perturbation of the power sharing and observation of the global efficiency was presented in [26], aiming to achieve high efficiency dynamically. A strategy for slicing the efficiency curve and assigning priorities to each slice was proposed in [27]. The controller of each converter is responsible for maintaining the converter operating in a higher efficiency region or reducing its power until shutdown. In [28], a sensorless strategy was formulated to equalize the processed power for Input-Parallel Output-Parallel (IPOP) DAB converters. The same system topology was covered in [29], where a tunable power-sharing strategy improved the transient performance for input-voltage disturbances. An Active Current Sharing (ACS) is proposed in [30] to balance the output currents and improve transient performance in the presence of disturbances.

All of these methods might improve global efficiency, but they do not ensure that the system will operate with optimal efficiency throughout all operating ranges. Several strategies have been proposed to overcome this issue. In [31], a Lagrangian loss optimal load sharing for phase-shifted full-bridge converters was presented. For wind power systems, Ref. [32] presented an optimization strategy based on an exhaustive search that lacks efficiency in complex systems. A hybrid heuristic optimization algorithm for DC-DC converters was introduced in [33], reducing the computational effort compared to the previous method. However, these three alternatives perform the optimization of a single variable, that is, processed power.

The main objective of this paper is to present an improved approach for power sharing among parallel converters, providing optimal efficiency throughout the entire system operating range, particularly for light loads. The method here is based on [33] and extends the optimization for input voltage variations while providing insights for control designers to implement sharing supervisor and loop controllers. More specifically, the proposed method differs from existing efficiency-oriented power-sharing approaches in three main aspects: (i) it determines the optimal power sharing among converters without enforcing equal power distribution, (ii) it considers a multivariable optimization framework that includes both processed power and input voltage, and (iii) it enables practical real-time implementation through an offline optimization stage combined with LUT-based control. This enhanced approach is particularly suitable for systems fed by renewable sources and battery-based systems, where the mission profile of the converters is to operate below half of the rated power most of the time and with varying input voltages.

The remainder of this paper is organized as follows. In Section 2, the efficiency of the parallel converter system is discussed. The optimization problem is formulated, and its constraints and search spaces are presented. The proposed optimization methodology and its inner stages are described in Section 3. Section 4 introduces the design of the control strategy for implementing optimal power sharing. The experimental results and discussions on the decision variables for supervisory control are presented in Section 5. Finally, the remarks and conclusions are presented in Section 6.

2. System Efficiency and Problem Formulation

Power losses in electronic conversion systems occur because of various phenomena. Some examples include conduction or switching of semiconductors, power consumption of ancillary systems such as drive circuits, protection and signaling subsystems [34,35,36]. The total losses of a converter vary depending on its operating point, and temperature, as well as in terms of their technological and constructive characteristics [37,38]. For light loads, the losses in the ancillary subsystems tend to be more significant and approximately constant. However, increasing the power level makes the switching and conduction losses more significant. The resulting converter efficiency ($\eta$) is usually plotted for all load ranges, and can be handled as a function of the output ($p_{\mathrm{out}}$) or input power ($p_{\mathrm{in}}$). It may be represented as a function of other relevant variables, such as the input ($v_{\mathrm{in}}$) or output voltage ($v_{\mathrm{out}}$). In [39], the authors compared different approaches to model efficiency curves or surfaces. For cases considering power and voltage, it is shown that the double quadratic model can approximate surfaces with adequate correlation. This model is defined by

$$\eta (p,v)={\displaystyle \frac{p}{p+\left({\alpha }_0\left(v\right)+{\alpha }_1\left(v\right)p+{\alpha }_2\left(v\right)p^2\right)}}$$

(1)

with

$$\begin{array}{cc}\hfill {\alpha }_0\left(v\right)& \triangleq k_{0,0}+k_{0,1}v+k_{0,2}{v}^2\hfill \end{array}$$

(2)

$$\begin{array}{cc}\hfill {\alpha }_1\left(v\right)& \triangleq k_{1,0}+k_{1,1}v+k_{1,2}{v}^2\hfill \end{array}$$

(3)

$$\begin{array}{cc}\hfill {\alpha }_2\left(v\right)& \triangleq k_{2,0}+k_{2,1}v+k_{2,2}{v}^2\hfill \end{array}$$

(4)

where $k_{0,0\dots 2}$, $k_{1,0\dots 2}$, and $k_{2,0\dots 2}$ are the coefficients to be determined by surface-fitting algorithms over experimental, simulation, or theoretical results. In this model, p and v correspond to the average power and voltage values, respectively, computed over one switching period $T_s$ and measured under steady-state operating condition. This equation is generic enough that, at this point, p or v can represent input or output values.

For systems composed of $n_c$ parallel converters, the global efficiency of the system (${\eta }_{\mathrm{sys}}$) can be determined from the ratio between the sum of the output powers and the sum of the input powers of all converters, where $p_{\mathrm{out},c}$ and $p_{\mathrm{in},c}$ denote the output and input power of the c-th converter, respectively, that is,

$${\eta }_{\mathrm{sys}}={\displaystyle \frac{p_{\mathrm{out},1}+p_{\mathrm{out},2}+\dots +p_{\mathrm{out},n_c}}{p_{\mathrm{in},1}+p_{\mathrm{in},2}+\dots +p_{\mathrm{in},n_c}}}={\displaystyle \frac{{\displaystyle \sum _{c=1}^{n_c}}{p}_{\mathrm{out},c}}{{\displaystyle \sum _{c=1}^{n_c}}{p}_{\mathrm{in},c}}}$$

(5)

Inspecting (5) and knowing that $p_{\mathrm{out},c}=p_{\mathrm{in},c}{\eta }_c$ one might suppose that, for the same output power, the resulting system efficiency will be different for different power distributions among the converters. This leads to the need for a methodology that establishes optimal power references for each converter to ensure that global efficiency is maximized for each operating point. If the efficiency model (1) is fitted in terms of the input power and the input voltage, the output power can be computed as $p_{\mathrm{out},c}=p_{\mathrm{in},c}{\eta }_c(p_{\mathrm{in},c},v_{\mathrm{in}})$. By substituting (1) into this expression and subsequently replacing $p_{\mathrm{out},c}$ in (5), a cost function minimization problem can be written as

$$\eta {(p_{\mathrm{in},1},\dots ,p_{\mathrm{in},n_{\mathrm{c}}})}_{\max }=\underset{p_{\mathrm{in}}}{min}\left(-{\displaystyle \frac{{\displaystyle \sum _{c=1}^{n_c}}{\displaystyle \frac{p_{\mathrm{in},c}^2}{p_{\mathrm{in},c}+{\alpha }_{0,c}\left(v_{\mathrm{in}}\right)+{\alpha }_{1,c}\left(v_{\mathrm{in}}\right)p_{\mathrm{in},c}+{\alpha }_{2,c}\left(v_{\mathrm{in}}\right)p_{\mathrm{in},c}^2}}}{{\displaystyle \sum _{c=1}^{n_c}}{p}_{\mathrm{in},c}}}\right)$$

(6)

The solution to this problem provides an optimal set of $p_{\mathrm{in},1},\dots ,p_{\mathrm{in},n_{\mathrm{c}}}$ values that ensure the maximum system efficiency for all feasible operating points. For compactness, the vector of processed power values is defined as ${\mathit{p}}_{\mathrm{in}}={[p_{\mathrm{in},1},p_{\mathrm{in},2},\dots ,p_{\mathrm{in},n_c}]}^{\mathrm{T}}$, which represents a candidate or optimal solution throughout the optimization process. Although the objective is to maximize the efficiency, (6) is formulated as the minimization of its negative value. This formulation is adopted because most optimization algorithms, including those employed in this work, are designed to minimize a cost function rather to maximize a merit function. The optimization problem (6) is nonlinear and subject to certain constraints. The first states that the system power under optimization ($P_{\mathrm{opt}}$) must match the power processed by all converters, that is, $P_{\mathrm{opt}}=p_{\mathrm{in},1}+\dots +p_{\mathrm{in},n_c}$. Since the algorithms used in the methodology handle restrictions in matrix form, this linear equality can be expressed as

$$\left[\begin{array}{cccc}1& 1& \dots & 1\\ 0& 0& \dots & 0\\ ⋮& ⋮& \ddots & ⋮\\ 0& 0& \dots & 0\end{array}\right]\left[\begin{array}{c}{p}_{\mathrm{in},1}\\ p_{\mathrm{in},2}\\ ⋮\\ p_{\mathrm{in},n_c}\end{array}\right]=\left[\begin{array}{c}{P}_{\mathrm{opt}}\\ 0\\ ⋮\\ 0\end{array}\right]$$

(7)

Another constraint states that the processed power of each converter ($p_{\mathrm{in},c}$) must be less than or equal to its rated value ($P_{\mathrm{in},c}^{\max }$) and the minimum value ($P_{\mathrm{in},c}^{\min }$). Thus, one has the linear inequality given by

$$\left[\begin{array}{cccc}1& 0& \dots & 0\\ -1& 0& \dots & 0\\ 0& 1& \dots & 0\\ 0& -1& \dots & 0\\ ⋮& ⋮& \ddots & ⋮\\ 0& 0& \dots & 1\\ 0& 0& \dots & -1\end{array}\right]\left[\begin{array}{c}{p}_{\mathrm{in},1}\\ p_{\mathrm{in},2}\\ ⋮\\ p_{\mathrm{in},n_c}\end{array}\right]\le \left[\begin{array}{c}{P}_{\mathrm{in},1}^{\max }\\ -P_{\mathrm{in},1}^{\min }\\ P_{\mathrm{in},2}^{\max }\\ -P_{\mathrm{in},2}^{\min }\\ ⋮\\ P_{\mathrm{in},n_c}^{\max }\\ -P_{\mathrm{in},n_c}^{\min }\end{array}\right]$$

(8)

where the inequality between vectors is understood componentwise; that is, for any $\mathit{a},\mathit{b}\in {\mathbb{R}}^m$,

$$\mathit{a}\le \mathit{b}\iff a_j\le b_j\forall j=1,\dots ,m$$

(9)

Defining a minimum power level in (8) introduces a degree of freedom that can be used by the designer to prevent converters from operating in unsupported regions, whether due to the employed control strategy or hardware constraints. This degree of freedom can also be exploited to prioritize operation only in desired modes, such as continuous conduction mode.

The minimization function (6), in addition to its nonlinear and constrained nature, may feature multiple local minima or even multiple global minima in cases where the system is composed of equal converters. This paper proposes a new method to solve this optimization problem and presents a control strategy that enables parallel converter systems to operate at optimal efficiency over all load and input-voltage ranges.

3. Proposed Methodology

The main approach of the proposed optimization method is to perform a search throughout the solution hyperplane (global optimization) and simultaneously provide good precision for defining the optimal solution (local optimization). However, because multiple global optimum points can exist, an arbitrating strategy must select the most appropriate solution for each situation (ambiguity resolution). These characteristics define the basis for the proposed methodology, which is summarized in the flowchart depicted in Figure 1 and described in the following sections.

3.1. Stage 1: Initialization

The first step of the optimization process is to provide the data required for the algorithms. In this stage the efficiency functions ${\eta }_c(p,v)$ of each converter must be defined. While it is possible to use different approaches to represent it, they often require data samples that can be obtained in multiple ways. Modeling the efficiency surfaces usually reduces the computational effort or approximation errors throughout the optimization process. Although model (1) is suggested due to its generality, the designer can use any other model that may better represent the converters used in the system. It is even possible to skip the surface-fitting step and employ multidimensional interpolation between data samples. Furthermore, although the formulation in this work uses the input power and input voltage as variables, the minimization problem can be defined using any other suitable combination (e.g., output power, output voltage), depending on the application. For any such cases, the cost function (6) must be updated accordingly.

To perform the surface fitting and obtain the efficiency models, the designer must provide three sets of values. Let the input power and input voltage sampling vectors be defined as ${\mathit{p}}_c^s={[P_1^s,P_2^s,\dots ,P_m^s]}^T$ and ${\mathit{v}}_c^s={[V_1^s,V_2^s,\dots ,V_n^s]}^T$, respectively, where the superscript ^s stands for the sampled source of the variables. For each combination $(P_m^s,V_n^s)$ an efficiency measurement is acquired, and the complete set of samples for the c-th converter can be organized in the following matrix:

$${\mathit{\eta }}_c^s=\left[\begin{array}{cccc}{\eta }_{11}& {\eta }_{12}& \dots & {\eta }_{1n}\\ {\eta }_{21}& {\eta }_{22}& \dots & {\eta }_{2n}\\ ⋮& ⋮& \ddots & ⋮\\ {\eta }_{m1}& {\eta }_{m2}& \dots & {\eta }_{mn}\end{array}\right]$$

(10)

Because the double-quadratic model (1) contains nine coefficients, at least nine efficiency samples are required to determine the model uniquely. In practice, however, a denser sampling grid is recommended to ensure numerical robustness and to accurately capture regions with higher curvature in the efficiency surface.

The proposed methodology employs the nonlinear least squares procedure based on the Levenberg–Marquardt algorithm [40] to fit model (1) to the efficiency samples. Once the coefficients $k_{0,0\dots 2}$, $k_{1,0\dots 2}$ and $k_{2,0\dots 2}$ are identified for each converter, the corresponding efficiency surfaces functions ${\eta }_1(p,v),\dots ,{\eta }_{n_c}(p,v)$ are obtained. These models are substituted into (6) to define the nonlinear cost function used to evaluate the global system efficiency over all feasible operating points.

The designer must define the rated power levels ($P_{\mathrm{in}}^{\max }$), and the minimum allowable power levels ($P_{\mathrm{in}}^{\min }$) for each of the $n_c$ converters. These limits determine the feasible operating region and are used to construct the constraint matrices (7) and (8), ensuring that the optimization respects both the total system power and the individual converter ratings.

Finally, the designer must provide the points at which the power-sharing optimization is to be performed. Let ${\mathcal{P}}_{\mathrm{opt}}=\left\{P_{\mathrm{opt},1},\dots ,P_{\mathrm{opt},n_P}\right\}$ and ${\mathcal{V}}_{\mathrm{opt}}=\left\{V_{\mathrm{opt},1},\dots ,V_{\mathrm{opt},n_V}\right\}$ be the sets of processed power and input voltage points, respectively. To evaluate all possible operating conditions, a list of input parameter combinations is defined as the following Cartesian product:

$$\begin{array}{cc}\hfill \mathcal{X}& ={\mathcal{P}}_{\mathrm{opt}}\times {\mathcal{V}}_{\mathrm{opt}}\hfill \\ \hfill \mathcal{X}& =\left\{(P_{\mathrm{opt},k},V_{\mathrm{opt},i})\mid 1\le k\le n_P,1\le i\le n_V\right\}\hfill \end{array}$$

(11)

and each element $x=\left(P_{\mathrm{opt},k},V_{\mathrm{opt},i}\right)\in \mathcal{X}$ corresponds to one combination of power and voltage values to be processed by the optimization algorithms. Although there is no specific rule in defining these points, the designer can start with a basic set of points to coarsely investigate the sharing surface. Then, apply a refinement in subsequent passes to increase resolution and accuracy, especially over rapidly varying regions of the sharing surfaces.

3.2. Stage 2: Global Optimization

Conventional minimization methods such as Newton-Raphson, secant, and bissecant require an appropriate initial guess, which may not always be easy to obtain [41]. Although they are fast and provide good accuracy, these methods are based on gradients, jacobians, or other derivative terms. Therefore, if the initial guess is not chosen properly, they might erroneously converge to a local minimum.

Genetic Algorithms (GA) are known to be effective in optimizing problems containing local and global minima. They are a class of iterative and stochastic algorithms based on the natural selection principle, and minimize cost functions using the evolutionary adaptation of a set [42]. This set, known as the population, is composed of individuals, or chromosomes, which in turn are composed of genes that correspond to the variables that will be optimized. At each iteration, also called a generation, the GA searches through the entire solution hyperplane without relying on initial guesses and prior knowledge of it. This feature allows for a general evaluation of feasible solutions before converging to the optimum point.

Based on the definitions provided by the initialization stage, the GA is set up to minimize the cost function (6) running one optimization for each $(P_{\mathrm{opt}},V_{\mathrm{opt}})$ pair in $\mathcal{X}$. The algorithm comprises several internal strategies that perform the evolution of a population. Although there is no unique choice, one must consider that these algorithms must be able to handle optimization constraints. The methods employed here are the roulette wheel for parental selection, heuristic for crossover, and adaptive feasible for mutation [33,42,43].

The evolutionary process may terminate under different conditions. A common criterion is to stop when the fitness of the best individual does not evolve after a maximum number of generations (a criterion called stall generations). Because of its stochastic nature, GA may not provide an accurate solution, or it may take more time compared to gradient-based methods with a good initial guess. In the hybrid strategy proposed in this study, the GA is mainly used to search for the optimal solution region. After a few stall generations, the GA is stopped, and the process advances through a local (faster) optimizer.

3.3. Stage 3: Local Optimization

The best chromosome obtained by the GA, which is treated as an estimate of the optimal solution (${\widehat{P}}_{\mathrm{opt}}$), is used as an initial guess for the local optimizer. Gradient-based methods have been extensively developed to rapidly obtain solutions for well defined convex functions. An algorithm known as Sequential Quadratic Programming (SQP) is employed to solve the constrained optimization problem (6). SQP performs an inline search using a figure of merit similar to that proposed in [44,45], and approximates the Newton method for constrained optimization, as is done for unconstrained problems [46]. This algorithm uses the Karush–Kuhn–Tucker (KKT) equations, which are necessary conditions to minimize constrained problems [47,48], and is now the basis of many nonlinear programming algorithms [48]. This local optimization approach can be easily carried out with the aid of specialized software packages, such as the fmincon function of Matlab (2021b). This stage provides $P_{\mathrm{opt}}^{*}$, which is the optimal power distribution between converters that provides the maximum system efficiency for a given operating point.

3.4. Stage 4: Ambiguity Resolution

Systems of two or more identical converters exhibit symmetry in the solution hyperplane, resulting in multiple global minima. In these cases, applying the same percentage of power distribution among converters, but in different combinations, leads to the same theoretical efficiency. When performing a sweep throughout the system operating range, one cannot guarantee the convergence of the GA to the same region at each iteration. This behavior is due to the stochastic nature of the GA. Consequently, it is not possible to ensure that a given power distribution is employed similarly at the operating points in the neighborhood. To solve this problem, the proposed methodology includes an ambiguity resolution strategy to arbitrate the most appropriate solution against the qualitative variables not covered by (6).

The ambiguity resolution strategy works by sorting the power distribution results from previous and current iterations. If the sorting order remains unchanged, then the power distribution obtained in the current iteration is maintained. Otherwise, the power distribution is sorted according to the previous iteration, and the resulting efficiency is compared with the efficiency of the current iteration. If both are the same, the order of the preceding iterations is maintained. Otherwise, the results obtained in the current iteration are retained.

This strategy avoids sudden power redistribution without noticeable improvements in the system efficiency. Thus, the power distribution trajectories are preserved as smoothly as possible over the operating range specified for the system.

4. Control Strategy

In this section, a simple and effective control strategy based on Active Current Sharing (ACS) is presented to implement the power-sharing surfaces obtained using the optimization methodology. A block diagram of the proposed control strategy is shown in Figure 2 for a system of $n_c$ parallel converters. An external voltage loop is responsible for regulating the DC bus voltage ($v_{\mathrm{o}}$), where the voltage controller $C_v$ generates a global input current reference $i_{\mathrm{ref}}$. A sharing supervisor uses two decision variables to identify the system operating point in terms of input voltage (${\delta }_v$) and processed power (${\delta }_p$). These variables are employed to query a look-up table (LUT) that stores the results of the optimization methodology as a three-dimensional matrix of weighting factors. The signals of the decision variables pass through low-pass filters to mitigate noise injection into the supervisory control and improve the system transient response in some cases. Based on the LUT results, a convex combination is applied to the global current reference, providing the current references $i_{\mathrm{ref},1\dots n_c}$ that are imposed on the internal current loop of each converter. Finally, the inner current controllers $C_{i,1\dots n_c}$ are responsible for tracking the inductor current, enabling an optimal system efficiency. The following sections provide in-depth explanations and insights into the design of the most relevant blocks.

4.1. Supervisory Control

The optimization methodology proposed in Section 3 determines the power required by each converter to achieve optimal system efficiency. Manipulation from power to current must be performed to apply these results to the proposed control system. Furthermore, because the voltage controller provides a system input current reference, the supervisory block must perform a weighting over this value to obtain the current references that will be applied to each converter. The conversion from power to convex weighting surfaces was performed using

$$W_{k,i,c}={\displaystyle \frac{P_{\mathrm{opt},k,i,c}^{*}}{{\displaystyle \sum _{c=1}^{n_c}{P}_{\mathrm{opt},k,i,c}^{*}}}}$$

(12)

where c is the converter index, k and i correspond, respectively, to the discrete power and voltage levels for which the optimization was performed, maintaining the same correspondence defined in (11).

Decision variables are used to map the values of the input voltage and processed power to indices i and k. For ${\delta }_v$, the associated signal is the input voltage of the system. On the other hand, ${\delta }_p$ can be alternately defined according to the availability of sensors or signals. Choosing the most appropriate strategy is not straightforward; the final decision is made by the designer after carrying out a cost–benefit tradeoff.

As a first strategy for parallel boost converters, one can obtain the processed power by the product of $v_{\mathrm{in}}$ and the total input current $i_{\mathrm{in}}$, which corresponds to the sum of all inductor currents $i_{\mathrm{in},1\dots n_c}$. However, as in many other converters, the input power does not instantaneously reflect the power absorbed by the load, which can be confirmed by the Tellegen theorem [49].

Let $\overline{x}$ denote the average value of a signal $x\left(t\right)$ over one switching period. Neglecting the losses for the sake of simplicity, since their impact on system dynamics is negligible for this analysis, the circuit equations of a single boost converter can be written as

$${\overline{v}}_{\mathrm{in}}{\overline{𝚤}}_L={\overline{v}}_{\mathrm{out}}{\overline{𝚤}}_{\mathrm{out}}+L{\overline{𝚤}}_L\frac{\mathrm{d}{\overline{𝚤}}_L}{\mathrm{d}t}+C{\overline{v}}_C\frac{\mathrm{d}{\overline{𝚤}}_C}{\mathrm{d}t}$$

(13)

or, in a compact form

$${\overline{p}}_{\mathrm{in}}={\overline{p}}_{\mathrm{out}}+\Delta \epsilon$$

(14)

where $\Delta \epsilon$ is the sum of the inductor and capacitor energy variations. From (14), it can be observed that during transients, the averaged input power is affected by the energy variations required to lead the converter to a new operating point. It is only in the steady state, when the derivatives reduce toward zero, that the averaged input power can be considered the same as the averaged output power. In this sense, supervisory control cannot act instantaneously during transients because these energy variations result in erroneous load power estimations that may lead to inadequate power redistributions and cause performance degradation or even instabilities. To mitigate the adverse effects, filtering strategies must be implemented to limit the bandwidth, so ${\delta }_p$ responds to nearly steady-state processed power. However, this should be done carefully, as large power steps could render the system unable to supply the load demand or force active converters to work under serious overload conditions. In-depth discussions will be presented along with the experimental results.

As a second strategy for ${\delta }_p$ one may employ only the output current $i_{\mathrm{out}}$ in systems where the output voltage is known and fixed or regulated, which is a common case for DC-DC converters. The advantage of this approach is that the power consumed by the load is directly related to the output current, and the output voltage oscillations are usually sufficiently small to be neglected. From the implementation perspective, this approach typically requires an additional current sensor, which affects the system costs. In contrast to the first approach, input-current sensors are often available in boost or other converters.

4.2. Inner Current-Loop Controller

Applying the sharing strategy does not rely on a specific type of controller. Instead, different approaches may be employed to track the optimal references provided by the supervisory control while achieving the desired control system goals. A classical discrete-time proportional–integral (PI) controller was used to track the current references for each converter. To design this controller, the control-to-input current transfer function is given by

$$G_{\widetilde{𝚤},\tilde{d}}\left(s\right)=K_{d,i}{\displaystyle \frac{{\displaystyle \frac{s}{{\omega }_{z,i}}}+1}{{\displaystyle \frac{s^2}{{\omega }_{0,i}^2}}+{\displaystyle \frac{s}{Q_i{\omega }_{0,i}}}+1}}$$

(15)

where $K_{d,i}$ is the DC gain of the transfer function; ${\omega }_{z,i}$ is the zero frequency; ${\omega }_{0,i}$ is the natural frequency; and $Q_i$ is the quality factor. This transfer function can be obtained by employing the state-space averaging technique and applying the Laplace transform to the obtained model. The necessary parameters are obtained from

$$\begin{array}{cc}\hfill K_{d,i}& ={\displaystyle \frac{2V_{\mathrm{in},\mathrm{rated}}}{R{D}^{\prime 3}}}\hfill \end{array}$$

(16)

$$\begin{array}{cc}\hfill {\omega }_{z,i}& ={\displaystyle \frac{2}{CR}}\hfill \end{array}$$

(17)

$$\begin{array}{cc}\hfill Q_i& =D^{\prime }R\sqrt{{\displaystyle \frac{C}{L}}}\hfill \end{array}$$

(18)

$$\begin{array}{cc}\hfill {\omega }_{0,i}& ={\displaystyle \frac{D^{\prime }}{\sqrt{LC}}}\hfill \end{array}$$

(19)

where $V_{\mathrm{in},\mathrm{rated}}$ is the rated input voltage, R is the equivalent load resistance, D and $D^{\prime }$ the duty ratio and its complement, respectively, such that $D^{\prime }=1-D$, L is the input inductance, and C is the DC-bus capacitor.

4.3. DC-Bus Voltage Controller

The design of the voltage controller may face some challenges owing to the optimal sharing strategy. Each boost converter may provide different current values or they can even be turned off to increase system efficiency, leading to a nonlinear and variable-structure system. A simplification of the complete dynamics must be assumed to continue using a classical control approach. With a fast and well-regulated inner current loop, each converter behaves as a controlled current source, feeding the output impedance comprising the resistive load and the DC-bus capacitor, as depicted in Figure 3. The total output current is given by $i_{\mathrm{in},\mathrm{sys}}=i_{\mathrm{in},1}+\dots +i_{\mathrm{in},n_c}$. For the boost converter, the output current is related to the input current as $i_{\mathrm{out},\mathrm{sys}}=i_{\mathrm{in},\mathrm{sys}}{D}^{\prime }$. Applying the Laplace transform to the circuit shown in Figure 3, the transfer function of the DC-bus voltage can be obtained using the system input current as

$$G_z\left(s\right)=K_{d,v}{\displaystyle \frac{1}{{\displaystyle \frac{s}{{\omega }_{p,v}}}+1}}$$

(20)

The DC gain of the transfer function and pole frequency are defined by

$$\begin{array}{cc}\hfill K_{d,v}& =D^{\prime }R\hfill \end{array}$$

(21)

$$\begin{array}{cc}\hfill {\omega }_{p,v}& ={\displaystyle \frac{1}{RC}}\hfill \end{array}$$

(22)

Although $G_z\left(s\right)$ is a simplification, high-frequency dynamics can be neglected if the bandwidth of the DC-bus voltage controller is sufficiently narrower than that of the current loop.

5. Experimental Results

An experimental setup with three parallel boost converters was constructed to evaluate the proposed optimization methodology.

Table 1. Parameters of the experimental prototype.

Parameter	Value
$P_{\mathrm{out},\mathrm{sys}}$	750 $\mathrm{W}$ (1 $\mathrm{p}.\mathrm{u}.$)
$P_{\mathrm{out},1}$, $P_{\mathrm{out},2}$, $P_{\mathrm{out},3}$	250 $\mathrm{W}$ (0.33 $\mathrm{p}.\mathrm{u}.$)
$F_s$	10 $\mathrm{k}$$\mathrm{Hz}$
$V_{\mathrm{out}}$	325 $\mathrm{V}$ (1 $\mathrm{p}.\mathrm{u}.$)
$V_{\mathrm{in}}$	110 V to 250 V
$V_{\mathrm{in},\mathrm{rated}}$	190 $\mathrm{V}$
D	0.415
$L_B$	6 $\mathrm{m}$$\mathrm{H}$
$C_o$	680 $\mathsf{\mu }$$\mathrm{F}$
$R_L$	140.8 $\Omega$

summarizes the specifications of the proposed system. All the tests were conducted with the platform dSPACE DS1103 that works together with Matlab/Simulink (version R2021b). The platform was built around a PowerPC604e processor and a DSP TMS320F240 as a slave microcontroller for advanced I/O purposes, such as PWM signal generation. Efficiency measurements were performed using a Yokogawa WT1600 digital power meter (1 $\mathrm{M}$$\mathrm{Hz}$ bandwidth).

The first step in applying the proposed methodology involves modeling the efficiency surface. A total of 64 samples were acquired across voltages ranging from 110 $\mathrm{V}$ to 250 $\mathrm{V}$ in steps of 20 $\mathrm{V}$. For each converter, the samples were collected at 12%, 20%, 28%, 41%, 59%, 89%, 93%, and 100% of the rated output power.

Table 2. Experimental efficiency samples for Converter 1.

		Output Power (%)
		12	20	28	41	59	89	93	113
Input voltage ($\mathrm{V})$	110	72.72	79.22	83.39	87.59	90.47	92.67	92.84	93.55
	130	74.35	79.93	83.28	87.51	90.55	92.92	93.12	93.87
	150	76.76	81.47	84.09	87.64	90.79	93.20	93.39	94.18
	170	79.11	83.03	85.36	88.08	91.21	93.59	93.80	94.56
	190	81.77	85.09	86.87	89.14	91.85	94.06	94.31	95.03
	210	84.16	87.35	88.57	90.37	92.78	94.81	94.97	95.62
	230	87.84	89.83	90.29	91.94	93.93	95.68	95.83	96.33
	250	90.24	93.11	91.41	93.77	95.42	96.68	96.83	97.21

presents the efficiency samples obtained for Converter 1. Converters 2 and 3 provide results with a difference of less than 1% and are therefore omitted here.

Applying the efficiency samples from Table 2 to the surface-fitting algorithm for (1) results in the efficiency surface model. The obtained coefficients are listed in

Table 3. Coefficients of the fitted efficiency surface.

Coefficient	Value
$k_{0,0}$	0.111214
$k_{0,1}$	−0.269991
$k_{0,2}$	0.174552
$k_{1,0}$	−0.355473
$k_{1,1}$	1.734400
$k_{1,2}$	−1.562100
$k_{2,0}$	0.322832
$k_{2,1}$	−1.451300
$k_{2,2}$	1.289200

, and Figure 4 shows the fitted surface and experimental samples. The quality of the fit is confirmed by a root-mean-square error (${\mathrm{RMS}}_{\mathrm{e}}$) between the fitted surface and the experimental samples of $4.091\times {10}^{-3}$. Because the converters have identical specifications, their efficiency surfaces are assumed equal.

After properly modeling the efficiency surfaces, the following steps consist of running the global and local optimizations. The GA is configured with a population size of 50 individuals, crossover rate of 0.5, and mutation rate of 0.1. The proposed algorithm performs a sweep in the system power from 0.02 p.u. to 1.0 p.u., in steps of 0.02 p.u., and the input voltage varies from 110 V to 250 V, in steps of 20 V. Figure 5 shows the resulting optimized power values that each converter must supply to achieve the optimal system efficiency. For this case study, the most noticeable difference in power distribution is for an input voltage of 110 $\mathrm{V}$. For higher voltage levels, the sharing follows a similar profile between adjacent voltage values. It is important to note that the almost intuitive power distribution surfaces are a special feature of the prototype. It has been verified that in several other scenarios, the optimal sharing surfaces are more complex than the ones presented. This feature is most commonly observed when the peak efficiency is at the rated power of the converter.

Applying (12) to convert the optimization results shown in Figure 5 from the power to weighting values, one obtains the surfaces depicted by Figure 6. This set of values is stored in the supervisory control subsystem as one LUT for each converter.

The final step in designing the control system is tuning the current and voltage loops. After substituting the parameters from Table 1 into the transfer function (15), a current controller for the inner loop can be designed. Discretizing by a ZOH with the sampling frequency matching the switching frequency and considering one sample delay ($z^{-1}$) for implementation, one can obtain the PI controller transfer function given by

$$C_i\left(z\right)={\displaystyle \frac{0.087669z-0.078200}{z-1}}$$

(23)

which provides a bandwidth of 800 $\mathrm{Hz}$ and a phase margin of 40°, approximately.

Substituting the parameters from Table 1 and again discretizing by a ZOH with a sampling frequency matching the switching frequency, the outer PID controller for the DC-bus voltage is designed, and its transfer function is given by

$$C_v\left(z\right)={\displaystyle \frac{0.056137z-0.055705}{z^2-1.575643z+0.575643}}$$

(24)

which provides a bandwidth of 18 $\mathrm{Hz}$ and a phase margin of approximately 80°.

Figure 7 shows the block diagram used to implement each controller. Although not all terms must be used, it realizes a PI+filter action. $K_A$ is related to the tracking time constant that configures the rate at which the integral term is reset, forming an anti-windup strategy based on back calculation. Here, defining a time constant $T_{\mathrm{aw}}=0.2 \mathrm{s}$, the anti-windup gain can be calculated as

$$K_A={\mathrm{e}}^{\left(-T_s/T_{\mathrm{aw}}\right)}=0.9995$$

(25)

The other parameters of the control system were obtained by applying partial fraction decomposition to the controller transfer function. For the current controller (23), this procedure results in parameters $K_P=0.087669$, $K_I=0.009469$, and $K_f=w_f=0$. Similarly, for the voltage controller, the obtained parameters were $K_I=0.001019$, $K_F=0.055118$, $w_f$ = 575,643, and $K_P=0$.

5.1. Decision Variables and Bandwidth Considerations

Decision variables play a critical role in supervisory control and overall system performance. Therefore, care should be taken to mitigate undesirable dynamics and noise coupling. In this section, several filtering strategies are investigated, providing insights into the appropriate selection of decision variables and their impact on system performance in terms of bandwidth and filter complexity. This analysis proposes the main guidelines for applying the results of the efficiency optimization methodology. To avoid the cross-influence of the decision variables and investigate the differences between the implementation strategies for ${\delta }_p$, the input voltage was fixed in the experimental setup at 190 $\mathrm{V}$ (${\delta }_v=0.57$); therefore, so just ${\delta }_p$ was used as a decision variable.

In the first analysis, the output current was used as a decision variable, and ${\delta }_p=i_{\mathrm{out}}$. In addition to quickly following variations in the power consumed by the load, this signal provides a wider bandwidth. Therefore, the objective of a low-pass filter is to simply attenuate and decouple noise that can degrade the performance of supervisory control. Figure 8 presents the experimental results for three different filtering strategies when the load is switched from 100% to 50% of its rated value. Initially, when the system operates at full power, the three converters deliver their rated power. When the load is reduced to half power, the optimal sharing algorithm establishes that Converter 3 must be turned off, whereas converters 1 and 2 operate at half power.

Starting with a simpler case, Figure 8a depicts the waveforms for the three input currents and output voltage when using a first-order filter with a cutoff frequency of 500 $\mathrm{Hz}$. The notable noise present on currents $i_1$ and $i_2$ was introduced by supervisory control. Instrumentation noise, which might be inherent in the signals, causes the weightings applied by the supervisory control to the reference currents to become noisy. However, this problem can not be solved by using a heavier filter. Figure 8b presents the results for a sixth-order IIR Butterworth filter with a bandwidth of 1000 $\mathrm{Hz}$. It can be observed that the steady-state performance is severely degraded compared with the previous case. Finally, Figure 8c shows the results for a third-order IIR Butterworth filter with a bandwidth of 300 $\mathrm{Hz}$. In this case, converter currents have much smoother trajectories while still maintaining a fast decision to shut down Converter 3 and reduce the power of converters 1 and 2 by half.

The results in Figure 8 show that the system performance is more sensitive to the decision variable bandwidth than to the filter complexity. Larger bandwidths allow coupling of noise to the weighting values provided by the supervisor. In addition to preventing the system from operating at optimal efficiency, it may lead to instability, depending on the magnitude of the noise affecting the decision variable. Among several other tests, it was verified that a second-order Butterworth FIR filter with a bandwidth of 500 $\mathrm{Hz}$ is the most effective for the case ${\delta }_p=i_{\mathrm{out}}$. Figure 9 shows the results obtained using this configuration. In this test, different load steps were applied at every 400 $\mathrm{m}$$\mathrm{s}$ following the sequence 80%, 40%, 20%, and 60% of the system’s rated power. The power sharing target to achieve the optimal system efficiency with each of these load values is presented in

Table 4. Optimal power-sharing for the evaluated load steps.

System Power	Weighting Values
	Converter 1	Converter 2	Converter 3
80%	0.416	0.416	0.166
40%	0.833	0.166	0.000
20%	1.000	0.000	0.000
60%	0.555	0.444	0.000

.

Now, considering ${\delta }_p=i_{\mathrm{in}}$, because the input voltage is fixed during this analysis, it has already been demonstrated by (14) that its dynamics must be significantly reduced so that the supervisory control operates solely based on its steady-state values. In other words, the supervisory controller should not respond to the energy variations required to push the converters toward new equilibrium points. In the case of a boost converter, when the output power increases, the controller momentarily keeps the switch closed for a longer period to allow the inductor current to rise and reach a new steady state level. Furthermore, to achieve a fast dynamic response of the output voltage, the controllers may induce brief overcurrents. If the supervisory control reacts to these events, it may unnecessarily trigger additional converters that should be off, only to complement the current during the transient period.

The filter topology of the second-order Butterworth FIR was kept the same for the following tests, allowing a more detailed evaluation of the bandwidth and system performance. The load switching sequence applied in the analysis presented by Figure 9 is maintained. Figure 10a depicts the results for a cutoff frequency of 1 $\mathrm{Hz}$, where a slower response in the power redistribution between the converters is observable. During the first load switch, Converter 3 takes a longer time to be turned on, causing Converters 1 and 2 to operate at higher power. When the load is increased to 60%, Converters 2 and 3 are initially off, and Converter 1 is set in an overload condition close to 200% during the first 200 $\mathrm{m}$$\mathrm{s}$. After this period, Converter 2 is turned on and Converter 3 is kept off as expected according to Table 4. Figure 10b presents the results when the filter bandwidth is increased to 5 $\mathrm{Hz}$. Power-sharing is performed with a faster dynamic, and the overload period when the power is increased to 60% is significantly reduced. Nevertheless, Converter 3 is improperly activated to help alleviate the overload. Finally, in an attempt to further improve the transient response for power sharing, the filter bandwidth is increased to 10 $\mathrm{Hz}$. Again, Converter 3 is not only put into operation incorrectly, but the current reference assigned to it is even higher. Although the wider bandwidth of the decision variable offers an improved transient response.

Comparing the results presented thus far, it is clear that the output current as a decision variable provides the best transient response and steady-state performance for the system. However, this option requires an additional sensor that is usually not present in the system. The major concern in this case is the avoidance of instrumentation noise coupling to the supervisory control. However, if the objective is to enable efficiency optimization without penalizing costs, employing the total input current may be the best approach. In this situation, a more thorough analysis of the transient response of the system is required, particularly regarding the potential for overcurrent events while pushing the converters to new operating points.

5.2. Transient Response and Power-Sharing Performance

Three power-sharing strategies are compared in the discussion that follows in terms of their transient response and system efficiency. In addition to the optimal power distribution employing the input power and output current as decision variables, a strategy of equal power sharing among converters is also tested, as it is one of the most employed strategies for parallel converters. Based on the considerations in the previous section, the input power signal was band-limited to 10 $\mathrm{Hz}$, whereas the output current was limited to 500 $\mathrm{Hz}$. Because no fast changes are expected at the input voltage, it is also band limited to 10 $\mathrm{Hz}$. Second-order Butterworth FIR filters were employed for all the supervisory signals.

The same load step sequence as in the previous section was applied to analyze the transient behavior of the sharing strategies. However, for the upcoming analysis, the input voltage is varied and used as both a decision variable and input power estimation. Figure 11 depicts these results for an input voltage of 110 $\mathrm{V}$. Figure 11a presents the results for the equalized power-sharing strategy. The maximum overshoot and undershoot measured for the output voltage in this case were 5.38% and 3.17%, respectively. The waveforms presented in Figure 11b were obtained by employing the optimized power distribution with the total input power (${\delta }_p=p_{\mathrm{in}}$) as a decision variable. In these cases, the maximum values for the overshoot and undershoot were 5.01% and 3.17%, respectively. However, a noticeable current overshoot occurred during the fourth transient (when the load increased from 20% to 60%). As mentioned earlier, this is due to the energy variations required by the system to reach a higher power operating point. An improved dynamic response is observed in Figure 11c when the output current (${\delta }_p=i_{\mathrm{out}}$) is used as a decision variable. This is achieved thanks to the direct output power relationship and the wider bandwidth of the decision variable. The maximum overshoot and undershoot of the output voltage are 5.2% and 4.33%, respectively. This approach provides the best results with neither overcurrents nor erroneous power redistributions.

The experimental results for load variations with an input voltage of 230 $\mathrm{V}$ are depicted in Figure 12. The dynamic behavior when the power processed by each converter is the same is shown in Figure 12a. The maximum overshoot and undershoot values observed for the output voltage were 4.43% and 2.52%, respectively. For the optimized power sharing, with the input power as a decision variable (${\delta }_p=p_{\mathrm{in}}$), these extremes were 3.6% and 2.52%, respectively. A similar response to was observed at 110 $\mathrm{V}$ when the load is increased from 20% to 60%. Again, a high-current overshoot for converter 1 and a brief period with converter 3 turned on were verified. Finally, Figure 12c presents the results for optimized sharing with the output current as a decision variable (${\delta }_p=i_{\mathrm{out}}$). Maximum overshoot and undershoot within the five transients are 4.12% and 2.86%, respectively. Again, the best transient results are obtained with this strategy. Although the transient results are presented for the extremes of the voltage range, the system was also tested with an input voltage of 150 $\mathrm{V}$ and 190 $\mathrm{V}$. The performance is similar to what is presented in Figure 11 and Figure 12.

To conclude the analysis, Figure 13 presents a comparison of the system efficiency when operating in steady state, considering variations in the input voltage and processed power. A significant improvement was achieved with the proposed power-sharing optimization strategy, with an increment of up to 8.5% when operating with 20% of its rated power and the lowest input voltage. It is worth noticing that this maximum efficiency improvement occurs at the lowest power range of the mission profile. In this condition, equalized sharing forces all converters to operate at very low efficiency points, whereas the proposed strategy reallocates the power to fewer modules operating closer to their efficiency peaks. A comparison between the proposed strategy and other methods is presented in

Table 5. Comparison of the maximum absolute efficiency gain ($\Delta {\eta }_{\mathrm{sys}}$) reported in the literature for parallel converters, using conventional equalized power sharing as the baseline.

	[28]	[32]	[31]	[27]	[33]	Proposed Strategy
Max. absolute efficiency gain ($\Delta {\eta }_{\mathrm{sys}}$)	2%	2.8%	5.7%	6%	8%	8.5%

. The efficiency improvement values in the table are provided by each paper and are compared with the equalized power-sharing approach.

A broader statistical evaluation of the efficiency improvement across the full operating range has been conducted based on the experimental results provided in Figure 13. The average efficiency gain considering all operating points, with respect to equalized power sharing, was 2.3% for the strategy using input power as a decision variable and 2.9% when using output current in addition to input voltage. The average efficiency gain was also evaluated for each system power level, considering all input voltage conditions. The results are presented in

Table 6. Average efficiency gain for each system power level.

Decision Variable	System Power
	20%	30%	40%	60%	80%	100%
${\delta }_p=i_{\mathrm{in}}{v}_{\mathrm{in}}$	7.2%	3.6%	2.6%	0.7%	0.0%	0.0%
${\delta }_p=i_{\mathrm{out}}$	6.9%	6.1%	2.8%	1.8%	0.0%	0.0%

. As can be observed, the highest average efficiency gains occur at light load conditions. As the system power increases, more converters become active, and the optimal solution tends to converge to equalized power sharing.

5.3. System Expansion and Computational Complexity

The inclusion of the efficiency optimization strategy does not introduce significant complexity to the real-time implementation. All optimization stages are executed offline, and the real-time controller relies solely on the resulting LUTs. Furthermore, depending on the decision variables selected for the supervisory control, it is possible to implement the optimization scheme without any impact on the hardware.

Table 7. Comparison of the control system requirements between a three-phase interleaved boost converter and the proposed methodology.

Parameter	Boost Interleaved	Proposed Strategy
		${\mathit{\delta }}_{\mathit{v}}={\mathit{v}}_{\mathbf{in}}$, ${\mathit{\delta }}_{\mathit{p}}={\mathit{i}}_{\mathbf{in}}$	${\mathit{\delta }}_{\mathit{v}}={\mathit{v}}_{\mathbf{in}}$, ${\mathit{\delta }}_{\mathit{p}}={\mathit{i}}_{\mathbf{out}}$
Current sensors	3 ($i_{L,1\dots 3}$)	3 ($i_{L,1\dots 3}$)	4 ($i_{L,1\dots 3}$, $i_{\mathrm{out}}$)
Voltage sensors	1 ($v_{\mathrm{out}}$)	2 ($v_{\mathrm{in}}$, $v_{\mathrm{out}}$)	2 ($v_{\mathrm{in}}$, $v_{\mathrm{out}}$)
Current controllers	3	3	3
Voltage controllers	1	1	1
Digital filters	—	2 (${\delta }_v$, ${\delta }_p$)	2 (${\delta }_v$, ${\delta }_p$) *
2D look-up tables	—	3	3

* Recommended, but not required.

summarizes the differences between the control requirements for the conventional three-phase interleaved boost converter and the proposed strategy. The computational overhead of the proposed strategy was evaluated by counting the elementary floating-point operations (FLOPs) required per control cycle. As summarized in

Table 8. Computational cost for one instance of a PID controller and a 2D LUT.

Operation	Number of Operations
	PID	2D LUT	Conventional (4 PIDs)	Proposed (4 PIDs + 3 2D LUTs)
Additions/Subtractions	6	11	24	57
Multiplications/Divisions	7	11	28	61
Memory Accesses (Read/Write)	11	9	44	71
Logical Comparisons	2	0	8	8
Total FLOPs (approx.)	26	31	104	197

, the conventional interleaved control requires 4 PID controllers (one for voltage regulation and three for current loops). The proposed strategy adds three 2D Look-Up Table (LUT) queries with bilinear interpolation. Although the total number of operations increases from 104 to 197, this remains well within the capabilities of modern microcontrollers. For instance, in a 200 $\mathrm{M}$$\mathrm{Hz}$ processor with a dedicated Floating-Point Unit (FPU), the entire proposed algorithm is estimated to execute in less than 2 $\mathsf{\mu }$$\mathrm{s}$, which is negligible compared to typical PWM periods (20–100 $\mathsf{\mu }$$\mathrm{s}$).

In the case of system expansion with a larger number of converters, only minor modifications are required to apply the proposed strategy. In the optimization stage, it is sufficient to perform the efficiency surface fitting for the additional converters and provide the corresponding parameters. Since this step is performed offline, increasing the number of converters does not significantly affect the real-time processing requirements. In the proposed implementation, the resulting solution is stored using independent LUTs for each converter, indexed by the system operating conditions (input voltage and load power). Therefore, the size of each LUT remains unchanged, and the total memory requirement increases linearly with the number of converters. From the perspective of real-time computational cost, adding another converter to the system corresponds only to adding another individual current controller and one additional power-sharing LUT. If a properly designed LUT is used, its computational effort is significantly reduced.

Although the proposed strategy relies on an offline optimization procedure followed by LUT implementation, its performance remains robust under moderate parametric variations. In practical scenarios, factors such as component tolerances, aging, and temperature effects may introduce deviations in the efficiency surface. However, due to the smooth nature of the optimization problem, these variations tend to result only in minor shifts of the optimal operating point, without compromising the overall effectiveness of the method. As a result, the proposed approach still provides performance improvements compared to conventional equalized power sharing. For applications requiring higher adaptability, the method can be extended to include periodic updates of the LUT based on measured or estimated operating conditions, without requiring real-time optimization.

Regarding the practical implementation in multi-converter systems, it is worth noting that for systems with identical converters, the optimization problem exhibits symmetry in its solution hyperplane. This characteristic allows for a rotation of the power-sharing assignments among the modules without affecting the global efficiency. Such flexibility can be strategically used for thermal balancing by periodically rotating the converter roles over long time intervals, although the specific implementation of thermal management is beyond the scope of this work.

Finally, the impact of the proposed strategy on the system’s electromagnetic interference (EMI) profile is analyzed through the source current harmonic spectrum. Figure 14, Figure 15 and Figure 16 compare the Fast Fourier Transform (FFT) of the input current for the optimized and equalized power-sharing methods at 100%, 66%, and 33% of nominal power, respectively. At full load, both strategies converge to an identical interleaved profile with a primary harmonic component at 30 $\mathrm{k}$$\mathrm{Hz}$ (−20 dB). At partial loads, such as 33%, the optimized strategy deactivates redundant modules to maximize efficiency, which inherently reduces the interleaving cancellation effect and results in a higher low-order harmonic magnitude (−5.5 dB at 10 $\mathrm{k}$$\mathrm{Hz}$). However, this condition corresponds to a single converter operating at its rated current, a standard operating point for which EMI filters in modular systems are traditionally sized. Although a tradeoff between peak efficiency and low-frequency harmonic attenuation exists, the proposed strategy operates strictly within the hardware’s design envelope, ensuring that the efficiency gains do not compromise the physical integrity or the filtering requirements established for nominal operation.

6. Conclusions

This paper proposes an effective methodology for optimizing the global efficiency of parallel-converter systems. The problem formulation and optimization constraints were derived, and a four-stage process was presented. Owing to the inherent complexity and the possibility of multiple local and global minima, the methodology employs a genetic algorithm (GA) for global optimization. A sequential quadratic programming (SQP) algorithm provides further precision in a local optimization stage. Finally, the ambiguity-resolution stage ensures a smooth trajectory for the sharing pattern across the system power range. An active current-sharing control strategy was introduced to implement optimal sharing surfaces, offering practical insights for designers seeking to apply this methodology. The experimental results investigated two decision variables for supervisory control: the total input power and system output current. It was shown that using the output current as the decision variable provides superior performance under both transient and steady-state conditions, as it directly maps the power consumed by the load. These configurations were compared with equalized power-sharing, a widely used approach in parallel converter systems. The experimental results demonstrated that an efficiency improvement of up to 8.5% was achieved under light-load operation. This makes the proposed approach a strong candidate for optimizing the efficiency in applications whose mission profile predominantly operates in the lower half of the rated power range. Examples include battery powered systems, electric vehicles, and renewable energy generation systems (e.g., wind or photovoltaic systems). In these contexts, the proposed strategy can significantly enhance system autonomy or improve returns on investment.