Paralleling of Gallium Nitride Power Semiconductor Devices: A Review and Future Perspectives

Abstract

Wide-bandgap (WBG) semiconductors are propelling a paradigm shift in advanced power electronics, offering functionality that includes higher-switching-frequency operation with improved efficiency and power density possibilities. Gallium nitride (GaN) exhibits unique material properties that correspond to device parameters beneficial for achieving an improved performance compared to its counterparts. The inception of GaN power semiconductor devices has enabled advanced power electronics to realize efficient and compact power converters. However, the current rating of the devices is constrained, and paralleling of the devices is vital to realize high-currentrated power modules. Furthermore, paralleling of the devices can provide improved cooling results in high-power-density systems. This paper presents a comprehensive review study of the paralleling of GaN devices to discuss the different challenges associated with paralleling. One of the fundamental challenges is associated with the design of a structure for paralleling GaN devices. The parallel device structure consequently impacts the parasitics of the device, which limit the operating switching frequency and thermo-mechanical aspects. Furthermore, power loop inductance, gate loop inductance asymmetry, common-source inductance, gate inductance trace length mismatch, and different challenges lead to design trade-offs and efforts to optimize the design by realizing an appropriate trade-off, considering low-inductance packaging along with thermal strategies, and considering a parallel circuit layout and structure. Considering the recent research trends and studies related to the design of parallel GaN devices, this paper presents future perspectives anticipating the realization of an improved parallel GaN device structure.

1. Introduction

The growing need for higher efficiencies and power densities in modern power electronic systems has accelerated the transition from traditional silicon devices to wide-bandgap (WBG) semiconductors. WBG materials, silicon carbide (SiC) and gallium nitride (GaN), enable power converters to be more efficient and smaller with the ability to work at higher frequencies than traditional silicon technologies [1,2,3,4,5,6,7]. This is because they have a higher critical electric field, a higher electron saturation velocity, and better thermal conductivity. Silicon (Si) MOSFETs continue to dominate low- and medium-power applications due to their technological maturity, robust avalanche capability, and ease of paralleling resulting from the positive temperature coefficient of on-state resistance (R_DS(on)) [8]. SiC MOSFETs extend these advantages to higher-voltage and -temperature regimes, offering an improved switching performance at the expense of higher costs and increased sensitivity to parasitic elements [9,10,11,12,13].

1.1. GaN Technology Overview

Among WBG devices, GaN-based power technologies have emerged as a key enabler for next-generation power conversion systems, particularly in low- to medium-voltage, high-frequency applications. The unique properties of GaN, namely, its wide bandgap, high electron mobility, and superior breakdown strength, facilitate fast switching with minimal conduction and switching losses [7,8,9,10,14,15,16,17,18,19,20]. GaN power transistors are classified by their device geometries, substrates, and operating modes, as illustrated in Figure 1 [21,22]. Lateral GaN devices, typically realized on silicon substrates (GaN-on-Si), dominate low- to mid-voltage applications and are available in enhancement mode (E-mode) and depletion mode (D-mode), with the latter commonly used in cascode configurations [15,16,17]. Vertical GaN devices, fabricated on native GaN substrates (GaN-on-GaN), target high-voltage applications above 650 V and remain an emerging technology [18,19,20].

At present, lateral GaN HEMTs fabricated on silicon substrates dominate the commercial GaN power device market, typically supporting voltage ratings up to 650 V [18,21,22,23]. E-mode GaN HEMTs, which are normally OFF at zero gate bias, are preferred for power electronic applications due to their inherent fail-safe operation and compatibility with conventional gate drive circuits [24,25]. As a result, major semiconductor manufacturers such as Infineon Technologies-GaN Systems, EPC, Navitas Semiconductor, STMicroelectronics, and Innoscience have commercialized E-mode GaN devices for applications ranging from compact consumer fast chargers and data centers to solar inverters and motor drives [26]. Depletion-mode GaN devices (normally ON) are commonly employed in cascode structures using a low-voltage silicon MOSFET to achieve normally OFF behavior. Cascode GaN solutions offer improved ruggedness and ease of gate driving and have been commercialized by companies such as Transphorm, Infineon, Microchip Technology, and ON Semiconductor, particularly for industrial and higher-voltage applications [27,28,29,30,31].

To further reduce system complexity and enhance reliability, integrated GaN power ICs have been developed, combining the GaN power switch with gate drivers, protection circuits, and control logic within a single package. This high level of integration minimizes parasitic inductances, improves switching performance, and simplifies system design [32,33,34,35]. Leading suppliers including Navitas Semiconductor, Texas Instruments, Power Integrations, and STMicroelectronics have introduced integrated GaN solutions optimized for high-frequency and high-power-density converters [18,36]. At the same time, GaN Schottky diodes are getting attention for high-speed rectification because they have very low reverse-recovery losses. This makes them great for high-frequency power factor correction (PFC) and resonant converter applications [37,38,39,40,41,42]. The main types of GaN power devices are listed in

Table 1. Types of GaN devices and major manufacturing companies.

GaN Device Type	Description/Key Features	Typical Voltage Range	Manufacturer
Enhancement Mode (E-mode) (Lateral)	Normally OFF, safe operation, MOSFET-like control	100–650 V	GaN Systems (Infineon), Navitas, EPC, Transphorm (Renesas), Panasonic, Sanken, ExaGaN
Depletion Mode (D-mode) (Lateral)	Normally ON, used in cascode structures	600–900 V	Transphorm (Renesas), VisIC, ON Semiconductor
Cascode GaN (GaN + Si MOSFET) (Lateral)	Normally OFF, rugged	600–900 V	Transphorm (Renesas), Infineon, Microchip, ON Semiconductor
Integrated System-on-Chip GaN (E-mode)	Normally OFF, GaN switch with gate driver and protection in one package	≤650 V	Navitas, Texas Instruments, Power Integrations, STMicroelectronics, Cambridge GaN Devices
Vertical GaN Devices	High-voltage and -current capability, emerging technology	>1200 V	Panasonic, Infineon, ROHM (R&D/pilot stage), Mitsubishi Electric

with their most important features, their usual voltage ranges, and some of the companies that make them.

In addition to the technical advantages, favorable market conditions are contributing to the ongoing and speedy commercialization of GaN power devices. The market for power GaN devices is expanding rapidly on a global scale. Figure 2 shows the switching frequency vs. power capabilities of Si, SiC, and GaN devices (left), along with the voltage–current ratings of GaN devices, categorized by manufacturing company (right) [42].

1.2. GaN Paralleling Technology Overview

The evolving ecosystem demonstrates the growing significance of scalable, high-current-capable GaN technology that is expanding the increasing demand for different applications, such as high-frequency telecommunications, electric mobility, data centers, consumer rapid chargers, and renewable energy systems. This is anticipated to alter the competitive environment in addition to maintaining the strong compound annual growth rate of the GaN device market, as shown in Figure 3. As new businesses and vertically integrated solutions become more popular, the market share of established players will gradually change [40,41,42,43,44,45,46]. In order to accommodate upcoming high-power applications, considerable research has been done on sophisticated packaging, dependable device paralleling, and system-level optimization [47,48,49,50].

Although the number of GaN power devices is rapidly increasing and diversifying, a single lateral GaN HEMT is still insufficient to manage sufficient current. Paralleling of GaN devices is paramount for high-power applications [46,47,48,49,50]. The primary objective of device paralleling is to create a GaN-based high-current converter to meet high-power-rating requirements. This objective include power density, efficiency, performance, and thermal control. Devices must be efficiently paralleled and employ sophisticated thermal management techniques to extend their lifespans [48,51,52,53,54,55]. Paralleling requires multi-objective trade-offs to ensure that heat is distributed uniformly, the switching behavior is synchronized, the static and dynamic current sharing is equal, and the system is highly reliable [56].

However, there are significant technological issues that must be resolved in order to ensure that GaN HEMTs function properly and remain stable. One of the primary difficulties is device parameter mismatch, which occurs when manufacturing tolerances cause variations in the threshold voltage (V_TH), transconductance (g_m), and R_DS(on), which lead to the uneven distribution of the current [40,41,57,58,59,60]. These imbalances may create problems such as early device failure, localized thermal overload, or even catastrophic damage if they are not taken care of [53,54]. These issues could make controlling heat dissipation in high-power-density GaN systems much more difficult. Strong thermal coupling between adjacent devices can accelerate parameter drift, complicate current sharing, and, in difficult situations, result in thermal runaway [61,62,63]. Turn-on and turn-off transitions in GaN HEMTs occur in nanoseconds, making the issue worse. Switching can occur at different times due to even slight variations in the gate loop inductance, gate drive conditions, or device capacitances. This type of desynchronization can result in excessive voltage overshoot, increased switching losses, and an increased chance of avalanche-related failure mechanisms [64,65,66]. Furthermore, high-frequency oscillations and electromagnetic interference (EMI) can be caused by parasitic inductances from packaging and connecting structures, which further complicates steady operation [67,68,69,70]. It can be very hard for them to keep things cool and even out the heat when they work hard to get rid of parasitic elements [71,72].

The research and findings have been progressing to make sure that parallel-connected power devices work reliably. To get all the devices to behave the same way, it is important to make sure that the electrical symmetry is correct by using symmetrical gate signal routing, low-inductance layouts, and balanced power distribution networks [73,74,75]. At the same time, advanced thermal management techniques reduce temperature differences by using materials that conduct heat well, structures that are designed to dissipate heat well, and engineered substrates [76,77]. Innovations in gate drive technology, such as multi-channel isolated drivers, adaptive timing correction circuits, and active gate waveform control [70,78,79], have made switching synchronization better. Pre-screening, active current-sharing circuits, and parametric sorting (binning) are some of the methods used to make up for the fact that device parameters can change on their own. Moreover, packaging innovations simultaneously tackle electrical and thermal needs; contemporary multichip modules (MCMs) are engineered with inherently low parasitic inductance and incorporate thermal management capabilities directly into their design [66,80,81,82,83,84,85,86,87,88,89].

1.3. Review Objectives and Contributions

This article provides a thorough analysis of GaN HEMT paralleling methods, providing a critical synthesis of the problems and solutions reported in the literature from a multidimensional perspective. This review does not examine gate drive, thermal, and electrical issues independently. Rather, it examines how thermal interactions, dynamic current sharing, and parasitic effects combine to impact system performance and reliability. The organization and specific objectives and contributions of this review are as follows:

1. Section 2 outlines the GaN device technology overview and parameter variations to provide a comprehensive review of the GaN power device types (E-mode, D-mode, cascode, integrated ICs), their operating principles, and the key characteristics relevant to paralleled operation, considering parametric variations.

2. Section 3 describes the significance of the layout, parasitic inductance analysis, and packaging strategies to quantify the impact of the power loop, common-source, and gate loop inductances on the switching performance, current sharing, and voltage overshoot in paralleled GaN systems.

3. Section 4 demonstrates the parallel GaN power module system design and configurations to quantify the impact of the power loop, common-source, and gate loop inductances on the switching performance, current sharing, and voltage overshoot in paralleled GaN systems.

4. Section 5 investigates and demonstrates the thermal management and electrothermal effect to review advanced cooling architectures and their impacts on thermal symmetry, with consistent thermal metrics for evaluating package performances, and to examine the relationship between junction temperature gradients and current imbalance, quantifying how temperature differences translate to steady-state and transient current-sharing errors.

5. Section 6 provides a discussion on future perspectives to propose a normalized comparison framework enabling a consistent evaluation of the efficiency, power density, and switching frequency claims across different studies, and to synthesize acceptable mismatch limits for industrial GaN power modules, providing designers with quantitative targets for device selection, layout design, and gate drive implementation.

2. GaN Device Technologies and Parameter Effect on Paralleling

GaN power devices have rapidly evolved over the past two decades, and most GaN power devices available on the market are lateral AlGaN/GaN HEMTs made on silicon substrates [25,45,46]. The device technologies have distinctive typical device parameter values and an electrothermal effect that is crucial for the paralleling of GaN devices. Therefore, in this section, we discuss the device technologies, parametric variations, and temperature dependencies, considering the effects of variations in the parameters on device paralleling.

2.1. GaN Device Technologies

A comparison of GaN technologies (D-mode HEMTs, cascode D-mode HEMTs, E-mode HEMTs, vertical GaN FETs) is summarized in

Table 2. Comparison of different types of GaN FETs.

Category	D-Mode HEMT	Cascode D-Mode HEMT	E-Mode HEMT	Vertical GaN FET
Switching Performance	High speed	Medium speed	High speed	Medium speed
Capacitance	Lower gate/output capacitor	Higher gate/output capacitor	Lower gate/output capacitor	Lower gate/output capacitor
Gate Drive Complexity	Moderate	Simpler	Simpler	Simpler
Gate Drive Voltage Polarity	Negative	Positive	Positive	Positive
Gate Drive Voltage Level	Medium (~20 V)	Medium (~20 V)	Low (~5 V)	Medium (~20 V)
Cost	Cheapest	Medium	Medium	Higher

, considering different parameters: device rating, switching states, switching performance, and gate driving. This subsection elaborates on GaN device technologies: E-mode GaN HEMTs, D-mode GaN HEMTs, cascode GaN devices, integrated GaN power ICs, and new vertical GaN devices.

2.1.1. Enhancement-Mode (E-Mode) GaN HEMTs

E-mode GaN HEMTs are normally OFF devices, meaning that no conduction occurs at zero gate bias. This behavior is essential for safe operation in power electronic systems and simplifies gate drive design [72,82]. E-mode GaN HEMTs (Figure 4) are widely used in commercial power converters due to their compatibility with common control and protection systems.

E-mode GaN HEMTs can switch quickly and with less power loss thanks to their lateral structure, very low gate charge, and output capacitance. Because of this, they are excellent for applications that require low-to-medium voltages and high frequencies [24,29,30,31,32,33,34,35,36].

2.1.2. Depletion-Mode (D-Mode) GaN HEMTs

The 2-DEG channel conducts even with the gate bias at zero since D-mode GaN HEMTs are always-on devices. Although D-mode devices have excellent built-in performance and durability, their “normally on” nature creates safety issues and makes system-level implementation more difficult [19]. As a result, D-mode GaN devices are typically employed as the primary switching element in cascode configurations rather than directly in power converters [31,64,68].

From a structural standpoint, D-mode devices retain a continuous 2-DEG under the gate, resulting in low on-resistance and high g_m [31]. Their superior intrinsic characteristics make them attractive for high-performance applications when combined with appropriate normally OFF architectures. Figure 5 illustrates the fundamental structural difference between D-mode and E-mode GaN HEMTs in terms of channel depletion beneath the gate.

2.1.3. Cascode GaN Devices

Cascode GaN devices combine a depletion-mode GaN HEMT with a low-voltage silicon MOSFET connected in series. This configuration achieves normally OFF operation while retaining many of the high-speed and low-loss advantages of GaN technology [31,63,64]. The silicon MOSFET controls turn-on and turn-off, while the GaN device supports the majority of the voltage and current stress during operation, as shown in Figure 6.

Structurally, the cascode approach separates the control and high-speed-switching functions, improving ruggedness and ease of gate driving. However, the presence of two semiconductor devices introduces additional parasitic elements and can limit the ultimate switching speed compared to monolithic E-mode GaN HEMTs [64].

2.1.4. Vertical GaN Power Devices

In order to overcome the issues that lateral GaN device topologies have with managing voltage and current, vertical GaN power devices have emerged as a viable solution [27,34]. Because the current travels over the substrate in vertical patterns, larger n-GaN drift layers and significantly greater breakdown voltages (typically above 1200 V) are possible. The design of this device facilitates improved heat escape through the substrate and increases the uniformity of the electric field [34]. Examples of vertical GaN device structures, including trench-gate and planar MOSFET designs, are shown in Figure 7.

The gate electrode in planar GaN MOSFETs is made on the surface of the GaN drift layer. This makes the process of making them easier and makes the gate more reliable. But the planar structure usually has a lower channel density and a higher specific R_DS(on) because the current does not spread out as much. Trench GaN MOSFETs, in contrast, have a gate electrode that is built into etched trenches. This makes it possible for vertical channels to form and greatly increases the channel density. This design not only lowers the specific on-resistance and increases the current capacity but also makes trench etching, gate oxide reliability, and electric-field crowding at the trench corners more difficult. To find the right balance between performance and long-term reliability in trench-based vertical GaN devices, careful design and process optimization are needed [72].

Even though vertical GaN power devices have a lot of performance benefits, they are still mostly only used in research and pilot-scale development. The primary issues are the scarcity of large-area, low-defect bulk GaN substrates, the necessity for stringent defect control in thick drift layers, and the high cost and complexity of their production [27].

2.1.5. Integrated GaN Power ICs

To further enhance system integration, performance consistency, and reliability, integrated GaN power ICs have been developed, leveraging the intrinsic advantages of gallium nitride as a wide-bandgap semiconductor capable of sustaining high electric fields and supporting high carrier densities. The AlGaN/GaN heteroepitaxial structure enables the formation of a high-mobility two-dimensional electron gas (2-DEG), which significantly reduces channel and drift region resistance compared to both silicon and silicon carbide devices, thereby facilitating high-efficiency, high-frequency operation. By adopting lateral device architectures, GaN power ICs achieve extremely low parasitic charges and enable the monolithic integration of the GaN power transistor with gate drivers, protection circuits, and, in some cases, control and logic functions within a single package [25,28,29,30,31]. Such integration markedly minimizes external gate loop parasitics, improves switching uniformity, and enhances electromagnetic compatibility, making these devices particularly attractive for compact, high-power-density converter applications [36,37,38]. Recent process platforms, such as AllGaN™ power IC technology, demonstrated the feasibility of monolithically integrating 650 V GaN FETs with drive, logic, voltage regulation, and ESD protection entirely in GaN, as illustrated in Figure 8 [47].

2.2. Parameter Variations and Temperature Dependencies

Device parameter variations are unavoidable due to manufacturing process complexities. The temperature dependency of the parameters makes the device performance and reliability crucial at system-level operation. Furthermore, in the case of paralleling, the device parameter distribution with temperature dependencies can result in severe dynamic current unbalancing, causing failure issues.

Table 3. Statistical distributions and temperature coefficients for GaN HEMTs.

Parameter	Device Type	Typical Value	Standard Deviation	Temperature Coefficient	Measurement Conditions	References
Threshold Voltage (VTH)	E-mode GaN (p-GaN gate)	1.2–1.8 V	A 15% variation due to measurement bias conditions	−2 to −4 mV/°C	Id = 1 mA/mm, Vds = 10 V	[14,18,22,82]
	Cascode GaN	1.5–2.5 V	σ = 100–150 mV (from Si MOSFET variation)	−1 to −3 mV/°C (dominated by Si MOSFET)	Vds = 10 V	[31,64]
	Integrated GaN IC	1.0–1.5 V	Simulated Monte Carlo: σ = 0.33–0.60 V (UVLO), matched on-chip	−1.5 to −2.5 mV/°C (estimated)	Pulsed measurement	[36,44,45,83]
	GaN-on-diamond HEMT	~1.2 V	Not specified	−0.2 mV/K (25–125 °C)	25–125 °C	[84]
On-Resistance RDS(on)	650 V E-mode (25 °C)	50–70 mΩ	σ = 5–8 mΩ (10–15%) from lot variation	+0.4 to +0.6%/°C	Vgs = 6 V, Id = 20 A	[18,22,23]
	650 V E-mode (150 °C)	70–95 mΩ	-	+0.4 to +0.6%/°C	Vgs = 6 V, Id = 20 A	[18,22,23]
	100 V E-mode (EPC2065)	3.6 mΩ at 25 °C	Not specified	Not specified	GIT device	[85]
	Cascode GaN (650 V)	100–150 mΩ	Increases under high-voltage stress	+0.2 to +0.4%/°C (Si MOSFET-dominated)	Tj = 25 °C	[31,64]
	1200 V E-mode GaN	~70 mΩ (est.)	Not specified	63% decrease (RT to −150 °C)	Cryogenic	[86]
Transconductance (gm)	E-mode GaN	20–35 S	Not specified	−0.2 to −0.4%/°C	Peak gm at Vds = 10 V	[22,28]
	Cascode GaN	15–25 S	Not specified	−0.15 to −0.3%/°C (estimated)	Vds = 10 V	[31,64]
	1200 V E-mode GaN	~12 S (est.)	Not specified	1.34× increase (RT to −178 °C)	Cryogenic	[86]

summarizes reported statistical distributions and temperature coefficients for enhancement-mode, cascode, and integrated GaN devices for the V_TH, R_DS(on), and g_m.

2.3. Effects of Parameters on Paralleling of GaN Devices

Paralleling power semiconductor switches are a widely adopted technique to increase the current capacity, enhance the thermal performance, and improve the power density in high-performance power electronic systems [33,40,47]. The reliable operation of parallel-connected GaN power devices requires the careful management of both the intrinsic device characteristics and system-level design parameters [53,54]. The V_TH critically determines the turn-on and turn-off timing; small variations cause lower-V_TH devices to conduct earlier, resulting in transient current overshoot, increased switching losses, and localized heating [40,63]. Similarly, the g_m governs the current rise and fall rates during switching, and mismatch leads to unequal dynamic current sharing, with higher-g_m devices experiencing elevated transient stress [63,64]. Static current sharing is primarily influenced by the R_DS(on); however, GaN HEMTs exhibit a weak or negative temperature coefficient at high current densities, limiting inherent self-balancing and increasing the sensitivity to parameter mismatch [47].

Table 4. Critical system parameters for parallel-connected power semiconductor switches.

Design Parameter	Effect on Paralleling	Desired Characteristics
Gate threshold voltage, VTH	Determines turn-on and turn-off timing; lower-VTH devices turn on earlier, leading to transient current overshoot and increased switching losses	Tight parameter distribution; minimal temperature dependence or positive temperature coefficient
Transconductance, gm	Governs current rise and fall rates during switching; mismatch results in unequal dynamic current sharing during transients	Narrow distribution; temperature-independent or slightly negative temperature coefficient
On-state resistance, RDS(on)	Dominant factor for steady-state (static) current sharing during conduction; lower-resistance devices conduct more current	Positive temperature coefficient to enable inherent current self-balancing
Junction temperature	Junction temperature variations modify electrical parameters, potentially leading to static or dynamic current imbalance and thermal runaway	Uniform thermal paths; common heatsink or substrate to equalize junction temperatures
Gate-driver circuitry	Influences switching synchronization and current commutation paths between parallel devices; asymmetry causes timing skew and dynamic imbalance	Symmetrical gate drive architecture; matched gate resistance and interconnect impedance
Circuit layout and parasitics	Parasitic inductance and resistance mismatch cause dynamic current imbalance, voltage overshoot, and EMI, especially in high-speed GaN switches	Minimized and closely matched parasitic inductance and resistance in gate and power loops

summarizes the key device- and system-level parameters governing static and dynamic current sharing in parallel-connected GaN power devices.

3. Parallel System Layout and Design

3.1. Packaging Technology

Beyond the intrinsic device parameters, the device packages and circuit-level factors strongly influence the paralleling performance in GaN-based converters. It is important to minimize the parasitic inductance of the package and layout design to exploit the high-frequency advantage of GaN power devices [73]. Package inductance has been minimized by using distinct packaging technology adopted by the device manufacturers considering the appropriate thermal dissipation to realize high-frequency switching at different power levels [73,74,75,76]. The EPC manufacturer uses the Land Grid Array (LGA) package for high-voltage lateral GaN devices (eGaN), with a total package inductance less than 0.2 nH [73]. The GaN system manufacturer’s (Infineon) GaNPX package also claims a total package inductance of 0.2 nH for lower-voltage-application GaN devices and 0.5 nH for high-voltage-application GaN devices [77,78]. The SMD packaging technology has taken a significant leap to reduce the package parasitic inductance compared to the conventional TO220, TO247, D2PAK, DPAK and SO8 packages [74,76,77,78]. PQFN wire bonds and PQFN copper clip packaging technology have significantly improved the total package inductance compared to conventional packaging but is on the higher side compared to LGA and GaNPX technology. The advanced SMD package of GaN devices leverages the high-frequency switching potential. The discrete SMD packages consisting of single GaN devices need to be connected through the circuit layout to form a half bridge, but connecting multiple devices in parallel to realize high-current capability can lead to the high-parasitic-inductance issue [76].

3.2. Fundamental Layout Challenges

The layout design faces significant challenges in minimizing the total parasitics of the circuit layout design. The highly crucial parasitic inductances are as follows in priority order: common-source inductance (CSI), quasi-common-source inductance (QCSI), mutual inductance (M), power loop inductance, and gate loop inductance [76,79,80,81,87,88,89,90,91,92,93]. CSI is the inductance part of the gate-driver loop, as well as the drain to the source power current loop. The mutual inductance between the self-inductance of the gate-driver loop and the power loop contributes to the additional CSI [52,89,90]. In addition, the kelvin terminal is employed to minimize the interaction of the gate loop and power loop; however, it cannot fully eliminate this interaction due to QCSI, resulting in a similar effect to that of CSI. CSI can be more critical in the case of the paralleling of GaN devices operating at very high dv/dt and di/dt; therefore, CSI is the most significant factor that potentially causes the ringing across the drain source as well as the gate source voltage and is considered extremely high priority for designing the circuit layout for the paralleling of the devices. Also, higher CSI reduces the effective gate current and voltage that ultimately slow down the switching speed, resulting in higher switching losses.

The parasitic minimization of the layout design is not limited only to CSI, but CSI is considered to be of primary importance, with the consideration of the other power loop inductances and gate loop inductances as well, to minimize the ringing, overshoot, and EMI issues [40,41]. The second most highly critical parasitic parameter is the commutation loop inductance, which consists of the drain inductances L_D1, L_D2, L_D3, and L_D4 and the DC busbar side inductances L_Lp1 and L_Lp2. The commutation loop inductance comprises the drain parasitic inductance, the loop inductance/busbar inductance from the drain terminal of the device to the DC voltage capacitor, and the ESL of the DC voltage capacitor. This combined effect can generate very high drain–source voltage (V_ds) overshoot during the turn-off condition. The gate inductance (L_G) increases the V_GS overshoot and ringing, which is sophisticated in the case of GaN devices considering the smaller gate voltage levels and margins.

The schematic of two parallel GaN half bridges in Figure 9 represents the different parasitic/stray inductances associated in the circuit layout as follows: L_CS1, L_CS2, L_CS3 and L_CS4 are the common-source inductances for the high side–low side of half bridge 1 and half bridge 2; L_C1, L_C2, L_S1, L_S2, and L_C12 and L_C3, L_C4, L_S3, and L_S4 are the quasi-common-source inductances for the high side–low side of half bridge 1 and half bridge 2; L_D1, L_D2, L_D3, L_D4, L_Lp1, and L_Lp2 are the high-frequency power loop–commutation loop inductances; L_G1, L_G2, L_G3, and L_G4; L₁, L₂, L₃, and L₄ are the gate inductances of the high side–low side of half bridge 1 and half bridge 2. In addition, the mutual inductances M₁, M₂ and M₃, M₄ between the power loop and gate-driver loop contribute the total CSI between the loops [89,90,94,95]. The geometric position of the source and return current governs the mutual inductance, resulting in the increase or decrease in the effective mutual inductance [89,90]. These parasitic inductances, including the mutual inductance, should be minimum and balanced to anticipate the best performance of the parallel GaN device system. It is a trade-off between different parasitic inductances, and optimization can be considered based on the extremely high-priority and medium- to low-priority inductances. The common-source inductance, quasi-common-source inductance, and mutual inductance are considered extremely high priority, the high-frequency power loop–commutation loop inductance is considered high priority, and the gate drive loop inductance is considered medium priority for most design applications [52,95].

The inherently low input and output capacitances of GaN HEMTs interact with unavoidable stray inductances to create underdamped resonant circuits [89]. These circuits can oscillate at frequencies ranging from tens to hundreds of megahertz, increasing electromagnetic interference (EMI) and switching losses while threatening device reliability through voltage overshoot and unpredictable gate behavior [40]. Therefore, considering all these critical aspects, the layout design becomes more complex for paralleling, as the anticipated goal is to minimize the parasitics, but this requires balanced parasitics among the parallel devices [52,73,91,92,93,94,95].

3.3. Parallel GaN Devices and Module

The ideal paralleling of the devices requires a perfectly shared dynamic and static current among the parallel-connected devices. Nevertheless, system layout and design challenges with the switching speed of GaN HEMT devices makes it extremely challenging to realize paralleling of the devices, anticipating ideal possibilities. High-speed GaN HEMT devices are characterized by a rate of change of the current di/dt during turn-on and the voltage dv/dt during turn-off that might exceed 100 A/ns and 100 V/ns, which amplifies the critical effect of the parasitic and balanced layout design [80,89]. In cases of high switching frequencies, the dynamic current sharing imbalance becomes more pivotal with unbalanced switching losses and localized heating that can easily lead to long-term reliability issues and thermal breakdown [47].

Compared to the discrete parallel devices in the half-bridge configuration, paralleling of the half bridges as depicted in Figure 10, possibly can minimize the common-source inductance of the high side device mismatch possibility that effectively can reduce the sophistication of the parallel and help in realizing lower current unbalancing as well as ringing [96].

The common-source inductance added by the PCB layout must have minimum interaction with the gate drive loop and high-frequency power loop. Further, the optimized layout design requires the appropriate use of lateral power loops and vertical power loops to minimize the return path, consequently minimizing the parasitic inductance. DC-link capacitors must be positioned to minimize high-frequency loop areas, ideally located centrally with respect to parallel devices [89]. This is authenticated in [73], in which distributed high-frequency loops for four parallel-connected GaN transistors are deployed. In the first design, the four are in close proximity to operate as a single power device, with a single high-frequency power loop. The distributed high-frequency loops with the appropriate central location of DC-link capacitors realizes the loop inductance (L_Lp ≈ 0.4 nH). In contrast, the four parallel transistors are located in close proximity, acting as a single power device and resulting in significantly increased high-frequency loop inductance and non-homogenous parasitics, as their individual power loops are different (L_Lp ≈ 1.7–2.6 nH), helping to realize better current sharing and a better thermal performance with improved system efficiency.

The paralleling of the devices enables the realization of the high-current system possibility using GaN devices, as well as a decrease in system losses for the system application with dominant conduction losses [88]. A comparison is demonstrated in [88] that represents the significant improvement in the system losses for three parallel GaN HEMTs and four parallel GaN HEMTs as the paralleling of the devices effectively reduces the R_DS(on), responsible for the dominant conduction losses. Nevertheless, the parallel intensifies the system sophistication. This intensified system sophistication requires challenging and innovative layout design solutions considering multiple CSIs, multiple high-frequency power loops and gate-driving loops, and the optimization and balancing of parasitic/stray inductances.

Table 5. Comparison of parasitic inductance types in GaN circuits.

Inductance Type	Primary Impacts	Relative Importance	Key References
Common-source inductance (LCS1, LCS2, LCS3, LCS4)	Feedback di/dt to gate source voltage Causes potential ringing in gate source voltage Current sharing	★★★★★	[40,52,88,93]
Quasi-common-source inductance (LC1, LC2, LS1, LS2, LC12 and LC3, LC4, LS3, LS4)	Feedback di/dt to gate source voltage Causes potential ringing in gate source voltage Current sharing	★★★★★	[52,88]
Mutual inductance (M1, M2 and M3, M4)	Feedback di/dt to gate source voltage Causes potential ringing in gate source voltage Mainly impacts during turn-on of device and can cause high unbalanced current if very high and unbalanced	★★★★☆	[52,88]
Power loop/commutation loop inductance (LD1, LD2, LD3, LD4, LLp1, LLp2)	Increases Vds spike during turn-off	★★★★☆	[52,83,95]
Gate loop inductance (LG1, LG2, LG3, LG4; L1, L2, L3, L4)	Increases Vgs ringing Susceptible to gate oscillations if highly unbalanced	★★★☆☆	[40,52,88]

Key: ★★★★★ = Extremely high, ★★★★☆ = high, ★★★☆☆ = moderate.

summarizes the different parasitic inductance types in GaN circuits and their relative importances. Common-source inductance has the highest impact, as it resides in both power and gate loops, reducing the effective gate drive voltage [40,88]. At 0.5 nH, common-source inductance increases switching losses by 25–30% due to partial turn-off [88], and mismatch exceeding 1.5 nH creates 80–120 MHz oscillations [93]. Power loop inductance affects voltage overshoot and losses [95]. Gate loop inductance contributes to delay mismatch, with optimized designs achieving 0.29–0.34 nH [60]. Advanced packaging techniques (copper clips, double-sided cooling, U-type housing) significantly reduce all parasitic inductance types while maintaining the thermal performance and safety clearance [60,66,96,97,98,99,100].

The interesting and significant point to mention here is that power loop commutation inductance and common-source inductance minimization is required to achieve high-switching-frequency operation; however, lower power loop commutation inductance and common-source inductance are prone to higher current unbalancing corresponding to smaller differences in parasitic inductance (Figure 11) variations, which can be as small as 0.1 nH for a single-phase GaN-based buck converter with two half bridges operating in parallel with an input voltage (V_in) of 48 V, an output voltage (V_out) of 12 V, and an output current (I_out) of 25 A [73,88,93]. The nominal drain inductance for Figure 11a was set to 0.3 nH for one of the half bridges, and the nominal CSI for one of the half bridges was set to 0.1 nH (Figure 11b). Furthermore, higher common-source inductance leads to increased ringing and overshoot in the gate voltage as well as drain–source voltage. Similarly, higher power loop commutation inductance results in increased ringing and overshoot in the drain–source voltage with an increase in the unbalanced loop inductance.

The current imbalance (I_imb) is expressed in [73] as:

$${\mathrm{I}}_{\mathrm{i}\mathrm{m}\mathrm{b}}={\displaystyle \frac{\Delta \mathrm{I}}{\mathrm{I}}}={\displaystyle \frac{{\mathrm{I}}_{\mathrm{d}\mathrm{s}1}-{\mathrm{I}}_{\mathrm{d}\mathrm{s}2}}{{\mathrm{I}}_{\mathrm{d}\mathrm{s}1}+{\mathrm{I}}_{\mathrm{d}\mathrm{s}2}}}$$

The imbalance criterion can be derived from the fundamental relationship between the parasitic mismatch and transient current distribution discussed in [40,83]. The criteria are defined for two paralleled GaN devices with inductances L₁ and L₂ in their respective commutation paths, and the current-sharing mismatch during switching transients is expressed in [40] as follows:

$${\displaystyle \frac{\Delta \mathrm{I}}{\mathrm{I}}}={\displaystyle \frac{\Delta \mathrm{L}}{{\mathrm{L}}_{\mathrm{a}\mathrm{v}\mathrm{g}}}}\times {\displaystyle \frac{di}{dt}}\times {\displaystyle \frac{{\mathrm{t}}_{\mathrm{r}\mathrm{i}\mathrm{s}\mathrm{e}}}{{\mathrm{I}}_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}}}$$

where ΔL = |L₁ − L₂| is the inductance mismatch in the power loop inductance; L_avg is the average inductance of the power loop inductance of the paralleled devices; di/dt is the switching slew rate; t_rise is the current rise time; and I_load is the load current. In [40], the authors experimentally validated this relationship for 650 V GaN devices, considering di/dt = 5 A/ns, t_rise = 3 ns, I_load = 30 A, and L_avg = 5 nH, with the equation yielding 10%.

Thus, keeping ΔL < 1 nH maintains the transient current imbalance below 10% for these typical operating conditions. The measurements with 1.2 nH mismatch showed a 12–15% current imbalance, confirming the analytical relationship [40]. Figure 12 illustrates the relationship between the inductance mismatch (ΔL) and current imbalance in paralleled GaN devices, based on the analytical model and experimental data reported in [40]. Using typical values for 650 V GaN devices and a switching slew rate (di/dt) of 5 A/ns, a current rise time (t_rise) of 3 ns, a load current (I_load) of 30 A, and an average inductance (L_avg) of 5 nH, the model predicts a linear increase in the current imbalance with inductance mismatch. At ΔL = 1.0 nH, the predicted imbalance is 10%. The experimental validation point, shown as a marker in the figure, confirms this relationship: with 1.2 nH inductance mismatch, the authors of [40] measured a 12–15% current imbalance (plotted as 13.5%, the midpoint).

4. GaN Power Converters and Parallel GaN Power Module System

The industry is looking for GaN power converters with ultra-high-power densities (more than 10 kW/L), conversion efficiencies greater than 99%, and switching frequencies in the megahertz region [46,47]. This direction is also supported by market trends. It has been projected that the swift advances in 5G telecommunications, electric mobility, and smaller consumer fast-charging technologies will drive a nearly 30% compound annual growth rate (CAGR) in the global market for GaN power devices [43,45,46]. A comparison of the performances of GaN-based power converters is summarized in

Table 6. Comparative performance summary of GaN-based power converters with consistent boundary conditions.

Reference	Topology	Voltage/Current	Switching Condition	Frequency	Reported Efficiency	Power Density/Dimensions	Thermal Management	Parasitic Metrics
[38]	LLC resonant converter	400 V/12.5 A	Soft-switched (ZVS)	1 MHz	97.5%	12.5 kW/L	Liquid cooling	Not reported
[39]	Totem-pole PFC	230 VAC/6.25 A	Hard-switched (CCM)	65 kHz	98.7%	Not reported	Forced air	Not reported
[50]	On-board charger	400 V/30 A	Soft-switched	500 kHz	99.0%	Not reported	Not specified	Not reported
[66]	Half-bridge power module	48 V/328 A (DPT) 48 V/5 kW (inverter)	Hard-switched	20 kHz (inverter)	96.1% (buck converter)	44 × 79 × 10 mm	Liquid cooling (10 L/min) or forced air	Lloop = 1.14–1.175 nH
[73]	DC-DC converter	400 V/20 A	Soft-switched (ZVS)	1 MHz	98.5%	Not reported	Not specified	Not reported
[92]	DC-DC converter	400 V/60 A	Hard-switched	100 kHz	98.9%	Not reported	Not specified	Not reported
[97]	Power module	400 V/35 A	Hard-switched	100 kHz	99.1%	12.7 kW/L	IMS substrate	Not reported
[98]	Traction inverter module	400 V/150 A	Hard-switched	100 kHz	99.3%	14.5 kW/L	Double-sided cooling	Lloop < 5 nH
[99]	Integrated power module	650 V/not specified	Hard-switched	Not specified	Not reported	Not specified	Top-side cooling	Lloop = 2.65 nH

to provide an insight into the reported performances considering the switching frequency, efficiency, thermal management, and converter rating. The abbreviations are defined as follows: DPT: double-pulse test; CCM: continuous conduction mode; ZVS: zero-voltage switching.

4.1. Quantitative Impact of Parasitic Inductance on Power Losses

The influence of power loop inductance on GaN transistor losses is presented in [95], where the authors used a synchronous buck converter with GS66504B devices (650 V, 15 A) operating at 400 V input, 200 V output, 300 W, and 100 kHz. Through LTSpice simulations, the authors quantified the relationship between power loop inductance and high-side transistor losses under both continuous conduction mode (CCM) and synchronous conduction mode (SCM) operations. The simulations revealed distinctly different behaviors depending on the switching mode, as shown in Figure 13.

During hard switching (CCM), larger inductance slightly reduces loss by delaying current commutation and reducing voltage–current overlap. However, during soft switching (SCM), larger inductance significantly increases loss. At 1 nH, the loss is 1.08 W, but this increases progressively to 1.43 W at 5 nH, representing a 32% increase in loss. This phenomenon is attributed to soft-switching losses that become more pronounced with higher loop inductance [27,95].

The effects of common-source inductance and power loop inductance on GaN devices are presented in [100]. Figure 14 shows the influence of parasitic inductances on the power loss of a half-bridge GaN module operating at V_in = 12 V, V_out = 1.2 V, f_sw = 1 MHz, and I_out = 20 A. As the common-source inductance (CSI) increases from 0 to approximately 1 nH, the total power loss rises significantly from about 3.5 W to 5.3 W, indicating the strong sensitivity of the switching performance to CSI due to the negative feedback introduced in the gate loop, which slows switching transitions and increases switching energy. In contrast, the power loop inductance shows a more gradual impact, where the power loss increases from approximately 3.35 W to 4.2 W as the inductance rises from 0 to 3 nH. Although power loop inductance contributes to voltage overshoot and ringing, its effect on overall loss is smaller than that of CSI.

The effect of common-source inductance on GaN devices is presented in [88]. The common-source inductance appears in both power and gate loops, creating negative feedback that reduces the effective gate drive voltage during switching. At 300 pH, turn-on losses increase by 15% and turn-off losses by 10%. At 500 pH, partial turn-off during switching occurs, increasing losses by 25–30% [88]. In [93], the common-source inductance mismatch exceeding 1.5 nH between paralleled devices created sustained oscillations at 80–120 MHz. Keeping the common-source inductance mismatch below 0.8 nH suppressed these oscillations.

These results emphasize that minimizing common-source inductance and high-frequency power loop inductance through optimized layout techniques and reduced loop areas is critical for maintaining a high-efficiency and fast-switching performance in high-frequency GaN half-bridge converters. These findings emphasize that minimizing and matching common-source inductance and power loop inductance are essential for efficient and stable parallel operation.

4.2. Parallel GaN Module Design and Configuration Strategies

The different parallel GaN device layout designs and structures are reported in [97,98,101,102,103,104,105,106,107] considering the parasitic, thermal, and mechanical aspects for high-current half-bridge applications. The comparative analysis reported in

Table 7. Comparative review of parallel GaN device structures for high-current half-bridge power modules.

Ref./Year	Work/Focus	Voltage/Current Class	Parallel Devices/Structure	Parasitic/Switching Focus	Thermal/Mechanical Aspects	Key Contributions
[73], 2014	Low-voltage GaN power module	480 W/ 40 A	Four parallel, discrete GaN devices in buck converter	Parasitic-aware packaging, 0.4 nH	Improved heat spreading	Distributed high-frequency loops, lateral–vertical power loop
[101], 2014	Design and characterization of 270 V, 56 A GaN power module	270 V/56 A	Three GaN chips (six AlGaN HEMT cells per chip); wire-bonded in parallel	Dynamic current sharing and Id-Vds characteristics for parallel devices	Thermal performance evaluated for multiple-chip package	Demonstrated ability to parallel GaN HEMT dies with verified current sharing and high-current capability
[102], 2015	Development of high-frequency GaN-based half-bridge power module	650 V/150 A	Five GaN HEMTs (GS66508B) on DBC; multi-die integration	Poor power loop inductance (5.6 nH)	Junction-to-case thermal resistance modeling	Validated high-frequency GaN module performance
[52], 2017	Paralleling behavior of E-mode GaN HEMTs	650 V/240 A	Eight GaN HEMT (4 HS + 4 LS) (GS66516T) half bridge	Power loop and gate loop parasitic under high dv/dt and di/dt	Temperature-dependent RDS(ON) behavior	Analytical switching model and experimental validation of high-current GaN paralleling
[97], 2017	High-density GaN HEMT power module design and validation	650 V/120 A	Four GaN HEMTs (GS66508B), single-layer IMS	Impact of circuit parasitic on high-power, high-density operation	FEM-based thermal analysis; IMS substrate thermal behavior	Proposes an IMS-based GaN power module with FEM-validated thermal and electrical performance
[103], 2018	Loss balancing in paralleled GaN HEMTs	650 V/240 A module	Four GaN HEMTs (GS66516B) in power module; metal-core PCB	Analytical modeling of switching and conduction loss imbalance	Junction temperature monitoring, MCPCB-based module	Proves stable parallel operation and inherent auto-balancing of losses in GaN HEMTs without device preselection
[104], 2019	Analysis of commercial and custom low-voltage, high-current GaN modules	100 V/360 A	(Two GaN HEMTs (GS61008T)) ×2 on DBC, six-layer FR4 PCB	High-frequency parasitic modeling; Vds overshoot at hard turn-off; layout sensitivity analyzed	Lower power loop inductance (<1 nH)	Demonstrated design recommendations and custom 100 V/360 A GaN module capable of hard switching at die current ratings without failure
[40], 2019	Design and analysis of paralleled low-voltage GaN HEMTs	Low-voltage (≤100 V), 300 W converter	Two GaN HEMTs in parallel	Effect of parasitic inductances in driver and power loops; unbalanced branch parameters evaluated using ANSYS Q3D	Thermal effects due to parasitic mismatch in parallel branches	PCB layout and driver design guidelines validated on 300 W isolated DC-DC converter with proper parallel operation
[66], 2025	Design of compact 100 V/360 A GaN power module for high-current traction applications	100 V/360 A	Four GaN HEMTs (GS61008P), single-layer IMS and two-layer FR4 PCB	Ensures balanced current sharing, robust gate drive, and reliable switching under high di/dt and dv/dt	Excellent thermal dissipation and minimal mechanical stress; meets industrial requirements	Proposed compact GaN module with high-power capability, reliable switching, and validated performance in DPT, buck converter, and three-phase inverter tests
[105], 2020	Reducing parasitic inductance in DBC-based conventional housing GaN modules	650 V/1200 A	Eight GaN HEMTs on DBC, double-layer FR4 PCB	Techniques to minimize stray inductance; FEM and experimental evaluation	Conventional DBC housing; maintains excellent thermal performance and low cost	Novel housing design enabling reliable, efficient switching in conventional GaN modules without added cost
[106], 2021	GaN-based high-power-density chip-on-chip module	650 V/120 A	Four GaN HEMTs (GS66508T) on DBC, chip-on-chip configuration	Ultra-low parasitic inductance (2.1 nH) to improve switching performance	Considerations to reduce thermal stress and optimize mechanical integration in dense modules	High-power-density GaN module with low parasitic inductance and enhanced switching
[107], 2021	Top-cooled GaN power module with integrated gate drive	650 V/150 A	Two GaN HEMTs on DBC, top-mounted PCB	Reduced parasitic inductance in gate drive and power loops (1.54 nH) to limit voltage overshoot	DBC with ceramic insulation for heat dissipation	Compact high-current GaN module with integrated gate drive, low overshoot, and excellent thermal performance
[98], 2022	Design of compact 650 V GaN half-bridge power module	650 V/720 A	12× GaN HEMTs (GS66516T), six-layer FR4 PCB	Power loop stray inductance reduced to 0.42 nH; small voltage overshoot (18.5%)	Liquid-cooled from both sides; junction-to-coolant thermal resistance < 100 K/kW	Compact high-power GaN half-bridge module with low parasitic inductance, efficient switching, and excellent thermal performance

describes parallel GaN device structures and packaging approaches for high-current half-bridge applications. The table systematically summarizes the voltage and current classes, paralleling strategies, parasitic mitigation techniques, and thermal or mechanical design considerations adopted in prior works. This comparison highlights the evolution from discrete PCB-based paralleling to highly integrated, low-inductance module solutions while also revealing persistent limitations related to current-sharing accuracy, thermal coupling, and scalability. The insights derived from Table 7 provide a structured foundation for identifying existing research gaps and motivate the need for improved paralleling and packaging methodologies capable of meeting the stringent electrical and thermal demands of next-generation GaN power converters.

Traditional wire-bonded interconnects introduce excessive parasitic inductance for parallel GaN operation [93]. Laminated busbar structures or closely spaced parallel power planes in the PCB stackup provide minimal loop areas essential for high-di/dt operation [94]. Multiple low-inductance ceramic capacitors in parallel, placed in close proximity to switching devices, provide necessary high-frequency decoupling for nanosecond-scale current transitions. Interconnections must maintain overall symmetry to prevent the introduction of new imbalances.

In [73], converter-level studies verified effective current sharing and high efficiencies above 96% using optimized PCB layouts for parallel GaN operation (four parallel half bridges) at high switching frequencies in low-voltage applications (48 V to 12 V, 40 A). A 270 V, 56 A GaN power module based on three AlN substrates with parallel-connected GaN HEMT chips is presented in [101] to enhance current capability. Comprehensive DC, pulsed, and thermal characterizations were performed to analyze the scaling of the static parameters and dynamic current sharing under various operating conditions. Experimental results confirm the reliable paralleling of nine GaN HEMT dies with effective current sharing during switching, demonstrating suitability for high-current applications. A high-current 650 V GaN-based power module is presented in [102] for high-frequency, high-power conversion applications. The module is analyzed using combined thermal and electrical modeling to estimate the junction-to-case thermal resistance and power-loop parasitics, supported by temperature-dependent on-state and leakage measurements. The authors of [52] investigate the paralleling of enhancement-mode GaN HEMTs for 10–100 kW class power systems to increase the current capability and reduce conduction losses. An analytical switching model was developed to study the impact of device characteristics and circuit parasitics, along with corresponding gate-driver and layout design considerations. The proposed approach was experimentally validated using a 240 A/400 V half-bridge configuration, with double-pulse test results confirming reliable parallel operation.

In [97], a high-density, high-efficiency GaN HEMT power module based on insulated metal substrate (IMS) technology is presented for 3 kW and higher-power applications. The design addresses critical thermal and parasitic effects in compact GaN systems and was evaluated using FEM-based thermal–electrical simulations. Experimental results closely match the simulations, confirming the effectiveness of the proposed module design. The authors of [103] analyze the parallel operation of GaN HEMTs in high-power applications, focusing on loss imbalance and thermal reliability. An analytical loss model demonstrates the inherent auto-balancing of conduction and switching losses due to the negative temperature coefficient of g_m, enabling stable operation without device preselection. Experimental validation using 240 A/650 V metal-core PCB modules confirmed balanced loss distribution through junction temperature measurements. A detailed electrical and parasitic analysis of a commercial 100 V, 270 A GaN module is conducted in [104], highlighting its vulnerability to severe V_ds overshoot during hard turn-off due to fast switching and package parasitics. Simulation and double-pulse testing revealed premature failure at reduced current levels, motivating layout-focused design recommendations. A custom 100 V, 360 A GaN module was subsequently developed and experimentally validated, demonstrating reliable hard switching beyond 300 A. The authors of [33] report the design and characterization of a 270 V, 56 A GaN power module using three AlN substrates with parallel-connected GaN HEMT chips. Comprehensive DC, pulsed, and thermal measurements were performed to study the scaling of the static parameters and dynamic current sharing under various operating conditions. Experimental results demonstrate the reliable parallel operation of nine GaN HEMT dies, confirming the enhanced current capability during dynamic switching.

The parasitic reduction techniques for high-power GaN HEMTs using conventional DBC housing-type packages are demonstrated in [105]. FEM simulations and experimental evaluations compared multiple approaches to minimize stray inductance while retaining the cost and thermal advantages of conventional packaging. A novel housing design is proposed and validated in the paper, achieving reliable and efficient switching without additional cost. The authors of [106] propose a 650 V, 120 A half-bridge GaN power module based on a chip-on-chip architecture with integrated distributed decoupling capacitors. The close integration significantly reduced the power loop parasitic inductance to 2.1 nH and improved the dynamic current sharing among parallel devices. The comparative analysis reported in

Table 8. Comparative review of parallel GaN power modules considering parasitic inductances and operating switching frequency.

Reference	Configuration/Module Type	Voltage	Current	Switching Frequency	Lloop (nH)	Lcsi (nH)	Lg (nH)	Current Sharing Strategy	Key Contribution
[40]	Discrete parallel GaN devices	650 V	30–60 A	100–500 kHz	~5–10	~0.5–1	~1–2	Gate driver balancing	Shows strong influence of driver symmetry on current sharing
[51]	Parallel GaN half-bridge	48–100 V	20–40 A	100–500 kHz	~5–10	~0.5–1.5	~1–3	Symmetrical PCB layout	Demonstrates stable current sharing using optimized layout symmetry
[52]	High-power GaN module	400–650 V	>100 A	50–200 kHz	~8–15	~1–2	~2–4	Driver synchronization	Demonstrates scalability of GaN devices to high-power systems
[56]	Parallel GaN bridge leg	200–400 V	20–50 A	100–300 kHz	~6–12	~0.8–1.5	~2–3	Symmetric routing	Enables diode-free bridge operation with improved efficiency
[70]	PCB butterfly layout for parallel GaN	400–650 V	50–100 A	>200 kHz	~3–6	~0.3–0.8	~1–2	Butterfly layout	Significantly reduces loop inductance and improves switching balance
[71]	9 parallel GaN dies	270 V	56 A	100–500 kHz	5–10	~0.2–0.5	~2	Passive current sharing	Parallel current scaling validation
[87]	Review of GaN modules	Up to 1200 V	>200 A	>1 MHz	~3–10	~0.3–1.5	~1–3	Various techniques	Comprehensive overview of packaging, layout, and paralleling challenges
[91]	Cascode GaN parallel devices	650 V	40–80 A	100–300 kHz	~8–12	~1–2	~2–4	Device matching	Experimental validation of current balancing and switching loss distribution
[92]	Parallel GaN half-bridge	650 V	60–120 A	100–200 kHz	~7–12	~1–2	~2–4	Passive current sharing	Demonstrates high-current operation using paralleled GaN devices
[95]	GaN half-bridge layout	400–650 V	30–80 A	100–500 kHz	~4–8	~0.5–1	~1–3	Optimized power loop	Provides layout guidelines for minimizing parasitic inductance
[102]	High-current GaN module	650 V	150 A	100–300 kHz	~3–5	~0.3–0.8	~1–2	Integrated module layout	Demonstrates low-inductance high-current GaN power module
[106]	Integrated GaN module	650 V	>100 A	100–400 kHz	~2–4	~0.2–0.5	~1	Integrated packaging	Achieves ultra-low parasitic inductance in multichip modules

describes parallel GaN devices power module rating with operating switching frequency, parasitic inductances and current sharing strategy.

Double-sided cooling further enhanced the thermal performance of the module. In [107], a compact 650 V, 150 A GaN power module is presented using a DBC-based thermal pad and integrated PCB-mounted gate drive and decoupling components. The high level of integration significantly reduces gate and power loop parasitic inductance, resulting in suppressed voltage overshoot and excellent thermal impedance. Double-pulse and thermal tests validate reliable high-current operation, demonstrating suitability for high-power EV chargers and motor drive inverters. In [98], a compact 650 V, 2.1 mΩ GaN half-bridge power module is designed to address packaging challenges associated with the lateral structure of GaN HEMTs. A symmetric PCB-based layout with double-sided liquid cooling reduced the power loop inductance to 0.42 nH and enabled high-current operation with low-voltage overshoot and switching losses. Experimental results confirm an excellent thermal performance, with a junction-to-coolant thermal resistance below 100 K/kW. Moreover, a compact 100 V, 360 A GaN power module is presented in [66] targeting high-current traction and inverter applications. The design addresses challenges in paralleling GaN HEMTs by ensuring balanced current sharing, robust gate driving, and effective thermal and mechanical management using IMS/DBC packaging. Experimental validation through double-pulse testing, a 3-kW buck converter, and a 5 kW three-phase inverter confirms the module’s electrical and thermal performance.

5. Thermal Management Strategies

5.1. Multi-Scale Thermal Management Approach

To manage heat effectively, several approaches have been discussed in the literature. An overall hierarchical approach has been considered that presents heat transfer at different levels, from the semiconductor die to the system-level heat exchanger [23,30]. The packaging of the devices with bottom-side cooling, top-side cooling, and double-sided cooling is provided by the manufacturers [108,109]. Bottom-side cooling requires thermal vias to dissipate heat and a sophisticated balance between the electrical layout design and thermal vias. In addition, thermal vias increase the overall cost of the system, with the higher manufacturing cost of PCB manufacturing with hundreds of thermal vias [89]. The design of packages with top-side cooling with a trade-off between the thermal and electrical performances can be considered [89].

5.1.1. Die-Level Thermal Interfaces and Spacing Optimization

The thermal path starts at the GaN die, where the overall thermal resistance is greatly influenced by the substrate selection, the usage of thermal interface materials, and the device spacing [110,111,112,113]. In comparison to traditional solder alloys (1–3 W/mK) and thermal epoxies (1–5 W/mK), recent developments in the technology of sintered silver nano-paste have shown its higher thermal conductivity. In order to improve the heat dissipation and reduce the thermal coupling between devices coupled in parallel, proper chip spacing is crucial [114]. Because GaN devices are so small and contemporary converters have very strict power density standards, it is frequently not viable to install larger heatsinks. In order to balance thermal crosstalk, parasitic inductance, and connection restrictions, intelligent thermal management through die location and spacing is crucial [114,115].

5.1.2. Substrate-Level Thermal Spreading

Effective lateral heat dispersion is essential at the substrate level to prevent isolated hot patches and preserve uniform junction temperatures between parallel devices [85,116]. For parallel GaN systems that work at high current densities, regular FR4 substrates with thermal conductivities of about 0.3 W/mK are not good enough [117]. With thermal conductivities ranging from 170 to 200 W/mK, advanced substrates such as Direct Bonded Copper (DBC) on aluminum nitride (AlN) are excellent for dispersing heat and separating electricity [118]. Insulated metal substrates (IMSs) with thermally enhanced dielectric layers (1–3 W/mK) are a good middle ground for applications where cost is the most important factor. Thermal performance can be balanced using IMSs consisting of thermally enhanced dielectric layers with additional benefits of intuitive steps in manufacturing [110,114,117]. A lot of novel research is being conducted on thermal management by embedding some appropriate cooling materials directly into silicon and silicon carbide substrates, such as microfluidic cooling channels. The microfluidic cooling method efficiently helps in cooling the chip or substrate directly with the dedicated liquid, which significantly decreases the thermal resistance and, in turn, helps with more effective heat dissipation.

5.2. Advanced Cooling Architectures for Parallel Systems

5.2.1. Symmetrical Thermal Design

To have a stable and reliable operation through parallel-connected devices, the thermal system needs to be designed with good symmetry. When each device follows a similar heat dissipation path, junction temperatures tend to remain more uniform, which, in turn, supports balanced current sharing. Reducing temperature differences between devices significantly lowers the risk of thermal runaway, a harmful feedback process in which localized heating leads to increased current flow and further temperature rise. In conclusion, improved temperature stability can be obtained by using a symmetrical thermal design for the whole system [110,111,117,119].

The following elements must be carefully considered in order to have a good symmetrical thermal design:

• Geometrical symmetry in die placement relative to cooling interfaces;
• Uniform application of thermal interface materials;
• Identical mounting pressure distribution;
• Balanced fluid flow distribution in liquid-cooled systems.

Even minor asymmetries in thermal impedance can initiate thermal runaway, particularly under high-load conditions where temperature gradients are magnified by strong electrothermal coupling in GaN devices [120].

5.2.2. Cooling Technology Selection

The choice of cooling technology depends on the power density needs of the system, the packaging limits, and the duty cycles [120,121]. The cooling technologies are mentioned below:

• Forced-air cooling: Forced-air cooling is still possible for power densities below 1 W/mm², as long as you use optimized finned heatsinks with thermal resistances of 1.0–3.0 °C/W. Advanced designs use vapor chambers to spread heat better and keep temperatures the same across many devices [74,110].
• Single-Phase Liquid Cooling: With cold plates that have thermal resistances of 0.3–0.8 °C/W, single-phase liquid cooling can handle power densities of up to 3 W/mm². Micro-channel and pin-fin designs find the best balance between thermal performance and pressure drop. Flow distribution networks that are carefully designed make sure that all paralleled devices get the same amount of cooling [78,117].
• Two-Phase Cooling Systems: Two-phase cooling systems, such as vapor chambers and advanced heat pipes, have thermal conductivities that are orders of magnitude higher than copper and can spread heat very well. These systems are very useful for keeping the temperature the same across a lot of parallel devices [92,119].
• Double-Sided Cooling: Double-sided cooling is the best way to cool ultra-high-power-density applications (>5 W/mm²) because it lowers the thermal resistance between the junction and coolant to 0.1–0.3 °C/W by providing cooling paths on both sides of the power module. This method usually needs special packaging, but it can double the amount of heat that can be removed compared to normal single-sided cooling [99,117].

  Table 9. Performance comparison of different cooling technologies.

  Technology	Thermal Resistance	Power Density	Application Scope
  Advanced Air Cooling	0.8–2.0 °C/W	~1.5 W/mm2	Cost-sensitive applications
  Single-Phase Liquid Cooling	0.3–0.8 °C/W	~3 W/mm2	High-performance systems
  Double-Sided Cooling	0.1–0.3 °C/W	>5 W/mm2	Ultra-high-density designs

  presents how the different cooling technologies compare in terms of their performances.

5.3. Electrothermal Coupling Effects in Paralleled GaN Transistors

The current-sharing behavior of parallel-connected GaN HEMTs is strongly influenced by self-heating and mutual thermal coupling through coupled electrothermal interactions. When one device conducts slightly higher current than the others, it dissipates greater conduction and switching losses, leading to a faster rise in the junction temperature. In enhancement-mode GaN devices, the R_DS(on) increases with temperature, which provides a stabilizing mechanism for static current sharing, since the hotter device experiences a higher conduction resistance and its current is partially redistributed to adjacent devices [16,21].

However, the V_TH of GaN HEMTs decreases with increasing temperature, introducing a potentially destabilizing effect [16,18]. A device with a slightly lower initial V_TH turns on more strongly and carries higher current. The resulting higher losses cause a faster temperature rise, which further reduces its V_TH. This forms a positive electrothermal feedback loop, as illustrated in Figure 15, and may aggravate current imbalance if electrical and thermal symmetry are not ensured. Experimental investigations on paralleled GaN devices have reported that parameter mismatch combined with temperature rise can lead to current crowding and unequal loss distribution, particularly under high-current operation [51,87,95].

In multichip GaN power modules, mutual thermal coupling further modifies this behavior. Since closely spaced dies share a common substrate and heat-spreading path, heat generated in one transistor increases the temperature of neighboring devices. Strong and symmetrical thermal coupling can reduce temperature gradients and improve steady-state current sharing, whereas asymmetric layout or non-uniform cooling may create localized hot spots that reinforce imbalance [85,92,113]. Moreover, during high-speed switching, parasitic inductance mismatch and layout asymmetry can cause transient current spikes that are not immediately corrected by thermal effects due to slower thermal time constants [88,91]. Instability phenomena in GaN half-bridge configurations have also been linked to the interaction of device parameters and parasitic elements [121].

Therefore, although the positive temperature coefficient of R_DS(on) supports static current stabilization, the negative temperature coefficient of V_TH can introduce a reinforcing electrothermal loop. The reliable parallel operation of GaN transistors thus requires careful electrical symmetry and thermal uniformity to ensure that the stabilizing resistance effect dominates over the destabilizing threshold voltage-driven mechanism.

5.4. Combined Effects of Parasitic Inductances and Thermal Resistances on Drain Current

The maximum continuous drain current in GaN transistors is influenced by both electrical parasitics (through their effect on switching losses) and thermal resistance (through self-heating and the temperature dependence of R_DS(on)), as shown in Figure 16 [2,5,8,60,85,95]. This section presents a quantitative analysis of these combined effects based on device physics and published characterization data.

5.4.1. Thermal Resistance Effect on Current Capability

The relationship between thermal resistance and current capability can be derived from the temperature-dependent characteristics of GaN HEMTs. In [85], the authors demonstrate the importance of junction temperature control in paralleled GaN FETs, showing that temperature differences as small as 10 °C can create current imbalances of 3–5%. Using the typical temperature coefficient of R_DS(on) for 650 V GaN devices (approximately +0.5%/°C [19,22]), Figure 17 illustrates how thermal resistance affects maximum continuous current for a 30 A rated device operating at 100 kHz with a 50% duty cycle.

5.4.2. Parasitic Inductance Effect on Current Capability

Parasitic inductance does not directly limit the DC current but affects the current capability through increased switching losses, which add to the thermal load. In [2,5], the authors developed analytical models relating parasitic inductance to switching losses in GaN HEMTs. Using their framework, Figure 18 illustrates the calculated effect of loop inductance on the thermal headroom for the same 650 V/30 A device operating at 20 A and 100 kHz.

6. Future Research Perspectives and Conclusions

6.1. Future Research Directions

6.1.1. Thermal Modeling: Multi-Physics Simulation and Electrothermal Modeling

The extensive electrothermal analysis of GaN power modules is frequently performed using sophisticated multiphysics simulation tools such as ANSYS Icepak. Both normal and fault conditions can be accurately predicted by these techniques in terms of temperature changes [74]. The simulations based on these tools are necessary in the initial stage of the thermal design of systems, which help to identify the areas of instability and thermal stress, if there are any possibilities. These early simulation-based analyses helped to make cheaper hardware revisions through trial and error, preceding actual physical system design [78]. To build a complete and reliable performance database, a lot of parametric tests are needed to look at things, like where to put components, what kind of substrate to use, and how to cool the system. This empirical simulation data gives us a quantitative basis for making smart design choices and obtaining a methodically optimized thermal architecture [115].

6.1.2. AI-Driven Thermal Optimization

Artificial intelligence (AI) has emerged as a potent new method of solving this issue. An increasing amount of research is employing AI to create intelligent design frameworks that facilitate the identification of optimal heat management strategies [69,114,122]. Machine learning models trained on large electrothermal datasets can accurately connect layout features and material properties to understand how temperature spreads and how thermal gradients behave. When combined with optimization methods like Genetic Algorithms or Particle Swarm Optimization, these AI-assisted frameworks make it easy to find module configurations that lower peak junction temperatures and improve thermal uniformity among GaN devices that are connected in parallel [108,123].

This method makes it easier to efficiently explore the coupled electrical–thermal design space, which shows the best solutions that are hard to find with traditional trial-and-error methods [123]. Figure 19 shows a diagram of the layout of the GaN module that uses AI-based thermal optimization. Because GaN devices are so small, it is often not possible to add larger heatsinks, which makes it more difficult to manage heat. So, to improve heat dissipation and reduce thermal interference in the parallel device structure, it is important to optimize the space between GaN chips. Further, thermal cycle characterization is essential to validate the optimized layout and thermal management strategy [99].

6.1.3. Parallel GaN Power Module Development

GaN-based power electronic converter system development and its practical design face critical challenges, such as fabrication costs and thermal performance, which limits the system rating and operating switching frequency [82,83,84,86,124]. Furthermore, overall system power density, reliability, and efficiency are crucial aspects for the real-time operation in specific applications [125,126,127,128,129,130]. To develop GaN-based systems for high-power high-current applications, an ideal solution for reducing layout-related mismatches and thermal performance issues is to integrate multiple GaN devices on a single power module with appropriate spacing between the chips considering AI-based multi objective optimizations [114,122,123]. Considering this, early-stage finite-element analysis (FEA) simulations and/or experimental measurement techniques are required to identify the parasitic impedances of the layout design enabling targeted reduction and balancing the parallel system [108,123].

A general development flow of a GaN-based power converter is shown in Figure 20, where intelligent PCB layout techniques and AI-assisted thermal management are proposed as feasible possibilities for further research. The system compactness, efficiency, and reliability can be further improved by continual improvements in advanced packaging, especially technologies that incorporate gate drivers, sensors, and thermal management features. This approach has the potential to greatly streamline and enhance the design process and can aid in automated layout optimization.

6.1.4. Advanced Gate Driving Architectures

Independent source returns for the gate drive circuit are crucial in parallel GaN configurations [72]. Kelvin connections provide a low common source inductance; however, it had an additional parasitic inductance corresponding to an additional pad on the package for the Kelvin connection. This provides the path for gate return current that completely bypasses the high-power source current, preventing modulation of the gate-source voltage by rapidly changing power loop currents [131].

Multi-Channel Synchronized Drive Topology

Development of individual gate driving units are adopted rather than the common gate driving for the power module circuit board with paralleled GaN devices to avoid the common source configuration to minimize the gate ringing and parasitic inductance in gate loop layout of the gate driving unit [93]. Dedicated multi-channel gate driver ICs provide isolated, matched output channels for each parallel device, ensuring propagation delay mismatches below 1 ns [132]. However, a tight matching of the gate driving unit should be enforced to avoid unwanted mismatched gate signals. These integrated solutions incorporate adaptive dead-time control with resolution < 2 ns, preventing cross-conduction while minimizing body diode conduction losses [113]. The implementation employs Kelvin source connections for each device, creating independent gate return paths that bypass power loop inductance.

Active Gate Control Techniques

Active gate driving incorporates real-time monitoring and adaptive control to compensate for parameter variations and layout asymmetries [133]. Active gate voltage regulation dynamically adjusts V_gs based on temperature and load conditions, maintaining optimal switching characteristics while preventing gate overvoltage stress [134]. Dynamic timing control circuits continuously calibrate turn-on and turn-off delays using current-sense or voltage-feedback mechanisms, correcting for device-to-device variations. Active gate shaping techniques employ programmable gate resistance or multi-level gate driving to control di/dt and dv/dt, achieving an optimal trade-off between switching losses, device stress, and electromagnetic interference [134].

To effectively operate GaN power transistors, it is essential to meticulously evaluate a convergence of factors, including electrical parameters, dynamic switching characteristics, and hardware design, as depicted in Figure 21 [135,136]. To keep devices reliable, it is important to follow the gate-to-source voltage ratings very closely, especially the negative gate threshold V_TH, to avoid damage. One of the biggest problems with dynamic performance is dealing with high dv/dt transients to stop unwanted shoot-through currents, which can cause big losses or even the failure of the device [131,137].

6.2. Conclusions

This article presents a comprehensive review that systematically analyzes the key challenges and design imperatives for paralleling GaN HEMTs in high-power applications. This paper shows that parallelizing GaN HEMTs is an important and growing way to increase power without losing the speed and efficiency that come with GaN technology. To be successful, we need to follow clear design rules: careful layout symmetry, with parasitic inductance imbalances kept below 1 nH, and uniform thermal management using advanced cooling for power densities > 10 kW/L. The reliable parallel operation cannot be achieved by considering improvements in electrical, thermal, or control aspects independently (Figure 22). Rather, it needs a comprehensive, board-level collaborative design approach that simultaneously addresses the gate drive control, temperature control, and circuit layout because of their significant interdependence. Carefully balanced design choices are required instead of single-parameter optimization due to the complex trade-offs between various domains, such as the dispute between an efficient heat dissipation system and a compact, low-inductance layout.

This study shows that in parallel GaN systems, the dynamic current imbalance is the main deciding factor in the perfect current sharing among GaN devices rather than static current imbalances. It is possible to manage static current sharing well by matching devices and using a symmetrical layout. However, dynamic sharing during fast-switching transitions is still very difficult because small parasitic asymmetries become more pronounced. This shows how important it is to use the integrated approach that combines layout optimization and thermal management, which is reviewed comprehensively in this paper.

Also, parallel GaN systems do not scale well beyond 4–6 devices in a single parallel string. This is mostly because of the cumulative effect of parasitic elements and the growing difficulty of keeping all the devices in synchronization. For higher-power needs, multi-phase architectures with multiple parallel strings may work better than single strings with many devices.

Furthermore, this review identifies fundamental scalability limits for monolithic parallel strings, with stable operation becoming increasingly challenging beyond four to six devices due to cumulative parasitic effects and synchronization difficulties. For applications requiring higher power, multi-phase converter architectures employing multiple, smaller parallel strings present a more robust and scalable pathway than extending a single string.

In general, the idea of paralleling GaN HEMTs has gone from being a research idea to a useful and necessary method for modern power electronics. Future progress will depend on close cooperation between device design, packaging, control methods, and thermal engineering. This will lead to more improvements in efficiency, power density, and long-term system reliability.