Interleaved High-Gain DC-DC Converters with Low Input Ripple and Voltage Stress for Passenger Fuel Cell Vehicles

Abstract

Passenger fuel cell vehicles (FCVs) require high-gain DC/DC converters to achieve voltage matching between the low-power fuel cell (FC) stack (50–200 V) and the vehicle DC bus (400–800 V). To address the challenges in existing step-up DC/DC converters in relation to balancing the requirements of high voltage gain, wide input voltage range, low input current ripple and voltage stress, the common ground of input–output, and high efficiency in passenger FCV applications, this paper proposes three types of high-gain DC/DC converters based on an interleaved structure, incorporating quadratic Boost, quasi-Z source, and switched-inductor impedance networks. These designs effectively balance the scenario requirements of passenger FCVs. Meanwhile, taking one of the proposed converters (Interleaved-Quadratic Boost; I-QB) as an example, its steady-state performance such as voltage gain is analyzed and compared in detail with existing voltage step-up DC/DC converters. Furthermore, a scaled-down SiC-based experimental platform is constructed. Steady-state experiments validate the converter’s maximum voltage step-up capability of ten times, wide input voltage range of 30–80 V, input current ripple of less than 0.3 A, and low voltage stress on devices (≤U_o/2), thereby confirming the feasibility of these converters and the correctness of the performance analysis. The dynamic experimental results indicated that under input voltage step changes of 50–80 V and 100–50% load step changes, the I-QB converter exhibits a minor voltage overshoot with settling time under 200 ms. The prototype achieves a peak efficiency of 94.2%, confirming these converters’ suitability for passenger FCV powertrains.

1. Introduction

The energy crisis and environmental issues have compelled the rapid development of the new energy vehicle industry. Mainstream new energy vehicles currently on the market primarily include electric vehicles (EVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), range-extended electric vehicles (RE-EVs), and fuel cell vehicles (FCVs) [1]. Among these, FCVs are gaining increasing user favor due to their fast-refueling capability, the minimal impact of temperature on their driving range, and water being their only by-product. A typical structure of the FCV powertrain is shown in Figure 1; due to the slow dynamic response of FCs, they are used to deliver average power. The power battery is directly connected to the vehicle’s DC bus and is responsible for delivering and recovering instantaneous power [2]. FCVs come in two forms: commercial vehicles and passenger vehicles. Due to sufficient installation space, commercial FCVs are equipped with high-power (150–300 kW) fuel cell (FC) stacks, mainly used for mountainous terrain, heavy loads, and long-distance driving conditions. Conversely, passenger FCVs have limited installation space and are equipped with low-power FC engines (below 50 kW), serving as a supplement to EVs and primarily being used for flat terrain, light loads, and short-distance driving conditions. FCs typically operate in a constant-current output mode, where the stack current is related to factors such as the fuel supply rate, pressure, temperature, and humidity, etc. [3]. The rated power of an FC determines its output voltage level. Therefore, in passenger FCVs, a high-gain step-up converter is required to achieve voltage matching between the low-power FC stack and the vehicle’s DC bus (400–800 V).

The application scenario of passenger FCVs imposes the following “three requirements” on the DC/DC converter: (1) a high voltage gain, preferably achieved at a relatively low duty cycle (0.6–0.7) to enable precise output voltage control under a flat d-M (duty cycle–voltage gain) curve [4]; (2) a wide input voltage range, as the FC exhibits “soft” output attribute, necessitating a broad voltage regulation range from the DC/DC converter [5]; (3) a low input current ripple—over prolonged operation periods, the performance of FC gradually deteriorates due to intricate driving conditions and component ageing (high input current ripple exacerbates this performance degradation), requiring the input current ripple of the directly connected DC/DC converter to be as low as possible [6,7]. As a power conversion device, the following “three requirements” should also be considered. (1) Low voltage stress, as high stress increases the risk of device failure, reduces overall vehicle reliability, and raises converter cost and volume [8]. (2) Common ground of input–output; considering vehicle driving safety, EMI should be minimized, requiring the DC/DC converter to have a common ground attribute of input–output. (3) High efficiency, maintaining efficient operation across the full load range to improve vehicle’s overall energy utilization and driving range.

Considering factors such as efficiency, vehicle space, and stress, non-isolated DC/DC converters are typically utilized in FCVs. The theoretical high gain of a conventional non-isolated Boost is difficult to achieve in practice, due to limitations from parasitic parameters, making it unsuitable for the actual requirements of FCV powertrains [9]. To address these issues, researchers have designed various high-gain DC/DC converters. Initially, the goal was simply to enhance the voltage gain of DC/DC converters. Ref. [9] combined quasi-Z sources with switched capacitors, Ref. [10] cascaded Z sources and switched capacitors, while Ref. [11] cascaded switched inductors with voltage multipliers. However, these topologies lack a common ground attribute. To avoid extra EMI, it is necessary to enhance the voltage gain while simultaneously addressing the issue of common ground of input–output. Ref. [5] cascaded a half Z source (IWJ structure [12]) with voltage multipliers, Ref. [13] mixed a voltage lifting circuit with a quadratic Boost converter, and Ref. [14] combined a Z source with a voltage multiplier. Although the issue of input–output common ground was resolved, these topologies exhibited pulsating input current. Furthermore, to address the issue of pulsating input current while enhancing the voltage gain, Ref. [15] cascaded the interleaved structure with the switched capacitor, and Ref. [16] cascaded Boost and a clamped capacitor with a three-level structure. In Refs. [17,18], the Boost converter was combined with a modified voltage multiplier, while in Refs. [19,20], the Cuk converter was integrated with a quadratic Boost or Boost converter, achieving high voltage gain under a continuous input current. However, these topologies, in turn, introduced the previous issue of the non-common ground of input–output. So, can the voltage gain be enhanced while ensuring both conditions—continuous input current and the common ground of input–output? Ref. [21] employed a hybrid structure interleaving with a voltage multiplier. However, the voltage stresses of the capacitors were large. Finally, to address the issue of high voltage stress, in Ref. [22], the quasi-Z source structure was cascaded with the three-level structure, which improved the voltage gain with the premise of ensuring the continuous input current, common ground, and low device voltage stress, but the duty cycle range was 0.5–0.75, which increased the difficulty in controller design. The resolution of existing issues is frequently accompanied by the emergence of new challenges. Despite significant efforts to enhance voltage gain through various approaches, existing high voltage step-up converters for passenger FCVs struggle to simultaneously achieve continuous input current, common grounding, and low voltage stress. This persistent trade-off among key performance indicators—ranging from pulsating input current and non-common ground configuration to high device voltage stress and limited duty cycle ranges—reveals a critical research gap in developing a DC/DC converter that holistically satisfies all practical FCV powertrain requirements.

Therefore, this study is dedicated to designing DC/DC converters that address the current research gap. Based on the author’s previous research [8], the quadratic Boost, quasi-Z source, and switched-inductor impedance networks demonstrate outstanding voltage step-up capabilities, continuous input current, and common ground attributes, effectively balancing the requirements of passenger FCVs. Considering that the interleaved structure can achieve ripple elimination, this paper rationally integrates these impedance networks to construct three high-gain DC/DC converters: the Interleaved-Quadratic Boost (I-QB), the Interleaved-Quasi-Z source (I-QZS), and the Interleaved-Switched-Inductor (I-SI). Detailed analysis, modeling, and experimental verification are performed using the I-QB converter as an example. The results demonstrate that the I-QB converter has the following advantages:

Extremely high voltage gain under a flat d-M curve;

Practically achievable wide input voltage range;

Low input current ripple with inductor currents cancellation;

Low voltage stress;

Common ground of input–output;

Satisfactory efficiency.

In Section 2, three types of high-voltage-gain DC/DC converters are given. The steady-state characteristics of the I-QB converter are analyzed in Section 3. Section 4 provides the comparisons. In Section 5, the experimental validation is provided. Section 6 discusses the conclusions.

2. The Proposed Topologies

The three novel topologies are shown in Figure 2. Figure 2a depicts the I-QB topology, Figure 2b shows the I-QZS topology, and Figure 2c illustrates the I-SI topology.

3. Analysis of the I-QB Topology

3.1. Topology Selection

Due to space constraints, this paper will select one topology for analysis and verification. Introducing a quasi-Z source impedance network would introduce (1-2d) in the denominator of the converter’s voltage gain function. This would result in an extremely steep d-M curve. While this avoids the occurrence of the limit duty cycle, even minor changes in the duty cycle would cause significant fluctuations in the output voltage. When system disturbances require adjusting the duty cycle, unacceptable output voltage overshoot could easily occur, posing challenges for controller design. Moreover, the I-SI converter requires significantly more components than the I-QB and I-QZS converters. Although the I-SI converter offers a higher voltage gain, the excessive component count makes it challenging to improve the efficiency and power density. After weighing the trade-offs, this paper selects the I-QB topology as an example to demonstrate the feasibility and effectiveness of the proposed topologies. The analysis method for I-QB topology is applicable to both the I-QZS and I-SI topologies. The conclusions obtained for the I-QB topology can be appropriately extended to the I-QZS and I-SI topologies.

3.2. Topology and Operating Principles

The I-QB converter consists of four inductors (L₁–L₄), six diodes (D₁–D₆), four capacitors (C₁–C₄), and two switches (S₁ and S₂). U_in is the input voltage, and U_o is the output voltage. The interleaved structure consisting of inductor L₁ and inductor L₃ in parallel can reduce the input current ripple. The step-up structure, which consists of inductors L₁ and L₂, diodes D₁ and D₂, and capacitor C₁ (or inductor L₃ and inductor L₄, diodes D₃ and D₄, and capacitor C₂), can expand the input voltage operating range and enhance the voltage gain. The voltage multiplier cell consisting of capacitor C₃, diode D₅, and D₆ can further increase the voltage gain.

Assume that all devices in the I-QB converter are ideal, meaning that all power semiconductor devices have zero on-resistance, no current flows when they are turned off, and the turn-on time and turn-off time of switches are zero. We also ignore the equivalent series resistance (ESR) of the inductors and capacitors. The relationship between d₁ and d₂ can be recorded as d₁ = d₂ = d, where d₁–d₂ denote the duty cycles of S₁–S₂, respectively. The phase difference between the gate–source driving signals of S₁ and S₂ is 180. When the I-QB converter operates in the continuous conduction mode (CCM), there are four switching states recorded as “S₁S₂” in a switching cycle, S₁S₂ = {00,01,10,11}. Moreover, the sequence of the switching states in one cycle is related to the duty cycle ranges of S₁ and S₂. The sequence I “10-00-01-00-10” appears within the duty cycle range of 0–0.5, while the sequence II “11-10-11-01-11” is obtained within the duty cycle range of 0.5–1.

The key operating waveforms of the I-QB converter are shown in Figure 3. The output current is I_o, and the currents of L₁, L₂, L₃, and L₄ are I_L1, I_L2, I_L3, and I_L4. Define the voltage between the cathode and the anode of the diode as the voltage stress of the diode. T_S indicates the period of the PWM driving signal. The energy flows and equivalent circuit diagrams of the I-QB converter in different operating modes are shown in Figure 4.

3.2.1. S₁S₂ = 11 (S₁ and S₂ Are ON)

As shown in Figure 4a, in this state, diodes D₁, D₃, D_5, and D₆ are reversed biased and there are five current loops in the circuit: (1) DC-source U_in is charged to L₁ through D₂ and S₁; (2) C₁ charges L₂ through S₁; (3) DC-source U_in charges L₃ through D₄ and S₂; (4) C₂ charges L₄ through S₂; and (5) the capacitor C₄ supplies energy to the load R. Moreover, the currents I_L1, I_L2, I_L3, and I_L4 increase linearly.

3.2.2. S₁S₂ = 10 (S₁ Is ON, S₂ Is OFF)

As shown in Figure 4b, diodes D₁, D₄, and D₆ are reverse biased and there are five current loops in the circuit: (1) DC-source U_in charges L₁ by D₂ and S₁; (2) the inductor L₂ is charged by the capacitor C₁ through S₁; (3) DC-source U_in and inductor L₃ charge capacitor C₂ through diode D₃; (4) DC-source U_in, inductor L₃ and inductor L₄ are connected in series to charge C₃ through D₃, D₅, and S₁; and (5) the capacitor C₄ supplies energy to the load R. In addition, the inductor currents I_L1 and I_L2 increase linearly, and I_L3 and I_L4 decrease linearly.

3.2.3. S₁S₂ = 01 (S₁ Is OFF, S₂ Is ON)

As shown in Figure 4c, diodes D₂, D₃, and D₅ are reverse biased and the circuit has five current loops: (1) DC-source U_in and inductor L₁ charges capacitor C₁ through D₁; (2) DC-source U_in, inductors L₁, L₂ and capacitor C₃ are connected in series to supply the load R; (3) DC-source U_in, inductors L₁, L₂ and capacitor C₃ are connected in series to supply power to capacitor C₄; (4) inductor L₃ charged by DC-source U_in through D₄ and S₂; (5) and capacitor C₂ charges L₄ through S₂. Moreover, the inductor currents I_L1 and I_L2 decrease linearly, while I_L3 and I_L4 increase linearly.

3.2.4. S₁S₂ = 00 (S₁ Is OFF, S₂ Is OFF)

As shown in Figure 4d, diodes D₂ and D₄ are reverse biased and the circuit has six current loops: (1) DC-source U_in and inductor L₁ charges capacitor C₁ through D₁; (2) DC-source U_in and inductor L₃ charge capacitor C₂ through diode D₃; (3) DC-source U_in, inductors L₁, L₂ and capacitor C₃ are connected in series to supply the load R; (4) DC-source U_in, inductors L₁, L₂ and capacitor C₃ are connected in series to supply power to capacitor C₄; (5) DC-source U_in, inductors L₃, L₄ are connected in series to supply the load R; and (6) DC-source U_in, inductors L₃, L₄ are connected in series to supply power to capacitor C₄. Moreover, the currents I_L1, I_L2, I_L3, and I_L4 decrease linearly.

3.3. Voltage Gain

Within the range 0 < d < 0.5, assuming the parasitic parameters of all power devices are negligible, the capacitance value and the inductance value are sufficiently large. Where U_in/U_o denotes the input/output voltage. The voltages across capacitors C₁–C₄ are U_C1, U_C2, U_C3, and U_C4, respectively. When S₁S₂ = 10, the inductor voltages across L₁–L₄ are U_L110, U_L210, U_L310, U_L410, respectively. When S₁S₂ = 01, the inductor voltages across L₁–L₄ are U_L101, U_L201, U_L301, U_L401, respectively. When S₁S₂ = 00, the inductor voltages across L₁–L₄ are U_L100, U_L200, U_L300, U_L400, respectively. When S₁S₂ = 11, the inductor voltages across L₁–L₄ are U_L111, U_L211, U_L311, U_L411, respectively. By applying KVL to Figure 4b–d, (1)–(3) can be obtained for S₁S₂ = 10, S₁S₂ = 01 and S₁S₂ = 00, respectively.

$$\left\{\begin{array}{l}{U}_{\mathrm{L}110}=U_{\mathrm{in}}\\ U_{\mathrm{L}210}=U_{\mathrm{C}1}\\ U_{\mathrm{L}310}=U_{\mathrm{in}}-U_{\mathrm{C}2}\\ U_{\mathrm{L}410}=U_{\mathrm{C}2}-U_{\mathrm{C}3}\end{array}\right.$$

(1)

$$\left\{\begin{array}{l}{U}_{\mathrm{L}101}=U_{\mathrm{in}}-U_{\mathrm{C}1}\\ U_{\mathrm{L}201}=U_{\mathrm{C}1}+U_{\mathrm{C}3}-U_{\mathrm{o}}\\ U_{\mathrm{L}301}=U_{\mathrm{in}}\\ U_{\mathrm{L}401}=U_{\mathrm{C}2}\end{array}\right.$$

(2)

$$\left\{\begin{array}{l}{U}_{\mathrm{L}100}=U_{\mathrm{in}}-U_{\mathrm{C}1}\\ U_{\mathrm{L}200}=U_{\mathrm{C}1}+U_{\mathrm{C}3}-U_{\mathrm{o}}\\ U_{\mathrm{L}300}=U_{\mathrm{in}}-U_{\mathrm{C}2}\\ U_{\mathrm{L}400}=U_{\mathrm{C}2}-U_{\mathrm{o}}\end{array}\right.$$

(3)

According to Figure 3a, by applying the volt-second balance principle to the inductors L₁–L₄, (4) can be obtained.

$$\left\{\begin{array}{l}{U}_{\mathrm{L}110}d{T}_{\mathrm{s}}+U_{\mathrm{L}101}d{T}_{\mathrm{s}}+U_{\mathrm{L}100}(1-2d)T_{\mathrm{s}}=0\\ U_{\mathrm{L}210}d{T}_{\mathrm{s}}+U_{\mathrm{L}201}d{T}_{\mathrm{s}}+U_{\mathrm{L}200}(1-2d)T_{\mathrm{s}}=0\\ U_{\mathrm{L}310}d{T}_{\mathrm{s}}+U_{\mathrm{L}301}d{T}_{\mathrm{s}}+U_{\mathrm{L}300}(1-2d)T_{\mathrm{s}}=0\\ U_{\mathrm{L}410}d{T}_{\mathrm{s}}+U_{\mathrm{L}401}d{T}_{\mathrm{s}}+U_{\mathrm{L}400}(1-2d)T_{\mathrm{s}}=0\end{array}\right.$$

(4)

Substitute (1)–(3) into (4), and (5) can be obtained as follows:

$$\left\{\begin{array}{l}{U}_{\mathrm{C}1}={\displaystyle \frac{1}{1-d}}{U}_{\mathrm{in}}={(1-d)}^2{U}_{\mathrm{o}}\\ U_{\mathrm{C}2}={\displaystyle \frac{1}{1-d}}{U}_{\mathrm{in}}={(1-d)}^2{U}_{\mathrm{o}}\\ U_{\mathrm{C}3}={\displaystyle \frac{d}{{(1-d)}^3}}{U}_{\mathrm{in}}=d{U}_{\mathrm{o}}\\ U_{\mathrm{C}4}={\displaystyle \frac{1}{{(1-d)}^3}}{U}_{\mathrm{in}}=U_{\mathrm{o}}\end{array}\right.$$

(5)

Within the range of 0.5 $\le$ d < 1, by applying KVL to Figure 4a, (6) can be obtained for S₁S₂ = 11.

$$\left\{\begin{array}{l}{U}_{\mathrm{L}111}=U_{\mathrm{in}}\\ U_{\mathrm{L}211}=U_{\mathrm{C}1}\\ U_{\mathrm{L}311}=U_{\mathrm{in}}\\ U_{\mathrm{L}411}=U_{\mathrm{C}2}\end{array}\right.$$

(6)

According to Figure 3b, by applying the volt-second balance principle to the inductors L₁–L₄, (7) can be obtained.

$$\left\{\begin{array}{l}{U}_{\mathrm{L}110}(1-d)T_{\mathrm{s}}+U_{\mathrm{L}101}(1-d)T_{\mathrm{s}}+U_{\mathrm{L}111}(2d-1)T_{\mathrm{s}}=0\\ U_{\mathrm{L}210}(1-d)T_{\mathrm{s}}+U_{\mathrm{L}201}(1-d)T_{\mathrm{s}}+U_{\mathrm{L}211}(2d-1)T_{\mathrm{s}}=0\\ U_{\mathrm{L}310}(1-d)T_{\mathrm{s}}+U_{\mathrm{L}301}(1-d)T_{\mathrm{s}}+U_{\mathrm{L}311}(2d-1)T_{\mathrm{s}}=0\\ U_{\mathrm{L}410}(1-d)T_{\mathrm{s}}+U_{\mathrm{L}401}(1-d)T_{\mathrm{s}}+U_{\mathrm{L}411}(2d-1)T_{\mathrm{s}}=0\end{array}\right.$$

(7)

Substitute (1), (2) and (6) into (7) and (8) can be obtained as follows:

$$\left\{\begin{array}{l}{U}_{\mathrm{C}1}={\displaystyle \frac{1}{1-d}}{U}_{\mathrm{in}}={\displaystyle \frac{1-d}{2}}{U}_{\mathrm{o}}\\ U_{\mathrm{C}2}={\displaystyle \frac{1}{1-d}}{U}_{\mathrm{in}}={\displaystyle \frac{1-d}{2}}{U}_{\mathrm{o}}\\ U_{\mathrm{C}3}={\displaystyle \frac{1}{{(1-d)}^2}}{U}_{\mathrm{in}}={\displaystyle \frac{1}{2}}{U}_{\mathrm{o}}\\ U_{\mathrm{C}4}={\displaystyle \frac{2}{{(1-d)}^2}}{U}_{\mathrm{in}}=U_{\mathrm{o}}\end{array}\right.$$

(8)

3.4. Voltage Stress

The voltage and current stresses are important criteria for selecting electronic devices, as the stresses will impact the durability and lifetime of the converter.

Ignore the forward voltage drop and the other parasitic parameters of the semiconductor devices. When d is within 0–0.5, according to (2) and Figure 4, the voltage stresses of all devices in the I-QB converter are expressed in

Table 1. Voltage stress of power devices (0 < d < 0.5).

Device	S1	S2	D1	D2
Voltage Stress	$(1-d)U_{\mathrm{o}}$	$U_{\mathrm{o}}$	${(1-d)}^2{U}_{\mathrm{o}}$	$d(1-d)U_{\mathrm{o}}$
Device	D3	D4	D5	D6
Voltage Stress	${(1-d)}^2{U}_{\mathrm{o}}$	$d(2-d)U_{\mathrm{o}}$	$U_{\mathrm{o}}$	$(1-d)U_{\mathrm{o}}$
Device	C1	C2	C3	C4
Voltage Stress	${(1-d)}^2{U}_{\mathrm{o}}$	${(1-d)}^2{U}_{\mathrm{o}}$	$d{U}_{\mathrm{o}}$	$U_{\mathrm{o}}$

. U_D1–U_D6 denote the voltage stresses across diodes D₁–D₆, respectively. U_S1 and U_S2 represent the voltage stresses of switches S₁ and S₂, respectively.

As indicated in Table 1, within the interval of 0 < d < 0.5, S₂, D₅, and C₄ exhibit the highest voltage stress, equivalent to the output voltage. D₂, D₄, and C₃ achieve their maximum voltage stress at d = 0.5, corresponding to 0.25 times, 0.75 times, and 0.5 times the output voltage, respectively. The voltage stress on the other components decreases as the duty cycle increases, remaining below 0.5 times the output voltage. Therefore, assuming a vehicle DC bus voltage of 300 V, to ensure sufficient margin and device reliability, C₃ and C₄ are selected as electrolytic capacitors with a withstand voltage of 900 V (achieved through the series–parallel connection of capacitors), while C₁ and C₂ are chosen as electrolytic capacitors with a withstand voltage of 450 V. All power devices are selected with a withstand voltage of 1200 V. However, in actual passenger FCVs, due to the relatively low voltage of the FC, high voltage stress typically does not occur in the low duty cycle range. Consequently, this paper should also focus on the results within the interval of 0.5 ≤ d < 1 during component selection.

When d is within 0.5–1, according to (4) and Figure 4, the voltage stresses of all devices in the I-QB converter are expressed in

Table 2. Voltage stress of power devices (0.5 $\le$ d < 1).

Device	S1	S2	D1	D2
Voltage Stress	${\displaystyle \frac{U_{\mathrm{o}}}{2}}$	${\displaystyle \frac{U_{\mathrm{o}}}{2}}$	${\displaystyle \frac{1-d}{2}}{U}_{\mathrm{o}}$	${\displaystyle \frac{d}{2}}{U}_{\mathrm{o}}$
Device	D3	D4	D5	D6
Voltage Stress	${\displaystyle \frac{1-d}{2}}{U}_{\mathrm{o}}$	${\displaystyle \frac{d}{2}}{U}_{\mathrm{o}}$	$U_{\mathrm{o}}$	${\displaystyle \frac{U_{\mathrm{o}}}{2}}$
Device	C1	C2	C3	C4
Voltage Stress	${\displaystyle \frac{1-d}{2}}{U}_{\mathrm{o}}$	${\displaystyle \frac{1-d}{2}}{U}_{\mathrm{o}}$	${\displaystyle \frac{U_{\mathrm{o}}}{2}}$	$U_{\mathrm{o}}$

.

From Table 2, with the exception of D₅ and C₄, whose voltage stress is equivalent to the output voltage, the voltage stress on all other components is less than half of the output voltage. Assuming a vehicle bus voltage of 300 V, the aforementioned component selection remains reasonable and meets the requirements. Given that the DC/DC converter in passenger FCVs typically operates at a relatively high duty cycle, this paper will focus on the results within the interval of 0.5 $\le$ d < 1.

3.5. Current Stress

In the range of 0 < d < 0.5, I_L1–I_L4 denote the current flowing through L₁–L₄, and I_o/I_in denotes the output/input current. When S₁S₂ = 10, the average currents through capacitors C₁–C₄ are I_C110, I_C210, I_C310 and I_C410, respectively. When S₁S₂ = 01, the average currents through capacitors C₁–C₄ are I_C101, I_C201, I_C301 and I_C401, respectively. When S₁S₂ = 00, the average currents through capacitors C₁–C₄ are I_C100, I_C200, I_C300 and I_C400, respectively. When S₁S₂ = 11, the average currents through capacitors C1–C4 are I_C111, I_C211, I_C311 and I_C411, respectively. By applying KCL to Figure 4b–d, (9)–(11) can be obtained for S₁S₂ = 10, S₁S₂ = 01 and S₁S₂ = 00, respectively.

$$\left\{\begin{array}{l}{I}_{\mathrm{C}110}=-I_{\mathrm{L}2}\\ I_{\mathrm{C}210}=I_{\mathrm{L}3}-I_{\mathrm{L}4}\\ I_{\mathrm{C}310}=I_{\mathrm{L}4}\\ I_{\mathrm{C}410}=-I_{\mathrm{o}}\end{array}\right.$$

(9)

$$\left\{\begin{array}{l}{I}_{\mathrm{C}101}=I_{\mathrm{L}1}-I_{\mathrm{L}2}\\ I_{\mathrm{C}201}=-I_{\mathrm{L}4}\\ I_{\mathrm{C}301}=-I_{\mathrm{L}2}\\ I_{\mathrm{C}401}=I_{\mathrm{L}2}-I_{\mathrm{o}}\end{array}\right.$$

(10)

$$\left\{\begin{array}{l}{I}_{\mathrm{C}100}=I_{\mathrm{L}1}-I_{\mathrm{L}2}\\ I_{\mathrm{C}200}=I_{\mathrm{L}3}-I_{\mathrm{L}4}\\ I_{\mathrm{C}300}=-I_{\mathrm{L}2}\\ I_{\mathrm{C}400}=I_{\mathrm{L}2}+I_{\mathrm{L}4}-I_{\mathrm{o}}\end{array}\right.$$

(11)

According to Figure 3a, by applying the ampere-second balance principle to the capacitors C₁–C₄, (12) can be obtained.

$$\left\{\begin{array}{l}{I}_{\mathrm{C}110}d{T}_{\mathrm{s}}+I_{\mathrm{C}101}d{T}_{\mathrm{s}}+I_{\mathrm{C}100}(1-2d)T_{\mathrm{s}}=0\\ I_{\mathrm{C}210}d{T}_{\mathrm{s}}+I_{\mathrm{C}201}d{T}_{\mathrm{s}}+I_{\mathrm{C}200}(1-2d)T_{\mathrm{s}}=0\\ I_{\mathrm{C}310}d{T}_{\mathrm{s}}+I_{\mathrm{C}301}d{T}_{\mathrm{s}}+I_{\mathrm{C}300}(1-2d)T_{\mathrm{s}}=0\\ I_{\mathrm{C}410}d{T}_{\mathrm{s}}+I_{\mathrm{C}401}d{T}_{\mathrm{s}}+I_{\mathrm{C}400}(1-2d)T_{\mathrm{s}}=0\end{array}\right.$$

(12)

Substitute (9)–(11) into (12); then, (14) can be derived as follows:

$$\left\{\begin{array}{l}{I}_{\mathrm{L}1}={\displaystyle \frac{d}{{(1-d)}^3}}{I}_{\mathrm{o}}\\ I_{\mathrm{L}2}={\displaystyle \frac{d}{{(1-d)}^2}}{I}_{\mathrm{o}}\\ I_{\mathrm{L}3}={\displaystyle \frac{1}{{(1-d)}^2}}{I}_{\mathrm{o}}\\ I_{\mathrm{L}4}={\displaystyle \frac{1}{1-d}}{I}_{\mathrm{o}}\end{array}\right.$$

(13)

$$I_{\mathrm{in}}=I_{\mathrm{L}1}+I_{\mathrm{L}3}={\displaystyle \frac{1}{{(1-d)}^3}}{I}_{\mathrm{o}}$$

(14)

Within the range of 0.5 $\le$ d < 1, by applying KVL to Figure 4a, (15) can be obtained for S₁S₂ = 11.

$$\left\{\begin{array}{l}{I}_{\mathrm{C}111}=-I_{\mathrm{L}2}\\ I_{\mathrm{C}211}=-I_{\mathrm{L}4}\\ I_{\mathrm{C}311}=0\\ I_{\mathrm{C}411}=-I_{\mathrm{o}}\end{array}\right.$$

(15)

According to Figure 3b, by applying the ampere-second balance principle to the capacitors C₁–C₄, (16) can be obtained.

$$\left\{\begin{array}{l}{I}_{\mathrm{C}110}(1-d)T_{\mathrm{s}}+I_{\mathrm{C}101}(1-d)T_{\mathrm{s}}+I_{\mathrm{C}111}(2d-1)T_{\mathrm{s}}=0\\ I_{\mathrm{C}210}(1-d)T_{\mathrm{s}}+I_{\mathrm{C}201}(1-d)T_{\mathrm{s}}+I_{\mathrm{C}211}(2d-1)T_{\mathrm{s}}=0\\ I_{\mathrm{C}310}(1-d)T_{\mathrm{s}}+I_{\mathrm{C}301}(1-d)T_{\mathrm{s}}+I_{\mathrm{C}311}(2d-1)T_{\mathrm{s}}=0\\ I_{\mathrm{C}410}(1-d)T_{\mathrm{s}}+I_{\mathrm{C}401}(1-d)T_{\mathrm{s}}+I_{\mathrm{C}411}(2d-1)T_{\mathrm{s}}=0\end{array}\right.$$

(16)

Substitute (9), (10) and (15) into (16); then, (18) can be derived as follows:

$$\left\{\begin{array}{l}{I}_{\mathrm{L}1}=I_{\mathrm{L}3}={\displaystyle \frac{1}{{(1-d)}^2}}{I}_{\mathrm{o}}\\ I_{\mathrm{L}2}=I_{\mathrm{L}4}={\displaystyle \frac{1}{1-d}}{I}_{\mathrm{o}}\end{array}\right.$$

(17)

$$I_{\mathrm{in}}=I_{\mathrm{L}1}+I_{\mathrm{L}3}={\displaystyle \frac{2}{{(1-d)}^2}}{I}_{\mathrm{o}}$$

(18)

In the range of 0 < d < 0.5, the current stresses of all devices can be calculated as shown in

Table 3. Current stress of power devices (0 < d < 0.5).

Device	S1	S2	D1	D2
Current Stress	${\displaystyle \frac{I_{\mathrm{o}}}{{(1-d)}^3}}$	${\displaystyle \frac{2-d}{{(1-d)}^2}}{I}_{\mathrm{o}}$	${\displaystyle \frac{d}{{(1-d)}^3}}{I}_{\mathrm{o}}$	${\displaystyle \frac{d}{{(1-d)}^3}}{I}_{\mathrm{o}}$
Device	D3	D4	D5	D6
Current Stress	${\displaystyle \frac{I_{\mathrm{o}}}{{(1-d)}^2}}$	${\displaystyle \frac{I_{\mathrm{o}}}{{(1-d)}^2}}$	${\displaystyle \frac{I_{\mathrm{o}}}{1-d}}$	${\displaystyle \frac{I_{\mathrm{o}}}{{(1-d)}^2}}$
Device	L1	L2	L3	L4
Current Stress	${\displaystyle \frac{d}{{(1-d)}^3}}{I}_{\mathrm{o}}$	${\displaystyle \frac{d}{{(1-d)}^2}}{I}_{\mathrm{o}}$	${\displaystyle \frac{I_{\mathrm{o}}}{{(1-d)}^2}}$	${\displaystyle \frac{I_{\mathrm{o}}}{1-d}}$

. In this paper, the current stresses of all semiconductor devices are defined as the maximum average current in all operating modes.

As shown in Table 3, the current stress of all components increases monotonically with the duty cycle, reaching its peak at a duty cycle of 0.5. At this point, the maximum current stress on the inductors, switches, and diodes is four times, eight times, and four times the output current, respectively. Considering that the current stress on components continues to increase within the interval 0.5 $\le$ d < 1, it is not feasible to select components based on Table 3.

In the range of 0.5 $\le$ d < 1, the current stresses of all devices can be calculated as shown in

Table 4. Current stress of power devices (0.5 $\le$ d < 1).

Device	S1	S2	D1	D2
Current Stress	${\displaystyle \frac{3-2d}{{(1-d)}^2}}{I}_o$	${\displaystyle \frac{2-d}{{(1-d)}^2}}{I}_o$	${\displaystyle \frac{I_o}{{(1-d)}^2}}$	${\displaystyle \frac{I_o}{{(1-d)}^2}}$
Device	D3	D4	D5	D6
Current Stress	${\displaystyle \frac{I_o}{{(1-d)}^2}}$	${\displaystyle \frac{I_o}{{(1-d)}^2}}$	${\displaystyle \frac{I_o}{1-d}}$	${\displaystyle \frac{I_o}{1-d}}$
Device	L1	L2	L3	L4
Current Stress	${\displaystyle \frac{I_o}{{(1-d)}^2}}$	${\displaystyle \frac{I_o}{1-d}}$	${\displaystyle \frac{I_o}{{(1-d)}^2}}$	${\displaystyle \frac{I_o}{1-d}}$

.

As indicated in Table 4, the current stress on all components also increases monotonically with the duty cycle. Based on the power, load, and output voltage, at a duty cycle of 0.8, the maximum current stress on the inductors, switches, and diodes is 16.67 A, 16.67 A, and 35 A, respectively. To enhance the devices’ reliability and ensure a sufficient margin, this paper selects the inductors with a maximum operating current of 20 A. To minimize device losses and heat generation, SiC devices with low on-resistance (R_ds(on)) are chosen. Considering the devices’ current-carrying capacity and design margin, diodes with I_F = 88 A and switches with I_D = 65 A are selected. Based on the aforementioned voltage results, the selected diodes and switches are SCTWA50N120 and C4D30120D, respectively. It is evident that utilizing wide-bandgap devices to build DC/DC converters will become a trend.

3.6. Current Ripple

In the range of 0.5 $\le$ d < 1, the input current ripple ΔI_in can be presented as (19).

$$\Delta I_{\mathrm{in}}=(I_{\mathrm{L}1\mathrm{a}}+I_{\mathrm{L}3\mathrm{a}})-(I_{\mathrm{L}1\mathrm{b}}+I_{\mathrm{L}3\mathrm{b}})=(I_{\mathrm{L}1\mathrm{a}}-I_{\mathrm{L}1\mathrm{b}})+(I_{\mathrm{L}3\mathrm{a}}-I_{\mathrm{L}3\mathrm{b}})$$

(19)

where I_L1a are I_L1b are the values of I_L1 at t₃ and t₂, respectively; I_L3a and I_L3b are the values of I_L3 at t₃ and t₂, respectively. When the I-QB converter is in the S₁S₂ = 11 and operates in the t₂–t₃ stage (see Figure 3b), (20) can be obtained.

$$\left\{\begin{array}{l}{I}_{\mathrm{L}1\mathrm{a}}-I_{\mathrm{L}1\mathrm{b}}={\displaystyle \frac{(2d-1)U_{\mathrm{in}}{T}_{\mathrm{s}}}{2L_1}}\\ I_{\mathrm{L}3\mathrm{a}}-I_{\mathrm{L}3\mathrm{b}}={\displaystyle \frac{(2d-1)U_{\mathrm{in}}{T}_{\mathrm{s}}}{2L_3}}\end{array}\right.$$

(20)

When inductors L₁ and L₃ have the same inductance, the input current ripple ΔI_in can be obtained by substituting (20) into (19), as shown in (21).

$$\Delta I_{\mathrm{in}}={\displaystyle \frac{(2d-1)U_{\mathrm{in}}{T}_{\mathrm{s}}}{L_1}}={\displaystyle \frac{(2d-1){(1-d)}^2{U}_{\mathrm{o}}{T}_{\mathrm{s}}}{2L_1}}$$

(21)

Similarly to the analysis of the input current ripple, the current ripples of inductors L₁, L₂, L₃ and L₄ can be expressed as (22).

$$\left\{\begin{array}{l}\Delta I_{\mathrm{L}1}={\displaystyle \frac{d{U}_{\mathrm{in}}{T}_{\mathrm{s}}}{L_1}}\\ \Delta I_{\mathrm{L}2}={\displaystyle \frac{d{U}_{\mathrm{C}1}{T}_{\mathrm{s}}}{L_2}}\\ \Delta I_{\mathrm{L}3}={\displaystyle \frac{d{U}_{\mathrm{in}}{T}_{\mathrm{s}}}{L_3}}\\ \Delta I_{\mathrm{L}4}={\displaystyle \frac{d{U}_{\mathrm{C}2}{T}_{\mathrm{s}}}{L_4}}\end{array}\right.$$

(22)

In the range of 0 < d < 0.5, using the similar method, (23) can be obtained. The current ripples of inductors L₁–L₄ are the same as that in the range of 0.5 $\le$ d < 1 (Equation (22)).

$$\Delta I_{\mathrm{in}}={\displaystyle \frac{d(1-2d)U_{\mathrm{in}}{T}_{\mathrm{s}}}{(1-d)L_1}}={\displaystyle \frac{d(1-2d){(1-d)}^2{U}_{\mathrm{o}}{T}_{\mathrm{s}}}{L_1}}$$

(23)

3.7. Power Losses

To examine the efficiency of the prototype with the designed topology, the power losses of the I-QB converter are investigated. The power losses of the converter mainly include the switching, conduction, and driving losses of switches, the switching and conduction losses of diodes, the ESR losses of capacitors, and the iron and copper losses of inductors, which are denoted by P_{S_switch}, P_{S_cond}, P_{S_drive}, P_{D_switch}, P_{D_cond}, P_C, P_Fe, and P_Cu, respectively.

To simplify the calculation, the voltage/current ripples across the inductors/capacitors are ignored. Moreover, it is assumed that there are no differences between the identical parasitic parameters of the same components.

The losses of the switches P_S can be calculated in (24) and (25).

$$\left\{\begin{array}{l}{P}_{\mathrm{S}}=P_{\mathrm{S}\_\mathrm{switch}}+P_{\mathrm{S}\_\mathrm{cond}}+P_{\mathrm{S}\_\mathrm{drive}}\\ P_{\mathrm{S}\_\mathrm{switch}}={\displaystyle \frac{d{P}_{\mathrm{o}}{f}_{\mathrm{s}}}{2{(1-d)}^3}}\left(T_{\mathrm{S}\_\mathrm{on}}+T_{\mathrm{S}\_\mathrm{off}}\right)+{\displaystyle \frac{d(2-d)P_{\mathrm{o}}{f}_{\mathrm{s}}}{2{(1-d)}^2}}\left(T_{\mathrm{S}\_\mathrm{on}}+T_{\mathrm{S}\_\mathrm{off}}\right)\\ P_{\mathrm{S}\_\mathrm{cond}}={\displaystyle \frac{d{P}_{\mathrm{o}}{r}_{\mathrm{S}}}{{(1-d)}^{6}R}}+{\displaystyle \frac{d{(2-d)}^2{P}_{\mathrm{o}}{r}_{\mathrm{S}}}{{(1-d)}^{4}R}}\\ P_{\mathrm{S}\_\mathrm{drive}}=2U_{\mathrm{S}\_\mathrm{drive}}{Q}_{\mathrm{S}\_\mathrm{gate}}{f}_{\mathrm{s}}\end{array}\right.; 0<d<0.5$$

(24)

$$\left\{\begin{array}{l}{P}_{\mathrm{S}}=P_{\mathrm{S}\_\mathrm{switch}}+P_{\mathrm{S}\_\mathrm{cond}}+P_{\mathrm{S}\_\mathrm{drive}}\\ P_{\mathrm{S}\_\mathrm{switch}}={\displaystyle \frac{d(3-2d)P_{\mathrm{o}}{f}_{\mathrm{s}}}{2{(1-d)}^2}}\left(T_{\mathrm{S}\_\mathrm{on}}+T_{\mathrm{S}\_\mathrm{off}}\right)+{\displaystyle \frac{d(2-d)P_{\mathrm{o}}{f}_{\mathrm{s}}}{2{(1-d)}^2}}\left(T_{\mathrm{S}\_\mathrm{on}}+T_{\mathrm{S}\_\mathrm{off}}\right)\\ P_{\mathrm{S}\_\mathrm{cond}}={\displaystyle \frac{d{(3-2d)}^2{P}_{\mathrm{o}}{r}_{\mathrm{S}}}{{(1-d)}^{4}R}}+{\displaystyle \frac{d{(2-d)}^2{P}_{\mathrm{o}}{r}_{\mathrm{S}}}{{(1-d)}^{4}R}}\\ P_{\mathrm{S}\_\mathrm{drive}}=2U_{\mathrm{S}\_\mathrm{drive}}{Q}_{\mathrm{S}\_\mathrm{gate}}{f}_{\mathrm{s}}\end{array}\right.; 0.5\le d<1$$

(25)

where T_{S_on} represents the turn-on delay time of S₁ and S₂; T_{S_off} represents the turn-off delay-time of S₁ and S₂; U_{S_drive} represents the drive voltages of S₁ and S₂; Q_{S_gate} represents the gate charges of S₁ and S₂; r_S represents the MOSFET’s (S₁–S₂) on-resistances; and f_s denotes the switching frequency. The losses of diodes P_D can be derived using (26) and (27).

$$\left\{\begin{array}{l}{P}_{\mathrm{D}}=P_{\mathrm{D}\_\mathrm{switch}}+P_{\mathrm{D}\_\mathrm{cond}}\\ P_{\mathrm{D}\_\mathrm{switch}}=2Q_{\mathrm{D}}{(1-d)}^2{U}_{\mathrm{o}}{f}_{\mathrm{s}}+Q_{\mathrm{D}}d(1-d)U_{\mathrm{o}}{f}_{\mathrm{s}}+Q_{\mathrm{D}}d(2-d)U_{\mathrm{o}}{f}_{\mathrm{s}}+Q_{\mathrm{D}}{U}_{\mathrm{o}}{f}_{\mathrm{s}}+Q_{\mathrm{D}}(1-d)U_{\mathrm{o}}{f}_{\mathrm{s}}\\ P_{\mathrm{D}\_\mathrm{cond}}={\displaystyle \frac{d^2{V}_{\mathrm{F}}{I}_{\mathrm{o}}}{{(1-d)}^3}}+{\displaystyle \frac{3d{V}_{\mathrm{F}}{I}_{\mathrm{o}}}{{(1-d)}^2}}+{\displaystyle \frac{d{V}_{\mathrm{F}}{I}_{\mathrm{o}}}{1-d}}+{\displaystyle \frac{V_{\mathrm{F}}{I}_{\mathrm{o}}}{1-d}}\end{array}\right.; 0<d<0.5$$

(26)

$$\left\{\begin{array}{l}{P}_{\mathrm{D}}=P_{\mathrm{D}\_\mathrm{switch}}+P_{\mathrm{D}\_\mathrm{cond}}\\ P_{\mathrm{D}\_\mathrm{switch}}=Q_{\mathrm{D}}(1-d)U_{\mathrm{o}}{f}_{\mathrm{s}}+Q_{\mathrm{D}}d{U}_{\mathrm{o}}{f}_{\mathrm{s}}+Q_{\mathrm{D}}{U}_{\mathrm{o}}{f}_{\mathrm{s}}+{\displaystyle \frac{Q_{\mathrm{D}}{U}_{\mathrm{o}}{f}_{\mathrm{s}}}{2}}\\ P_{\mathrm{D}\_\mathrm{cond}}={\displaystyle \frac{2V_{\mathrm{F}}{I}_{\mathrm{o}}}{1-d}}+{\displaystyle \frac{2d{V}_{\mathrm{F}}{I}_{\mathrm{o}}}{1-d}}+{\displaystyle \frac{2d{V}_{\mathrm{F}}{I}_{\mathrm{o}}}{{(1-d)}^2}}\end{array}\right.; 0.5\le d<1$$

(27)

where Q_D is the reverse recovery charge of diodes D₁–D₆, and V_F is the diodes’ (D₁–D₆) threshold voltage. The losses of capacitors P_C can be calculated in (28) and (29).

$$P_{\mathrm{C}}={\displaystyle \frac{d^3{P}_{\mathrm{o}}{R}_{\mathrm{ESR}\_\mathrm{C}}}{{(1-d)}^{5}R}}+{\displaystyle \frac{2d{P}_{\mathrm{o}}{R}_{\mathrm{ESR}\_\mathrm{C}}}{{(1-d)}^{3}R}}+{\displaystyle \frac{d(2-4d+d^2)P_{\mathrm{o}}{R}_{\mathrm{ESR}\_\mathrm{C}}}{{(1-d)}^{3}R}}; 0<d<0.5$$

(28)

$$P_{\mathrm{C}}={\displaystyle \frac{2d{P}_{\mathrm{o}}{R}_{\mathrm{ESR}\_\mathrm{C}}}{{(1-d)}^{3}R}}+{\displaystyle \frac{2P_{\mathrm{o}}{R}_{\mathrm{ESR}\_\mathrm{C}}}{(1-d)R}}+{\displaystyle \frac{d{P}_{\mathrm{o}}{R}_{\mathrm{ESR}\_\mathrm{C}}}{(1-d)R}}; 0.5\le d<1$$

(29)

where R_{ESR_C} is the equivalent series resistances of capacitors C₁–C₄. The losses of the inductors P_L can be calculated in (30) and (31).

$$\left\{\begin{array}{l}{P}_{\mathrm{L}}=P_{\mathrm{Cu}}+P_{\mathrm{Fe}}\\ P_{\mathrm{Cu}}={\displaystyle \frac{d^2{P}_{\mathrm{o}}{r}_{\mathrm{L}}}{{(1-d)}^{6}R}}+{\displaystyle \frac{d^2{P}_{\mathrm{o}}{r}_{\mathrm{L}}}{{(1-d)}^{4}R}}+{\displaystyle \frac{P_{\mathrm{o}}{r}_{\mathrm{L}}}{{(1-d)}^{4}R}}+{\displaystyle \frac{P_{\mathrm{o}}{r}_{\mathrm{L}}}{{(1-d)}^{2}R}}\\ P_{\mathrm{Fe}}=4l_{\mathrm{e}}{A}_{\mathrm{e}}a{B}^{\mathrm{b}}{f}_{\mathrm{s}}^{\mathrm{c}}\end{array}\right.; 0\le d<0.5$$

(30)

$$\left\{\begin{array}{l}{P}_{\mathrm{L}}=P_{\mathrm{Cu}}+P_{\mathrm{Fe}}\\ P_{\mathrm{Cu}}={\displaystyle \frac{2P_{\mathrm{o}}{r}_{\mathrm{L}}}{{(1-d)}^{4}R}}+{\displaystyle \frac{2P_{\mathrm{o}}{r}_{\mathrm{L}}}{{(1-d)}^{2}R}}\\ P_{\mathrm{Fe}}=4l_{\mathrm{e}}{A}_{\mathrm{e}}a{B}^{\mathrm{b}}{f}_{\mathrm{s}}^{\mathrm{c}}\end{array}\right.; 0.5\le d<1$$

(31)

where r_L is the ESR of inductors L₁–L₄. l_e is the length of the magnetic path and A_e is the cross-section of the core. a, b and c are the empirical parameters fitted according to the magnetic core data manual, and B is half of the AC flux swing.

Thus, the efficiency of the I-QB converter can be calculated in (32).

$$\eta ={\displaystyle \frac{P_{\mathrm{o}}}{P_{\mathrm{o}}+P_{\mathrm{S}}+P_{\mathrm{D}}+P_{\mathrm{C}}+P_{\mathrm{L}}}}$$

(32)

4. Comparisons

To prove the advantages of the I-QB converter in FCV application, a comparison with other existing DC/DC converters is performed in terms of voltage gain, the input current ripple, device stress, device number, and common ground or not, etc. The comparisons are summarized in

Table 5. Comparisons among different DC/DC converters.

Paper	Voltage Gain	Ripple Rate of Input Currents	Input Current	Voltage Stress of						Number of				Common Ground
				Switches (VQ/Vo)		Diodes (VD/Vo)		Capacitors (VC/Vo)		C	L	S	D
Ref. [22] (0.5 < d < 0.75)	${\displaystyle \frac{2}{3-4d}}$	${\displaystyle \frac{(1-d)(2d-1)(3-4d)R}{4L{f}_s}}$	Non-pulsating	S1/ S2	1/2	D1–D3	1/2	C1	$d-1/2$	4	2	2	3	Yes
								C2	$1-d$
								C3	1/2
								C4	1
Ref. [4]	${\displaystyle \frac{3+d}{{(1-d)}^2}}$	${\displaystyle \frac{d{(1-d)}^{4}R}{{(3+d)}^{2}L{f}_s}}$	Non-pulsating	S1	${\displaystyle \frac{1-d}{3+d}}$	D1/D2	${\displaystyle \frac{1-d}{3+d}}$	C1/ C2	${\displaystyle \frac{1-d}{3+d}}$	5	2	2	5	Yes
				S2	${\displaystyle \frac{1+d}{3+d}}$	D3–D5	${\displaystyle \frac{2}{3+d}}$	C3/ C5	${\displaystyle \frac{2}{3+d}}$
								C4	${\displaystyle \frac{1+d}{3+d}}$
Ref. [23] (0 < d < 0.5)	${\displaystyle \frac{2}{1-2d}}$	${\displaystyle \frac{d{(1-2d)}^{2}R}{2L{f}_s}}$	Non-pulsating	S1/ S2	1/2	D1–D5	1/2	C1– C4	1/2	4	1	2	5	Yes
Ref. [19]	${\displaystyle \frac{1+d}{1-d}}$	${\displaystyle \frac{d{(1-d)}^{2}R}{{(1+d)}^{2}L{f}_s}}$	Non-pulsating	S	${\displaystyle \frac{1}{1+d}}$	D1	1/2	C1/ C2	1/2	3	2	1	2	Yes
						D2	${\displaystyle \frac{1}{1+d}}$	C3	${\displaystyle \frac{1}{1+d}}$
Ref. [20]	${\displaystyle \frac{1+d(1-d)}{{(1-d)}^2}}$	${\displaystyle \frac{d{(1-d)}^{4}R}{{(1+d-d^2)}^{2}L{f}_s}}$	Non-pulsating	S	${\displaystyle \frac{1}{1+d(1-d)}}$	D1/D4	${\displaystyle \frac{1-d}{1+d(1-d)}}$	C1	1	4	3	1	4	No
						D2	${\displaystyle \frac{d}{1+d(1-d)}}$	C2	${\displaystyle \frac{d(1-d)}{1+d(1-d)}}$
						D3	${\displaystyle \frac{1}{1+d(1-d)}}$	C3/ C4	${\displaystyle \frac{1-d}{1+d(1-d)}}$
Ref. [26]	${\displaystyle \frac{1+3d}{1-d}}$	/	Pulsating	S1/ S2	${\displaystyle \frac{d}{1+3d}}$	D1–D4	${\displaystyle \frac{d}{1+3d}}$	C	1	1	4	2	4	No
Ref. [14] (0 < d < 0.5)	${\displaystyle \frac{3-2d}{1-2d}}$	/	Pulsating	S	${\displaystyle \frac{1}{3-2d}}$	D1–D4	${\displaystyle \frac{1}{3-2d}}$	C1– C3	${\displaystyle \frac{1-d}{3-2d}}$	5	2	1	4	No
								C4	${\displaystyle \frac{1}{3-2d}}$
								C5	${\displaystyle \frac{2-2d}{3-2d}}$
Ref. [13]	${\displaystyle \frac{2-d}{{(1-d)}^2}}$	/	Pulsating	S	${\displaystyle \frac{1}{{(1-d)}^2}}$	D1	${\displaystyle \frac{d}{{(1-d)}^2}}$	C1	${\displaystyle \frac{d(1-d)}{2-d}}$	3	2	1	4	Yes
						D2	${\displaystyle \frac{1}{1-d}}$
						D3/D4	${\displaystyle \frac{1}{{(1-d)}^2}}$	C2	${\displaystyle \frac{1-d}{2-d}}$
								C3	1
Ref. [10] (0 < d < 0.5)	${\displaystyle \frac{1+d}{1-2d}}$	/	Pulsating	S	${\displaystyle \frac{1-d}{1-2d}}$	D1	${\displaystyle \frac{d}{1+d}}$	C1/ C2	${\displaystyle \frac{1-d}{1+d}}$	5	3	1	3	No
						D2	${\displaystyle \frac{1}{1+d}}$	C3/ C4	${\displaystyle \frac{1}{1+d}}$
								C5	1
Ref. [27]	${\displaystyle \frac{6}{1-d}}$	${\displaystyle \frac{(2d-1){(1-d)}^{2}R}{36L{f}_s}}$ (d > 0.5)	Low input current ripple	S1/ S2	1/6	D1 –D6	1/3	C1/ C2	1/6	6	2	2	6	No
								C3/ C4	1/3
								C5/ C6	1/2
Ref. [17]	${\displaystyle \frac{2+2d}{1-d}}$	${\displaystyle \frac{d{(1-d)}^{2}R}{{(2+2d)}^{2}L{f}_s}}$	Non-pulsating	S	${\displaystyle \frac{1}{2+2d}}$	D1– D5	${\displaystyle \frac{1}{2+2d}}$	C1,2,6,7	${\displaystyle \frac{d}{2+2d}}$	7	3	1	5	No
								C3– C5	${\displaystyle \frac{1}{2+2d}}$
Ref. [24] (0 < d < 0.5)	${\displaystyle \frac{4}{1-2d}}$	${\displaystyle \frac{d{(1-2d)}^{2}R}{16L{f}_s}}$	Non-pulsating	S1	${\displaystyle \frac{1}{1-2d}}$	D1,2,6	1/4	C1/ C2	1/4	5	1	2	6	Yes
				S2	${\displaystyle \frac{2}{1-2d}}$	D3/ D5	1/2	C3– C5	1/2
Ref. [25]	${\displaystyle \frac{2}{1-d}}$	${\displaystyle \frac{d(1-d)(1-2d)R}{4L{f}_s}}$ ${\displaystyle \frac{(2d-1){(1-d)}^{2}R}{4L{f}_s}}$	Low input current ripple	S1/ S2	1/2	D1/ D2	1	C1/ C2	1/2	3	2	2	4	Yes
						D3/ D4	1/2	C3	1
Ref. [28]	${\displaystyle \frac{2}{1-d}}$	${\displaystyle \frac{d(1-d)(1-2d)R}{4L{f}_s}}$ ${\displaystyle \frac{(2d-1){(1-d)}^{2}R}{4L{f}_s}}$	Low input current ripple	S1/ S2	1/2	D1–D3	1/2	C1– C3	1/2	3	2	2	3	No
I-QB	${\displaystyle \frac{1}{{(1-d)}^3}}$ ${\displaystyle \frac{2}{{(1-d)}^2}}$	${\displaystyle \frac{d(1-2d){(1-d)}^{5}R}{L{f}_s}}$ ${\displaystyle \frac{(2d-1){(1-d)}^{4}R}{4L{f}_s}}$	Low input current ripple	S1/ S2	1/2	D1/D3	${\displaystyle \frac{1-d}{2}}$	C1/ C2	${\displaystyle \frac{1-d}{2}}$	4	4	2	6	Yes
						D2/D4	$d/2$
						D5	1	C3	1/2
						D6	1/2	C4	1
I-QZS (0 < d < 0.5)	${\displaystyle \frac{2}{1-2d}}$	${\displaystyle \frac{d{(1-2d)}^{2}R}{4L{f}_s}}$	Low input current ripple	S1/ S2	1/2	D1	1/2	C1/ C3	${\displaystyle \frac{1-d}{2}}$	6	4	2	4	Yes
						D2	1/2	C2/ C4	${\displaystyle \frac{d}{2}}$
						D3	1/2	C5	1/2
						D4	1/2	C6	1
I-SI	${\displaystyle \frac{1+2d-d^2}{{(1-d)}^3}}$ ${\displaystyle \frac{3+d}{{(1-d)}^2}}$	${\displaystyle \frac{d(1-2d){(1-d)}^{5}R}{{(1+2d-d^2)}^{2}L{f}_s}}$ ${\displaystyle \frac{(2d-1){(1-d)}^{4}R}{{(3+d)}^{2}L{f}_s}}$	Low input current ripple	S1/ S3	${\displaystyle \frac{1-d}{3+d}}$	D1–D4	${\displaystyle \frac{1-d}{3+d}}$	C1– C4	${\displaystyle \frac{1-d}{3+d}}$	6	4	4	6	Yes
				S2/ S4	${\displaystyle \frac{1+d}{3+d}}$	D5	${\displaystyle \frac{2}{3+d}}$	D5	${\displaystyle \frac{2}{3+d}}$
						D6	${\displaystyle \frac{2d}{3+d}}$	D6	1

. From Table 5, only Refs. [4,19,22,23,24,25] and the I-QB converter meet the requirements of continuous input current and common ground attribute. Moreover, the converter in Ref. [25] and the I-QB converter can reduce the input current ripple.

Figure 5 compares the voltage gain (M represents voltage gain) of Refs. [4,19,22,23,24,25] and the I-QB converter. It can be seen from Figure 5 that the slope of voltage gain in Refs. [22,23,24] is large. Although high voltage gain can be obtained in theory, the control difficulty increases. When duty cycle d > 0.8, the voltage gain of Refs. [19,25] is lower than ten, and it is necessary to continue increasing the duty cycle to obtain the voltage gain, but with the increase of the voltage gain, the parasitic power losses will decrease the efficiency so that the theoretical high voltage gain cannot be obtained in practice. Therefore, only the I-QB converter and Ref. [4] can obtain more than 50 times voltage gains in practice. Meanwhile, it was observed that the duty cycle ranges in Refs. [22,23,24] are relatively narrow (0.5–0.75 for Ref. [22], and 0–0.5 for Refs. [23,24]), posing challenges for converter’s controller design. When input voltage varies over a wide range, an inadequately designed controller may cause significant overshoot in the output voltage.

Figure 6 shows the input current ripple rate curves of Refs. [4,19,22,23,24,25] and the I-QB converter. As shown in Figure 6, when d is in the range of 0.5–1 (under a high voltage gain), the input current ripple rate of the I-QB converter is the smallest (see Figure 6b). When the duty cycle d is around 0.6, the maximum input current ripple rate of the I-QB converter is about 0.0012R/L/f_s, thereby well suppressing the input current ripple, reducing the adverse effects on the FC lifespan.

Figure 7 shows the voltage stress versus duty cycle curve for the I-QB converter. As shown in Figure 7, only diode D₅ and capacitor C₄ experienced voltage stresses equal to the output voltage, while the voltage stresses on all other components remained below half the output voltage value. This ensures that the majority of devices in the I-QB converter operate under low voltage stress conditions. Under conditions where components experience low voltage stress, even with a slightly higher number of components, the power density of the converter may not decrease significantly.

5. Modeling and Controller Design

5.1. Small-Signal Modeling

To analyze the dynamic response of the I-QB converter, the small-signal model is derived. u_in(t) is defined as the input voltage variable, u_o(t) is the output voltage variable, d(t) is the control variable, and i_L1(t)–i_L4(t) and u_C1(t)–u_C4(t) are the state variables of L₁–L₄ and C₁–C₄, respectively.

According to Figure 4, the state equation operating in S₁S₂ = 11, S₁S₂ = 10, S₁S₂ = 01, and S₁S₂ = 00 can be obtained, as described in (33)–(36), respectively.

$$\left\{\begin{array}{l}\left[\begin{array}{l}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}4}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}4}(t)}{\mathrm{d}t}}\end{array}\right]=\left[\begin{array}{cccccccc}0& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& 0& 0& \frac{1}{L_2}& 0& 0& 0\\ 0& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0& \frac{1}{L_4}& 0& 0\\ 0& -\frac{1}{C_1}& 0& 0& 0& 0& 0& 0\\ 0& 0& 0& -\frac{1}{C_2}& 0& 0& 0& 0\\ 0& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0& 0& 0& -\frac{1}{C_{4}R}\end{array}\right]\left[\begin{array}{l}{i}_{\mathrm{L}1}(t)\\ i_{\mathrm{L}2}(t)\\ i_{\mathrm{L}3}(t)\\ i_{\mathrm{L}4}(t)\\ u_{\mathrm{C}1}(t)\\ u_{\mathrm{C}2}(t)\\ u_{\mathrm{C}3}(t)\\ u_{\mathrm{C}4}(t)\end{array}\right]+\left[\begin{array}{l}{\displaystyle \frac{1}{L_1}}\\ 0\\ {\displaystyle \frac{1}{L_1}}\\ 0\\ 0\\ 0\\ 0\\ 0\end{array}\right]u_{\mathrm{in}}(t)\\ u_{\mathrm{o}}(t)=\left[\begin{array}{cccccccc}0& 0& 0& 0& 0& 0& 0& 1\end{array}\right] {\left[\begin{array}{cccccccc}{i}_{\mathrm{L}1}(t)& i_{\mathrm{L}2}(t)& i_{\mathrm{L}3}(t)& i_{\mathrm{L}4}(t)& u_{\mathrm{C}1}(t)& u_{\mathrm{C}2}(t)& u_{\mathrm{C}3}(t)& u_{\mathrm{C}4}(t)\end{array}\right]}^{\mathrm{T}}\end{array}\right.$$

(33)

$$\left\{\begin{array}{l}\left[\begin{array}{l}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}4}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}4}(t)}{\mathrm{d}t}}\end{array}\right]=\left[\begin{array}{cccccccc}0& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& 0& 0& \frac{1}{L_2}& 0& 0& 0\\ 0& 0& 0& 0& 0& -\frac{1}{L_3}& 0& 0\\ 0& 0& 0& 0& 0& \frac{1}{L_4}& -\frac{1}{L_4}& 0\\ 0& -\frac{1}{C_1}& 0& 0& 0& 0& 0& 0\\ 0& 0& \frac{1}{C_2}& -\frac{1}{C_2}& 0& 0& 0& 0\\ 0& 0& 0& \frac{1}{C_3}& 0& 0& 0& 0\\ 0& 0& 0& 0& 0& 0& 0& -\frac{1}{C_{4}R}\end{array}\right]\left[\begin{array}{l}{i}_{\mathrm{L}1}(t)\\ i_{\mathrm{L}2}(t)\\ i_{\mathrm{L}3}(t)\\ i_{\mathrm{L}4}(t)\\ u_{\mathrm{C}1}(t)\\ u_{\mathrm{C}2}(t)\\ u_{\mathrm{C}3}(t)\\ u_{\mathrm{C}4}(t)\end{array}\right]+\left[\begin{array}{l}{\displaystyle \frac{1}{L_1}}\\ 0\\ {\displaystyle \frac{1}{L_3}}\\ 0\\ 0\\ 0\\ 0\\ 0\end{array}\right]u_{\mathrm{in}}(t)\\ u_{\mathrm{o}}(t)=\left[\begin{array}{cccccccc}0& 0& 0& 0& 0& 0& 0& 1\end{array}\right] {\left[\begin{array}{cccccccc}{i}_{\mathrm{L}1}(t)& i_{\mathrm{L}2}(t)& i_{\mathrm{L}3}(t)& i_{\mathrm{L}4}(t)& u_{\mathrm{C}1}(t)& u_{\mathrm{C}2}(t)& u_{\mathrm{C}3}(t)& u_{\mathrm{C}4}(t)\end{array}\right]}^{\mathrm{T}}\end{array}\right.$$

(34)

$$\left\{\begin{array}{l}\left[\begin{array}{l}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}4}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}4}(t)}{\mathrm{d}t}}\end{array}\right]=\left[\begin{array}{cccccccc}0& 0& 0& 0& -\frac{1}{L_1}& 0& 0& 0\\ 0& 0& 0& 0& \frac{1}{L_2}& 0& \frac{1}{L_2}& -\frac{1}{L_2}\\ 0& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0& \frac{1}{L_4}& 0& 0\\ \frac{1}{C_1}& -\frac{1}{C_1}& 0& 0& 0& 0& 0& 0\\ 0& 0& 0& -\frac{1}{C_2}& 0& 0& 0& 0\\ 0& -\frac{1}{C_3}& 0& 0& 0& 0& 0& 0\\ 0& \frac{1}{C_4}& 0& 0& 0& 0& 0& -\frac{1}{C_{4}R}\end{array}\right]\left[\begin{array}{l}{i}_{\mathrm{L}1}(t)\\ i_{\mathrm{L}2}(t)\\ i_{\mathrm{L}3}(t)\\ i_{\mathrm{L}4}(t)\\ u_{\mathrm{C}1}(t)\\ u_{\mathrm{C}2}(t)\\ u_{\mathrm{C}3}(t)\\ u_{\mathrm{C}4}(t)\end{array}\right]+\left[\begin{array}{l}{\displaystyle \frac{1}{L_1}}\\ 0\\ {\displaystyle \frac{1}{L_3}}\\ 0\\ 0\\ 0\\ 0\\ 0\end{array}\right]u_{\mathrm{in}}(t)\\ u_{\mathrm{o}}(t)=\left[\begin{array}{cccccccc}0& 0& 0& 0& 0& 0& 0& 1\end{array}\right] {\left[\begin{array}{cccccccc}{i}_{\mathrm{L}1}(t)& i_{\mathrm{L}2}(t)& i_{\mathrm{L}3}(t)& i_{\mathrm{L}4}(t)& u_{\mathrm{C}1}(t)& u_{\mathrm{C}2}(t)& u_{\mathrm{C}3}(t)& u_{\mathrm{C}4}(t)\end{array}\right]}^{\mathrm{T}}\end{array}\right.$$

(35)

$$\left\{\begin{array}{l}\left[\begin{array}{l}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}4}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}4}(t)}{\mathrm{d}t}}\end{array}\right]=\left[\begin{array}{cccccccc}0& 0& 0& 0& -\frac{1}{L_1}& 0& 0& 0\\ 0& 0& 0& 0& \frac{1}{L_2}& 0& \frac{1}{L_2}& -\frac{1}{L_2}\\ 0& 0& 0& 0& 0& -\frac{1}{L_3}& 0& 0\\ 0& 0& 0& 0& 0& \frac{1}{L_4}& 0& -\frac{1}{L_4}\\ \frac{1}{C_1}& -\frac{1}{C_1}& 0& 0& 0& 0& 0& 0\\ 0& 0& \frac{1}{C_2}& -\frac{1}{C_2}& 0& 0& 0& 0\\ 0& -\frac{1}{C_3}& 0& 0& 0& 0& 0& 0\\ 0& \frac{1}{C_4}& 0& \frac{1}{C_4}& 0& 0& 0& -\frac{1}{C_{4}R}\end{array}\right]\left[\begin{array}{l}{i}_{\mathrm{L}1}(t)\\ i_{\mathrm{L}2}(t)\\ i_{\mathrm{L}3}(t)\\ i_{\mathrm{L}4}(t)\\ u_{\mathrm{C}1}(t)\\ u_{\mathrm{C}2}(t)\\ u_{\mathrm{C}3}(t)\\ u_{\mathrm{C}4}(t)\end{array}\right]+\left[\begin{array}{l}{\displaystyle \frac{1}{L_1}}\\ 0\\ {\displaystyle \frac{1}{L_3}}\\ 0\\ 0\\ 0\\ 0\\ 0\end{array}\right]u_{\mathrm{in}}(t)\\ u_{\mathrm{o}}(t)=\left[\begin{array}{cccccccc}0& 0& 0& 0& 0& 0& 0& 1\end{array}\right] {\left[\begin{array}{cccccccc}{i}_{\mathrm{L}1}(t)& i_{\mathrm{L}2}(t)& i_{\mathrm{L}3}(t)& i_{\mathrm{L}4}(t)& u_{\mathrm{C}1}(t)& u_{\mathrm{C}2}(t)& u_{\mathrm{C}3}(t)& u_{\mathrm{C}4}(t)\end{array}\right]}^{\mathrm{T}}\end{array}\right.$$

(36)

Based on (4) and (12), combining (34)–(36) (i.e., S₁S₂ = 10, S₁S₂ = 01, and S₁S₂ = 00 states) obtains the state-space average equation for duty cycles between 0 and 0.5, as shown in (37). Similarly, based on (7) and (16), combining (33)–(35) (i.e., S₁S₂ = 11, S₁S₂ = 10, and S₁S₂ = 01 states) obtains the state-space average equation for duty cycles between 0.5 and 1, as shown in (38).

$$\left\{\begin{array}{l}\left[\begin{array}{l}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}4}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}4}(t)}{\mathrm{d}t}}\end{array}\right]=\left[\begin{array}{cccccccc}0& 0& 0& 0& -{\displaystyle \frac{1-d\left(t\right)}{L_2}}& 0& 0& 0\\ 0& 0& 0& 0& {\displaystyle \frac{1}{L_2}}& 0& {\displaystyle \frac{1-d\left(t\right)}{L_2}}& -{\displaystyle \frac{1-d\left(t\right)}{L_2}}\\ 0& 0& 0& 0& 0& -{\displaystyle \frac{1-d\left(t\right)}{L_3}}& 0& 0\\ 0& 0& 0& 0& 0& {\displaystyle \frac{1}{L_4}}& -{\displaystyle \frac{d\left(t\right)}{L_4}}& -{\displaystyle \frac{1-2d\left(t\right)}{L_4}}\\ {\displaystyle \frac{1-d\left(t\right)}{C_1}}& -{\displaystyle \frac{1}{C_1}}& 0& 0& 0& 0& 0& 0\\ 0& 0& {\displaystyle \frac{1-d\left(t\right)}{C_2}}& -{\displaystyle \frac{1}{C_2}}& 0& 0& 0& 0\\ 0& -{\displaystyle \frac{1-d\left(t\right)}{C_3}}& 0& -{\displaystyle \frac{d\left(t\right)}{C_3}}& 0& 0& 0& 0\\ 0& {\displaystyle \frac{1-d\left(t\right)}{C_4}}& 0& {\displaystyle \frac{1-2d\left(t\right)}{C_4}}& 0& 0& 0& -{\displaystyle \frac{1}{C_{4}R}}\end{array}\right]\left[\begin{array}{l}{i}_{\mathrm{L}1}(t)\\ i_{\mathrm{L}2}(t)\\ i_{\mathrm{L}3}(t)\\ i_{\mathrm{L}4}(t)\\ u_{\mathrm{C}1}(t)\\ u_{\mathrm{C}2}(t)\\ u_{\mathrm{C}3}(t)\\ u_{\mathrm{C}4}(t)\end{array}\right]+\left[\begin{array}{l}{\displaystyle \frac{1}{L_1}}\\ 0\\ {\displaystyle \frac{1}{L_3}}\\ 0\\ 0\\ 0\\ 0\\ 0\end{array}\right]u_{\mathrm{in}}(t)\\ u_{\mathrm{o}}(t)=\left[\begin{array}{cccccccc}0& 0& 0& 0& 0& 0& 0& 1\end{array}\right] {\left[\begin{array}{cccccccc}{i}_{\mathrm{L}1}(t)& i_{\mathrm{L}2}(t)& i_{\mathrm{L}3}(t)& i_{\mathrm{L}4}(t)& u_{\mathrm{C}1}(t)& u_{\mathrm{C}2}(t)& u_{\mathrm{C}3}(t)& u_{\mathrm{C}4}(t)\end{array}\right]}^{\mathrm{T}}\end{array}\right.$$

(37)

$$\left\{\begin{array}{l}\left[\begin{array}{l}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{i}_{\mathrm{L}4}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{u}_{\mathrm{C}4}(t)}{\mathrm{d}t}}\end{array}\right]=\left[\begin{array}{cccccccc}0& 0& 0& 0& -{\displaystyle \frac{1-d\left(t\right)}{L_2}}& 0& 0& 0\\ 0& 0& 0& 0& {\displaystyle \frac{1}{L_2}}& 0& {\displaystyle \frac{1-d\left(t\right)}{L_2}}& -{\displaystyle \frac{1-d\left(t\right)}{L_2}}\\ 0& 0& 0& 0& 0& -{\displaystyle \frac{1-d\left(t\right)}{L_3}}& 0& 0\\ 0& 0& 0& 0& 0& {\displaystyle \frac{1}{L_4}}& -{\displaystyle \frac{1-d\left(t\right)}{L_4}}& 0\\ {\displaystyle \frac{1-d\left(t\right)}{C_1}}& -{\displaystyle \frac{1}{C_1}}& 0& 0& 0& 0& 0& 0\\ 0& 0& {\displaystyle \frac{1-d\left(t\right)}{C_2}}& -{\displaystyle \frac{1}{C_2}}& 0& 0& 0& 0\\ 0& -{\displaystyle \frac{1-d\left(t\right)}{C_3}}& 0& {\displaystyle \frac{1-d\left(t\right)}{C_3}}& 0& 0& 0& 0\\ 0& {\displaystyle \frac{1-d\left(t\right)}{C_4}}& 0& 0& 0& 0& 0& -{\displaystyle \frac{1}{C_{4}R}}\end{array}\right]\left[\begin{array}{l}{i}_{\mathrm{L}1}(t)\\ i_{\mathrm{L}2}(t)\\ i_{\mathrm{L}3}(t)\\ i_{\mathrm{L}4}(t)\\ u_{\mathrm{C}1}(t)\\ u_{\mathrm{C}2}(t)\\ u_{\mathrm{C}3}(t)\\ u_{\mathrm{C}4}(t)\end{array}\right]+\left[\begin{array}{l}{\displaystyle \frac{1}{L_1}}\\ 0\\ {\displaystyle \frac{1}{L_3}}\\ 0\\ 0\\ 0\\ 0\\ 0\end{array}\right]u_{\mathrm{in}}(t)\\ u_{\mathrm{o}}(t)=\left[\begin{array}{cccccccc}0& 0& 0& 0& 0& 0& 0& 1\end{array}\right] {\left[\begin{array}{cccccccc}{i}_{\mathrm{L}1}(t)& i_{\mathrm{L}2}(t)& i_{\mathrm{L}3}(t)& i_{\mathrm{L}4}(t)& u_{\mathrm{C}1}(t)& u_{\mathrm{C}2}(t)& u_{\mathrm{C}3}(t)& u_{\mathrm{C}4}(t)\end{array}\right]}^{\mathrm{T}}\end{array}\right.$$

(38)

The state variables, input variable, output variable, and control variable can be described by introducing small-signal disturbance variables, which can be given in (39), where I_L1–I_L4, U_C1–U_C4, U_in, U_o, and d are the steady-state components. ${\widehat{i}}_{L1}\left(t\right)$–${\widehat{i}}_{L4}\left(t\right)$, ${\widehat{u}}_{\mathrm{C}1}\left(t\right)$–${\widehat{u}}_{\mathrm{C}4}\left(t\right)$, ${\widehat{u}}_{\mathrm{in}}\left(t\right)$, ${\widehat{u}}_{\mathrm{o}}\left(t\right)$, and ${\widehat{d}}_{\mathrm{o}}\left(t\right)$ are the small-signal disturbance variables.

$$\left\{\begin{array}{l}{i}_{\mathrm{L}1}(t)=I_{\mathrm{L}1}+{\widehat{i}}_{\mathrm{L}1}(t)\\ i_{\mathrm{L}2}(t)=I_{\mathrm{L}2}+{\widehat{i}}_{\mathrm{L}2}(t)\\ i_{\mathrm{L}3}(t)=I_{\mathrm{L}3}+{\widehat{i}}_{\mathrm{L}3}(t)\\ i_{\mathrm{L}4}(t)=I_{\mathrm{L}4}+{\widehat{i}}_{\mathrm{L}4}(t)\\ u_{\mathrm{C}1}(t)=U_{\mathrm{C}1}+{\widehat{u}}_{\mathrm{C}1}(t)\\ u_{\mathrm{C}2}(t)=U_{\mathrm{C}2}+{\widehat{u}}_{\mathrm{C}2}(t)\\ u_{\mathrm{C}3}(t)=U_{\mathrm{C}3}+{\widehat{u}}_{\mathrm{C}3}(t)\\ u_{\mathrm{C}4}(t)=U_{\mathrm{C}4}+{\widehat{u}}_{\mathrm{C}4}(t)\\ u_{\mathrm{in}}(t)=U_{\mathrm{in}}+{\widehat{u}}_{\mathrm{in}}(t)\\ u_{\mathrm{o}}(t)=U_{\mathrm{o}}+{\widehat{u}}_{\mathrm{o}}(t)\\ d(t)=d+\widehat{d}(t)\end{array}\right. \mathrm{and} \left\{\begin{array}{l}{\widehat{i}}_{\mathrm{L}1}(t)<<I_{\mathrm{L}1}\\ {\widehat{i}}_{\mathrm{L}2}(t)<<I_{\mathrm{L}2}\\ {\widehat{i}}_{\mathrm{L}3}(t)<<I_{\mathrm{L}3}\\ {\widehat{i}}_{\mathrm{L}4}(t)<<I_{\mathrm{L}4}\\ {\widehat{u}}_{\mathrm{C}1}(t)<<U_{\mathrm{C}1}\\ {\widehat{u}}_{\mathrm{C}2}(t)<<U_{\mathrm{C}2}\\ {\widehat{u}}_{\mathrm{C}3}(t)<<U_{\mathrm{C}3}\\ {\widehat{u}}_{\mathrm{C}4}(t)<<U_{\mathrm{C}4}\\ {\widehat{u}}_{\mathrm{in}}(t)<<U_{\mathrm{in}}\\ {\widehat{u}}_{\mathrm{o}}(t)<<U_{\mathrm{o}}\\ \widehat{d}(t)<<d\end{array}\right.$$

(39)

By substituting (39) into (37) or (38), separating the disturbance signals, and ignoring the second-order infinitesimals, the small-signal models with duty d < 0.5 and d $\ge$ 0.5 can be obtained, as shown in (40)–(41), respectively.

$$\left\{\begin{array}{l}\left[\begin{array}{l}{\displaystyle \frac{\mathrm{d}{\widehat{i}}_{\mathrm{L}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{i}}_{\mathrm{L}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{i}}_{\mathrm{L}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{i}}_{\mathrm{L}4}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{u}}_{\mathrm{C}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{u}}_{\mathrm{C}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{u}}_{\mathrm{C}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{u}}_{\mathrm{C}4}(t)}{\mathrm{d}t}}\end{array}\right]=\left[\begin{array}{cccccccc}0& 0& 0& 0& -{\displaystyle \frac{1-d}{L_1}}& 0& 0& 0\\ 0& 0& 0& 0& {\displaystyle \frac{1}{L_2}}& 0& {\displaystyle \frac{1-d}{L_2}}& -{\displaystyle \frac{1-d}{L_2}}\\ 0& 0& 0& 0& 0& -{\displaystyle \frac{1-d}{L_3}}& 0& 0\\ 0& 0& 0& 0& 0& {\displaystyle \frac{1}{L_4}}& -{\displaystyle \frac{d}{L_4}}& -{\displaystyle \frac{1-2d}{L_4}}\\ {\displaystyle \frac{1-d}{C_1}}& -{\displaystyle \frac{1}{C_1}}& 0& 0& 0& 0& 0& 0\\ 0& 0& {\displaystyle \frac{1-d}{C_2}}& -{\displaystyle \frac{1}{C_2}}& 0& 0& 0& 0\\ 0& -{\displaystyle \frac{1-d}{C_3}}& 0& {\displaystyle \frac{d}{C_3}}& 0& 0& 0& 0\\ 0& {\displaystyle \frac{1-d}{C_4}}& 0& {\displaystyle \frac{1-2d}{C_4}}& 0& 0& 0& -{\displaystyle \frac{1}{C_{4}R}}\end{array}\right]\left[\begin{array}{l}{\widehat{i}}_{\mathrm{L}1}(t)\\ {\widehat{i}}_{\mathrm{L}2}(t)\\ {\widehat{i}}_{\mathrm{L}3}(t)\\ {\widehat{i}}_{\mathrm{L}4}(t)\\ {\widehat{u}}_{\mathrm{C}1}(t)\\ {\widehat{u}}_{\mathrm{C}2}(t)\\ {\widehat{u}}_{\mathrm{C}3}(t)\\ {\widehat{u}}_{\mathrm{C}4}(t)\end{array}\right]+\left[\begin{array}{l}{\displaystyle \frac{1}{L_1}}\\ 0\\ {\displaystyle \frac{1}{L_3}}\\ 0\\ 0\\ 0\\ 0\\ 0\end{array}\right]{\widehat{u}}_{\mathrm{in}}(t)+\left[\begin{array}{cccccccc}0& 0& 0& 0& {\displaystyle \frac{1}{L_1}}& 0& 0& 0\\ 0& 0& 0& 0& 0& 0& -{\displaystyle \frac{1}{L_2}}& {\displaystyle \frac{1}{L_2}}\\ 0& 0& 0& 0& 0& {\displaystyle \frac{1}{L_3}}& 0& 0\\ 0& 0& 0& 0& 0& 0& -{\displaystyle \frac{1}{L_4}}& {\displaystyle \frac{2}{L_4}}\\ -{\displaystyle \frac{1}{C_1}}& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& -{\displaystyle \frac{1}{C_2}}& 0& 0& 0& 0& 0\\ 0& {\displaystyle \frac{1}{C_3}}& 0& {\displaystyle \frac{1}{C_3}}& 0& 0& 0& 0\\ 0& -{\displaystyle \frac{1}{C_4}}& 0& -{\displaystyle \frac{2}{C_4}}& 0& 0& 0& 0\end{array}\right]\left[\begin{array}{l}{I}_{\mathrm{L}1}\\ I_{\mathrm{L}2}\\ I_{\mathrm{L}3}\\ I_{\mathrm{L}4}\\ U_{\mathrm{C}1}\\ U_{\mathrm{C}2}\\ U_{\mathrm{C}3}\\ U_{\mathrm{C}4}\end{array}\right]\\ {\widehat{u}}_{\mathrm{o}}(t)=\left[\begin{array}{cccccccc}0& 0& 0& 0& 0& 0& 0& 1\end{array}\right] {\left[\begin{array}{cccccccc}{\widehat{i}}_{\mathrm{L}1}(t)& {\widehat{i}}_{\mathrm{L}2}(t)& {\widehat{i}}_{\mathrm{L}3}(t)& {\widehat{i}}_{\mathrm{L}4}(t)& {\widehat{u}}_{\mathrm{C}1}(t)& {\widehat{u}}_{\mathrm{C}2}(t)& {\widehat{u}}_{\mathrm{C}3}(t)& {\widehat{u}}_{\mathrm{C}4}(t)\end{array}\right]}^{\mathrm{T}}\end{array}\right.\widehat{d}\left(t\right)$$

(40)

$$\left\{\begin{array}{l}\left[\begin{array}{l}{\displaystyle \frac{\mathrm{d}{\widehat{i}}_{\mathrm{L}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{i}}_{\mathrm{L}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{i}}_{\mathrm{L}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{i}}_{\mathrm{L}4}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{u}}_{\mathrm{C}1}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{u}}_{\mathrm{C}2}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{u}}_{\mathrm{C}3}(t)}{\mathrm{d}t}}\\ {\displaystyle \frac{\mathrm{d}{\widehat{u}}_{\mathrm{C}4}(t)}{\mathrm{d}t}}\end{array}\right]=\left[\begin{array}{cccccccc}0& 0& 0& 0& -{\displaystyle \frac{1-d}{L_1}}& 0& 0& 0\\ 0& 0& 0& 0& {\displaystyle \frac{1}{L_2}}& 0& {\displaystyle \frac{1-d}{L_2}}& -{\displaystyle \frac{1-d}{L_2}}\\ 0& 0& 0& 0& 0& -{\displaystyle \frac{1-d}{L_3}}& 0& 0\\ 0& 0& 0& 0& 0& {\displaystyle \frac{1}{L_4}}& -{\displaystyle \frac{1-d}{L_4}}& 0\\ {\displaystyle \frac{1-d}{C_1}}& -{\displaystyle \frac{1}{C_1}}& 0& 0& 0& 0& 0& 0\\ 0& 0& {\displaystyle \frac{1-d}{C_2}}& -{\displaystyle \frac{1}{C_2}}& 0& 0& 0& 0\\ 0& -{\displaystyle \frac{1-d}{C_3}}& 0& {\displaystyle \frac{1-d}{C_3}}& 0& 0& 0& 0\\ 0& {\displaystyle \frac{1-d}{C_4}}& 0& 0& 0& 0& 0& -{\displaystyle \frac{1}{C_{4}R}}\end{array}\right]\left[\begin{array}{l}{\widehat{i}}_{\mathrm{L}1}(t)\\ {\widehat{i}}_{\mathrm{L}2}(t)\\ {\widehat{i}}_{\mathrm{L}3}(t)\\ {\widehat{i}}_{\mathrm{L}4}(t)\\ {\widehat{u}}_{\mathrm{C}1}(t)\\ {\widehat{u}}_{\mathrm{C}2}(t)\\ {\widehat{u}}_{\mathrm{C}3}(t)\\ {\widehat{u}}_{\mathrm{C}4}(t)\end{array}\right]+\left[\begin{array}{l}{\displaystyle \frac{1}{L_1}}\\ 0\\ {\displaystyle \frac{1}{L_3}}\\ 0\\ 0\\ 0\\ 0\\ 0\end{array}\right]{\widehat{u}}_{\mathrm{in}}(t)+\left[\begin{array}{cccccccc}0& 0& 0& 0& {\displaystyle \frac{1}{L_1}}& 0& 0& 0\\ 0& 0& 0& 0& 0& 0& -{\displaystyle \frac{1}{L_2}}& {\displaystyle \frac{1}{L_2}}\\ 0& 0& 0& 0& 0& {\displaystyle \frac{1}{L_3}}& 0& 0\\ 0& 0& 0& 0& 0& 0& {\displaystyle \frac{1}{L_4}}& 0\\ -{\displaystyle \frac{1}{C_1}}& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& -{\displaystyle \frac{1}{C_2}}& 0& 0& 0& 0& 0\\ 0& {\displaystyle \frac{1}{C_3}}& 0& -{\displaystyle \frac{1}{C_3}}& 0& 0& 0& 0\\ 0& -{\displaystyle \frac{1}{C_4}}& 0& 0& 0& 0& 0& 0\end{array}\right]\left[\begin{array}{l}{I}_{\mathrm{L}1}\\ I_{\mathrm{L}2}\\ I_{\mathrm{L}3}\\ I_{\mathrm{L}4}\\ U_{\mathrm{C}1}\\ U_{\mathrm{C}2}\\ U_{\mathrm{C}3}\\ U_{\mathrm{C}4}\end{array}\right]\\ {\widehat{u}}_{\mathrm{o}}(t)=\left[\begin{array}{cccccccc}0& 0& 0& 0& 0& 0& 0& 1\end{array}\right] {\left[\begin{array}{cccccccc}{\widehat{i}}_{\mathrm{L}1}(t)& {\widehat{i}}_{\mathrm{L}2}(t)& {\widehat{i}}_{\mathrm{L}3}(t)& {\widehat{i}}_{\mathrm{L}4}(t)& {\widehat{u}}_{\mathrm{C}1}(t)& {\widehat{u}}_{\mathrm{C}2}(t)& {\widehat{u}}_{\mathrm{C}3}(t)& {\widehat{u}}_{\mathrm{C}4}(t)\end{array}\right]}^{\mathrm{T}}\end{array}\right.\widehat{d}\left(t\right)$$

(41)

5.2. Controller Design

Using the small-signal model of the I-QB converter, the transfer function from the duty cycle to output voltage can be derived. When the input voltage is 60 V, the transfer function is given by (42), with the calculation parameters listed in

Table 6. Experimental parameters.

Parameters and Devices	Models and Values
Input Voltage Uin	30–80 V
Duty Cycle Range	0.356–0.553
Output Voltage Uo	300 V
Voltage Gain M	3.75–10
Rated Power PO	200 W
Rated Load R	450 Ω
Switching Frequency fs	100 kHz
Switches S1, S2	ST SCTWA50N120 (SiC)
Diodes D1–D6	CREE C4D30120D (SiC)
Capacitors C1, C2	680 µF/450 V
Capacitors C3, C4	390 µF/220 µF/900 V
Inductors L1–L4	300 µH/20 A

. To simplify analysis, the original transfer function in (42) is reduced from eight to four order to obtain the simplified transfer function in (43). By the appropriate pole-zero elimination method, the (s² + 2.232s + 7.414 × 10⁵) and (s² + 6.226s + 1.157 × 10⁷) in the numerator and the (s² + 2.642s + 9.961 × 10⁵) and (s² + 3.391s + 1.375 × 10⁷) in the denominator are eliminated in (42). The BODE diagram curves of (42) and (43) are shown in Figure 8a. Similarly, when the input voltage is 30 V, the simplified transfer function after order reduction can also be obtained using the zero-pole elimination method, as shown in (44). From Figure 8, it can be seen that the original and simplified curves are approximately the same. However, both the phase margin and magnitude margin of the I-QB converter are negative, indicating the system’s instability. Therefore, a closed-loop controller must be designed to ensure the system’s stability. This paper uses a PI controller, which is designed based on (45).

$$G_{d\to U\mathrm{o},60\mathrm{V}}(s)={\left.{\displaystyle \frac{{\widehat{u}}_{\mathrm{o}}(s)}{\widehat{d}(s)}}\right|}_{{\widehat{u}}_{\mathrm{in}}(s)=0}={\displaystyle \frac{-14045(s-1.979\times {10}^5)(s^2+2.232s+7.414\times {10}^5)(s^2-22.77s+2.754\times {10}^6)(s^2+6.226s+1.157\times {10}^7)}{(s^2+3.287s+3.872\times {10}^5)(s^2+2.642s+9.961\times {10}^5)(s^2+0.7809s+8.051\times {10}^6)(s^2+3.391s+1.375\times {10}^7)}}$$

(42)

$${G^{\prime }}_{d\to U\mathrm{o},60\mathrm{V}}(s)={\left.{\displaystyle \frac{{\widehat{u}}_{\mathrm{o}}(s)}{\widehat{d}(s)}}\right|}_{{\widehat{u}}_{\mathrm{in}}(s)=0}={\displaystyle \frac{-14045(s-1.979\times {10}^5)(s^2-22.77s+2.754\times {10}^6)}{(s^2+3.287s+3.872\times {10}^5)(s^2+0.7809s+8.051\times {10}^6)}}$$

(43)

$${G^{\prime }}_{d\to U\mathrm{o},30\mathrm{V}}(s)={\left.{\displaystyle \frac{{\widehat{u}}_{\mathrm{o}}(s)}{\widehat{d}(s)}}\right|}_{{\widehat{u}}_{\mathrm{in}}(s)=0}={\displaystyle \frac{-6772.7(s-1.499\times {10}^5)(s^2-58.91s+1.96\times {10}^6)}{(s^2+4.809s+1.377\times {10}^5)(s^2+2.226s+1.089\times {10}^7)}}$$

(44)

$$G_{\mathrm{PI}}(s)=K_{\mathrm{P}}+{\displaystyle \frac{K_{\mathrm{I}}}{s}}$$

(45)

where the K_P is the proportional coefficient and K_I is the integral coefficient.

The block diagram of the closed-loop system is shown in Figure 9. G_FB(s) is the feedback transfer function. The prototype adopts the Hall sensor to collect the output voltage U_o, and the feedback transfer function is G_FB(s) = 1/200. G_d→Uo(s) is the transfer function of the I-QB from control to output. G_PI(s) is the transfer function of the designed PI controller.

In this work, K_p = 0.0000105 and K_I = 0.0003. When the input voltage is 60 V, the Bode diagram of closed-loop system is shown in Figure 10a. The phase margin and magnitude margin of the closed-loop system are 55.6° and 21.8 dB, respectively, indicating that the system is stable. When the input voltage is 30 V, the Bode diagram of the closed-loop system is shown in Figure 10b. The phase margin and gain margin of the closed-loop system is 25.6° and 13.1 dB, respectively. As indicated by the Bode diagram, although the converter system remains stable after the operating point shift, its control performance degrades and only marginally meets the basic requirements for passenger FCV applications. This limitation arises because fixed-parameter PI controllers struggle to achieve optimal performance simultaneously across the different operating points of the converter. Therefore, future research should explore control strategies that are insensitive to controlled converters, such as sliding mode control or hybrid control strategies, etc. [29,30].

6. Experiments

Wide-bandgap devices such as SiC and GaN offer high breakdown voltage, fast switching speed, and low losses, making them well-suited for achieving high-frequency and high-efficiency converter operation. To validate the performance of the I-QB converter, a scaled-down prototype based on SiC devices was developed and tested, demonstrating its steady-state and dynamic characteristics.

6.1. Parameters Selection

To ensure that the I-QB converter operates in the CCM condition, the values of inductors L₁, L₂, L₃, and L₄ should be designed to satisfy (46)–(48).

$$L=U_L{\displaystyle \frac{dt}{d{I}_L}}$$

(46)

$$\left\{\begin{array}{l}{L}_1={\displaystyle \frac{{(1-d)}^{6}R}{2f_s}}, L_2={\displaystyle \frac{{(1-d)}^{4}R}{2f_s}}\\ L_3={\displaystyle \frac{d{(1-d)}^{5}R}{2f_s}}, L_4={\displaystyle \frac{d{(1-d)}^{3}R}{2f_s}}\end{array}\right.; 0<d<0.5$$

(47)

$$\left\{\begin{array}{l}{L}_1=L_3\ge {\displaystyle \frac{Rd{(1-d)}^4}{4f_s}}\\ L_2=L_4\ge {\displaystyle \frac{Rd{(1-d)}^2}{4f_s}}\end{array}\right.; 0.5<d<1$$

(48)

where L is the inductance, dt = d/f_s, and dI_L = ΔI_L. According to Table 3 and Table 4 and (49), the calculation of all capacitors in the I-QB converter can be obtained in (50) and (51).

$$C=I_{\mathrm{C}}{\displaystyle \frac{dt}{d{U}_{\mathrm{C}}}}$$

(49)

$$\left\{\begin{array}{l}{C}_1\ge {\displaystyle \frac{d^2{I}_o}{{(1-d)}^2\Delta U_{C1}{f}_s}}\\ C_2=C_3\ge {\displaystyle \frac{d{I}_o}{(1-d)\Delta U_{C2/C3}{f}_s}}; 0<d<0.5\\ C_4\ge {\displaystyle \frac{d{I}_o}{\Delta U_{C4}{f}_s}}\end{array}\right.$$

(50)

$$\left\{\begin{array}{l}{C}_1=C_2\ge {\displaystyle \frac{d{I}_o}{(1-d)\Delta U_{C1}{f}_s}}\\ C_3\ge {\displaystyle \frac{I_o}{\Delta U_{C3}{f}_s}}\\ C_4\ge {\displaystyle \frac{d{I}_o}{\Delta U_{C4}{f}_s}}\end{array}\right.; 0.5<d<1$$

(51)

where C is the capacitance, dt = d/f_s, and dU_C = ΔU_C. The voltage fluctuations in capacitors C₁–C₄ are ΔU_C1, ΔU_C2, ΔU_C3, and ΔU_C4, respectively.

Incorporating the parameters in Table 1 and Table 3 and Equations (47), (48), (50) and (51), it can be obtained that the critical values of inductors in the five times voltage step-up state are L₁ = 90.2 μH, L₂ = 263.5 μH, L₃ = 63.9 μH, and L₄ = 186.9 μH. When the ripples of voltage are 0.02 V, the values of capacitors are C₁ = 167.8 μF, C₂ = 236.5 μF, C₃ = 236.5 μF, and C₄ = 138.3 μF. Incorporating the parameters in Table 2 and Table 4 and Equations (47), (48), (50) and (51), it can be obtained that the critical values of inductors in the ten times voltage step-up state are L₁ = 24.8 μH, L₂ = 124.3 μH, L₃ = 24.8 μH, and L₄ = 124.3 μH. When the ripples of voltage are 0.02 V, the values of capacitors are C₁ = 412.5 μF, C₂ = 412.5 μF, C₃ = 333.5 μF, and C₄ = 184.5 μF. To ensure that the I-QB converter consistently operates in CCM, and considering that the sum of the currents through L₁ and L₃ equals the input current, the following values are selected to further reduce the input current ripple while maintaining a sufficient margin: L₁–L₄ = 300 μH, C₁–C₂ = 680 μF, C₃ = 390μF, and C₄ = 220μF. Based on the analysis in Table 1, Table 2, Table 3 and Table 4 and Section 3.4 and Section 3.5, the switches and diodes are selected as SCTWA50N120 and C4D30120D, respectively. The parameters of the experimental platform are listed in Table 6, the SiC-based prototype of the I-QB converter is shown in Figure 11a, and the test platform is shown in Figure 11b. The controller chip utilizes TI’s TMS320F28335, and the voltage sampling circuit adopts the Hall sensor. The driving circuit adopts ADuM1200 and IXDD609 to realize galvanic isolation and high-frequency drive, respectively.

6.2. Steady-State Performance

When the U_in is 60 V and the reference voltage U_ref of the closed-loop system is 300 V, the converter works in a low voltage conversion ratio (ie. d < 0.5 and M = 5). The results are recorded in Figure 12. From Figure 12, it can be seen that the switching frequency f_s is 100 kHz and the duty cycle d is 0.43 (due to the parasitic parameters, it is slightly greater than 0.415). The inductor average currents are I_L1 = 1.4 A, I_L2 = 0.9 A, I_L3 = 2.0 A, I_L4 = 1.2 A, and I_in = 3.4 A, respectively, which are largely in agreement with the theoretical predictions. The U_o of the I-QB converter stabilizes at the U_ref of 300 V. The voltage stresses of power switches S₁–S₂, diodes D₁–D₆, and capacitors C₁–C₄ are shown in Figure 12a–g, which are basically consistent with the theoretical prediction and verify the correctness of the topology analysis. As shown in Figure 12f,g, the I-QB converter operates in an interleaved mode, and the current ripples of inductor L₁ and L₃ are compensating each other, resulting in a low ripple of the input current I_in, which is only 0.3 A.

When the U_in is 30 V and the U_ref of the closed-loop system is 300 V, the converter works in a high voltage conversion ratio (ie. d > 0.5 and M = 10). The waveforms are recorded in Figure 13 where the f_s is 100 kHz and the d is 0.58 (due to the parasitic parameters, it is slightly greater than 0.553). The inductor average currents are I_L1 = 3.5 A, I_L2 = 1.5 A, I_L3 = 3.5 A, I_L4 = 1.5 A, and I_in = 7 A, respectively, which verify the theoretical analysis. The U_o of the I-QB converter stabilizes at the U_ref of 300 V. The voltage stresses of switches S₁–S₂, diodes D₁–D₆, and capacitors C₁–C₄ are shown in Figure 13a–g, which are largely in agreement with the theoretical predictions and verify the correctness of the topology analysis. As shown in Figure 13f,g, the I-QB converter operates in an interleaved mode, and the current ripples of inductor L₁ and L₃ are compensated by each other, resulting in no significant input current ripple being observed.

6.3. Dynamic Performance Analysis

To verify the dynamic performance of the I-QB converter and simulate extreme FC voltage drop conditions, experiments with the I-QB converter under the input voltage step change are conducted. When the U_ref is set as 300 V and the rated power P_o is 200 W, we change the U_in between 50 V and 80 V. The waveforms are recorded in Figure 14. From Figure 14, when the U_in step changes in a wide range, the overshoot of U_o is less than 50 V, and the voltage can stabilize within 200 ms.

The settling time is influenced by the following factors. (1) Control bandwidth limitation: From Figure 10, the system’s control bandwidth is approximately 60 Hz. Due to the inverse relationship between settling time and control bandwidth, the inherent response speed is restricted. Although a higher bandwidth could shorten the settling time, it might compromise the system’s stability. This conflicts with the requirement for the converter to operate over a wide input voltage range, as changing the operating point already causes a reduction in the system’s stability margin. Moreover, non-ideal factors such as LC filtering, sampling, and PWM delays further prolong the settling time. (2) Passive component sizing: As mentioned in Section 6.1, the values of the inductors and capacitors are larger than their theoretical critical values. This is primarily to ensure that the converter operates in CCM and to minimize input current ripple. While these larger component values effectively suppress ripple, they inherently introduce larger time constants, further limiting the bandwidth, consequently leading to a longer settling time. (3) Experimental setup constraints: To ensure stable operation under all working conditions and maintain the anti-interference ability, the bandwidth cannot be designed too high, which objectively limits the dynamic response speed.

Since FCs primarily deliver average power while instantaneous power is supplied and recovered by the power battery (as shown in Figure 1), a settling time of 200 ms is acceptable for the DC/DC converter, as any resulting bus voltage overshoot can be offset by the power battery. Moreover, the experimental conditions for the input voltage step test are more stringent than the actual output characteristics of an FC. When the output voltage of an FC decreases slowly as the input current increases, the converter is expected to achieve an even better dynamic performance.

To verify the dynamic performance of the I-QB converter under sudden steps in vehicle driving conditions (load steps), we set the P_o to 200 W and the output resistor step change between 450 Ω and 900 Ω. The waveforms are recorded in Figure 15. From Figure 15, it can be seen that when the load steps are between 100% and 50%, the U_o has no obvious fluctuation. Thus, it is verified that the I-QB converter has a good dynamic response.

6.4. Efficiency Testing

The efficiency curves of this prototype are experimentally derived and shown in Figure 16. The P_o is 100 W, 200 W and 300 W, the U_in increases from 30 V to 80 V, the U_ref is set to 300 V, and the f_s is 100 kHz or 200 kHz.

Figure 16 shows that the theoretical and experimental results have good consistency, with the theoretical efficiency values slightly higher than the measured efficiency values. The maximum measured efficiency reaches 96.2%, occurring when the U_in is 80 V and the P_o is 100 W. At the rated power of 200 W, the maximum measured efficiency is 94.2%. At a power of 300 W, the maximum measured efficiency further decreased to 91.9%. The efficiency decreases when the U_in drops at a constant output power, as the resulting increase in the I_in leads to higher losses. Similarly, with the U_in fixed, raising P_o raises the I_in and consequently reduces efficiency. The peak efficiency of 92.1% occurs at P_o = 200 W and f_s = 200 kHz. For a constant P_o, the efficiency declines with a rising f_s due to greater switching losses from more frequent switching events. The experimental results validate that the overall efficiency of the I-QB converter is relatively high, and the energy loss of FCV powertrains can be potentially reduced by employing the I-QB converter.

It is worth noting that efficiency is correlated with factors such as the switching frequency, rated power, stress, component count, and device materials, etc. The 94.2% efficiency achieved in this SiC-based prototype cannot be regarded as extremely high efficiency. However, considering the component count, existing experimental conditions, PCB fabrication constraints, and other design requirements that the converter must balance, this efficiency level is satisfactory. For future researchers aiming to further improve efficiency, measures such as soft switching technology, synchronous rectification technology, optimized PCB layout, and EMI suppression could be considered. However, these aspects are not the primary focus of this study, as this prototype is intended solely to validate the feasibility and effectiveness of the I-QB converter.

6.5. Loss Analysis

Based on the parameters in Table 6, with V_F = 1.4 V, R_{ESR_C} = 0.02 Ω, r_L = 0.01 Ω, r_S = 0.021 Ω, the calculated loss distributions under U_in = 30 V/60 V, U_o = 200 V, f_s = 100 kHz and P_o = 200 W are shown in Figure 17. The results in Figure 17 indicate that the switching losses of switches and diode losses account for a substantial portion of the total losses. The proportion of switching loss increases with the increasing device stress. The conduction loss of the diodes increases with higher duty cycles, because the V_F is almost constant in a wide current range, and the conduction loss is determined by the diode’s current.

To further demonstrate the consistency between theory and experiment, this paper directly compares the theoretical and experimental values of the voltage gain, input current ripple, and efficiency, as shown in

Table 7. Comparison of theoretical and experimental values for voltage gain, input current ripple, and efficiency.

Indicator			Theoretical Value	Experimental Value	Error Value
Voltage Gain	60 V to 300 V		5	4.75	0.25
	30 V to 300 V		10	9.43	0.57
Input Current Ripple	M = 5 (60 V to 300 V)		0.24	0.3 A	0.06 A
	M = 10 (30 V to 300 V)		0.1	Not observed	/
Efficiency	Po = 100 W, fs = 100 kHz	M = 5	97.0%	95.6%	1.4%
		M = 10	95.8%	93.0%	2.8%
	Po = 200 W, fs = 100 kHz	M = 5	95.5%	93.7%	1.8%
		M = 10	92.8%	92.2%	0.6%
	Po = 300 W, fs = 100 kHz	M = 5	94.0%	92%	2%
		M = 10	89.4%	88.6%	0.8%
	Po = 200 W, fs = 200 kHz	M = 5	92.9%	91.2%	0.7%
		M = 10	89.1%	88.7%	0.4%

. From Table 7, the theoretical and experimental values exhibit good consistency. The errors are all within an acceptable range. Several reasons explain the errors between theoretical and experimental values. (1) The effects of parasitic parameters are neglected when calculating the voltage gain and input current ripple. (2) Although parasitic parameters are considered in the loss analysis, only average values are used, and the impact of devices’ temperature rise is not included in the calculations. (3) It is challenging to incorporate the effects of EMI on the converter during calculations. (4) Inevitable measurement noise and instrument errors affect the experimental results.

6.6. Discussion

It should be further clarified that the rated power of the experimental prototype in this paper is 200 W, which is relatively low compared to the kilowatt-level power (e.g., 50 kW) required for practical passenger FCVs powertrains. This prototype is intentionally designed as a scaled-down concept validation, aimed to verify the operating principles and control strategy of the I-QB converter under safe and cost-controllable conditions. The primary contribution of this work lies in demonstrating its functionality and feasibility, rather than immediately achieving full-power operation.

The proposed topologies can be adapted to higher power levels through two main engineering approaches. First, by employing SiC power modules with higher rated power (e.g., Cree EDB003M06TM3, Cree CAB500M17HM3) and optimizing magnetic components (e.g., using nanocrystalline ring magnetic core), along with corresponding thermal management upgrades—such as replacing the passive air cooling system with a forced liquid cooling system that meets automotive industry standards. Second, the modular attribute of these topologies supports power scaling by interleaving or directly paralleling multiple converter units. These strategies not only increase the total power capacity but also offer additional advantages such as a reduced input current ripple and enhanced system fault tolerance. Although these scaling pathways are conceptually sound and based on mature industrial practices, their experimental validation at kilowatt power levels remains a key direction for future work.

7. Conclusions

To address the voltage matching issue between the FC stack and the vehicle’s DC bus in passenger FCVs, this paper proposes three high-gain DC/DC converters based on an interleaved structure, integrated with the quadratic Boost, quasi-Z source, switched-inductor impedance networks, and named I-QB, I-QZS, and I-SI respectively. Meanwhile, taking the I-QB converter as an example, a scaled-down experimental platform is constructed based on steady-state analysis and comparisons. Steady-state experimental results demonstrate that the waveforms closely align with theoretical analysis, validating the feasibility of these converters and correctness of the steady-state analysis. The dynamic response results indicate that the I-QB converter exhibits an excellent dynamic performance under step changes in input voltage and load, with a maximum voltage overshoot of less than 50 V and a settling time of within 200 ms. The peak measured efficiency of this SiC-based prototype at rated power is 94.2%. These test results further demonstrate that all three converters can balance the “six requirements” for DC/DC converter design in passenger FCV scenarios, offering the following merits:

(1)

Up to 50 times voltage gain in theory (d = 0.8);

(2)

Experimentally verified 30–80 V input voltage range;

(3)

Input current ripple rate less than 0.05 × R/L/f_s;

(4)

Voltage stress of the S₁–S₂, C₁–C₃, and D₁–D₄, D₆: ≤0.5 times output voltage;

(5)

Common ground of input–output;

(6)

94.2% measured efficiency at rated conditions.

In conclusion, the proposed DC/DC converters are well-suited for passenger FCV scenarios.