Current Estimator LESO-Based Discrete-Time LADRC of a DC-DC Buck Converter

Abstract

This study proposes a systematic approach for implementing discrete-time Linear Active Disturbance Rejection Control in the closed-loop regulation of power converters. The continuous-time Linear Extended State Observer was discretized using the zero-order hold method to obtain a current estimator-based Linear Extended State Observer that is suitable for real-time implementation. The design considerations for discrete-time Linear Active Disturbance Rejection Control, including the selection of observer and controller parameters and the sampling period, are addressed. For performance comparison, a PI controller was designed and implemented in discrete time. The control schemes were evaluated via MATLAB/Simulink (2025b) simulations and real-time closed-loop experiments on a microcontroller to assess the transient response, disturbance rejection capability, and steady-state accuracy of the buck converter. The simulation and experimental results demonstrate that the discrete-time Linear Active Disturbance Rejection Control incorporating a current-estimator-based Linear Extended State Observer significantly outperforms the PI controller in terms of transient response and disturbance rejection capability. From this perspective, this study provides a meaningful contribution to the limited literature on linear extended state observer-based discrete-time Active Disturbance Rejection Control methods.

1. Introduction

Power converters are widely utilized in numerous applications, such as consumer electronics, electric vehicles, renewable energy systems, data centers, telecommunication infrastructure, industrial automation, medical devices, household appliances, lighting systems, and audio–visual equipment. Regardless of the application domain, a power converter must exhibit robust dynamic behavior and maintain stable operation in the presence of disturbances.

Like other dynamic systems, power converters are inherently exposed to various internal and external disturbances, including input voltage fluctuations, load variations, component tolerances, and measurement noise. These disturbances not only complicate the control design, but also degrade the system performance, efficiency, and reliability [1]. As modern power converters demand a higher dynamic response, tighter voltage regulation, and improved energy efficiency, the development of robust control strategies capable of rejecting disturbances in real time has become increasingly important.

Classical linear controllers, such as PI/PID controllers, have been widely used in industrial applications for many years because of their simple structures and ease of implementation. However, their performance deteriorates significantly under rapidly changing operating conditions, strong nonlinearities, and uncertainties in the system parameters. Moreover, with the widespread adoption of advanced microcontrollers and digital signal processors, the simplicity of classical controllers is no longer considered an advantage [2]. Consequently, traditional PI/PID control strategies are gradually being replaced by modern control approaches that offer superior disturbance rejection capabilities and enhanced robustness. Among these modern methods, Active Disturbance Rejection Control (ADRC) has emerged as a promising approach that provides higher adaptability and robustness without requiring an exact mathematical model of the system [2].

ADRC was first proposed by Han as a nonlinear control algorithm [3]. The core of the ADRC framework is an observer that estimates the total disturbance, including external disturbances and system uncertainties. This observer treats the total disturbance as an additional system state and is referred to as the Extended State Observer (ESO).

The original ADRC proposed by Han employs a Nonlinear Extended State Observer (NLESO) and is consequently known as Nonlinear Active Disturbance Rejection Control (NLADRC) [2]. Despite its robustness, the NLADRC involves numerous parameters that must be tuned, thereby limiting its applicability in practical engineering implementations. To address this limitation, Gao introduced a linear version that preserves many of the advantages of the original method while simplifying the tuning process [4]. This version uses a Linear Extended State Observer (LESO) and is commonly referred to as Linear Active Disturbance Rejection Control (LADRC) [3].

Numerous studies have investigated the application of the LADRC in power converter control. From a control strategy perspective, existing studies can be categorized into pure LADRC/ADRC-based control, hybrid LADRC/LESO-based control schemes, and LESO-assisted advanced control strategies.

Pure LADRC/ADRC-based control strategies constitute a significant portion of the literature. An LESO-based ADRC was proposed for the closed-loop control of a dual active bridge (DAB) series resonant converter, where the feedback law and observer were optimized to reduce estimation errors and improve stability and dynamic performance [5]. A fractional-order LADRC was introduced in [6] for a buck converter to enhance the response speed, disturbance rejection capability, and control accuracy, with validation through simulations and experiments. A series-compensation-based ADRC was developed for DAB power supplies feeding pulsed loads, improving the suppression of ramp, acceleration, and sinusoidal disturbances while reducing the steady-state error; disturbance estimation accuracy was enhanced by integrating a PID block [7]. An LESO-based ADRC focusing on estimating disturbances in the system gain was proposed to eliminate steady-state errors caused by time-varying disturbances and was validated on a floating boost converter [8]. Similarly, in [9], the LADRC was applied to an LLC resonant converter for electric vehicle chargers, where a compensation function was introduced to improve the LESO prediction accuracy while reducing the computational burden. A dual-loop LESO-based LADRC was proposed for a DC–DC boost converter to address output voltage instability caused by non-minimum phase behavior, input voltage variations, and load disturbances, and its effectiveness was demonstrated through both simulation and experimental studies [10].

Hybrid LADRC/LESO-based control strategies have been proposed to combine disturbance rejection capability with complementary control mechanisms. LADRC was applied to unified power flow control of modular multilevel converters, where an additional disturbance observer was employed to enhance LESO’s disturbance prediction capability [11]. A feedforward control strategy combining LESO and super-twisting sliding mode control was proposed for a DAB DC–DC converter in off-grid hydrogen production systems [12]. An adaptive control approach combining LESO with a phase-locked loop observer (PLLO) was presented for a DAB DC–DC converter, in which the transient behavior was regulated by the PLLO and the steady-state behavior was handled by the LESO [13]. A combined LADRC–sliding mode control (SMC) strategy was developed for a DAB converter in a distributed electric propulsion system, achieving an improved dynamic response and robustness [14]. A decentralized and decoupled LADRC-based control strategy was proposed for input-series output-parallel (ISOP) DAB converters, where two LESOs were employed to decouple the voltage regulation and input voltage-sharing loops, thereby mitigating coupling-induced oscillations and enhancing scalability [15].

LESO-assisted advanced control strategies, in which LESO is integrated into predictive or nonlinear control frameworks, represent another important research direction. A model-free LESO-based model predictive control (MPC) strategy was proposed for a non-isolated AC–DC–DC converter, achieving superior disturbance rejection against model uncertainties, external disturbances, and load variations compared with the conventional MPC [16]. The LESO was formulated in continuous time and discretized using the Euler method as follows: An LESO-based finite-set ultra-local MPC (FS-ULMPCC) was proposed for an AC–DC converter in direct-driven wind energy systems, yielding improved steady-state performance [17]. An LESO-based MPC was developed for a three-phase interleaved bidirectional DC–DC converter to enhance its robustness against uncertainties and external disturbances [18]. An LESO-based sliding mode control (SMC) scheme was proposed for the output voltage regulation of a buck–boost converter, where the LESO estimated matched and unmatched disturbances and the SMC handled voltage regulation; experimental validation was conducted using a dSPACE-based HIL platform [19]. An LADRC-based SMC strategy was applied to bus voltage regulation of an AC–DC converter in DC distribution networks, and the performance was verified through simulations [20].

Power converter applications have been widely studied with respect to Linear Active Disturbance Rejection Control (LADRC). A significant portion of these studies has focused primarily on simulation-based evaluations. While some implementations have been carried out in hardware-in-the-loop (HIL) laboratory setups, only a few have employed high-performance digital platforms such as FPGA or DSP. With the exception of [16], in all the surveyed studies, the Linear Extended State Observer (LESO), which is the core component of LADRC, was designed in continuous time. In [16], discretization is treated at a basic level using the Euler method, which is known to provide low accuracy compared to methods such as Zero-Order Hold (ZOH).

Our comprehensive literature review revealed a notable gap in the discrete implementation of the LADRC, particularly in power converter applications. The accurate estimation of state variables is critical for control performance. In discrete-time observer-based control systems, employing the most recent output sample is commonly referred to as the current estimator approach. This technique can significantly enhance the accuracy and reliability of the discrete control action. To the best of our knowledge, no comprehensive study has addressed the current estimator-based discrete-time LESO for power converter control. This situation limits the translation of the LADRC from simulations to real-world power converter systems.

This paper presents a systematic approach to the discrete implementation of Linear Active Disturbance Control (LADRC), addressing the gap in the existing literature. In this study, the Linear Extended State Observer (LESO), which is the core component of the LADRC, was discretized using the Zero-Order Hold (ZOH) method. In digital control applications, the ZOH method differs from the Euler, FOH, and Tustin methods in terms of its low computational load and physical consistency. The Euler, FOH, and Tustin methods exhibit limitations in terms of discretization accuracy, computational complexity, and distortion in the high-frequency dynamics, respectively.

The discrete-time LESO is designed current estimator form, which utilizes the most recent output sample. This enhances the estimation accuracy of the discrete time LESO. In addition, discrete-time Linear Active Disturbance Rejection Control (D-LADRC) incorporating a current-estimator-based Linear Extended State Observer (CE-LESO) was implemented on a power converter using a microcontroller.

This study also presents a systematic approach to parameter tuning and a practical method for sampling time selection in CE-LESO-based D-LADRC implementations. Overall, this study contributes to the field of Active Disturbance Rejection Control by systematizing the discrete design process and simplifying the experimental realization. It also aims to reduce dependence on high-level software tools such as embedded code generators.

This study systematically and comparatively examines LESO estimator topologies and discretization methods based on criteria such as estimation error, noise sensitivity, recovery time, sampling time, PWM latency, and sampling frequency sensitivity. In this context, the combination of the evaluation of the current-estimator-based LESO structure and Zero-Order Hold discretization approach provides a meaningful contribution to the limited literature on discrete LADRC design for high-frequency power converters.

The remainder of this paper is organized as follows. Section 2 presents the state-space model of the buck converter, feedback linearization, continuous-time LESO design, discretization of the LESO using the ZOH method in the current estimator form, D-LADRC parameter tuning, and CE-LESO-based D-LADRC block diagram of the buck converter. Section 3 presents the simulation and experimental results comparing the CE-LESO-based D-LADRC with a classical PI controller. Finally, Section 4 and Section 5 present the discussion and conclusions of the study, respectively.

2. CE-LESO-Based D-LADRC of Buck Converter

2.1. State Space Model

The circuit topology of the buck converter, as illustrated in Figure 1, consists of an inductance ($L_1$), a capacitance ($C_1$), and two semiconductor switches ($Q_1$ and $D_1$). The load supplied by the converter is represented by the variable resistance ($R_1$). The input and output voltages of the buck converter are denoted as $V_i$ and $V_o$, respectively, and $u$ denotes the control signal. The control signal is converted into switching pulses using a pulse-width modulator (PWM). The output voltage of the buck converter is regulated by adjusting the control signal $u$.

The dynamics of the buck converter can be expressed in the standard state-space form by employing the state-space averaging method. The standard state-space representation of a single-input single-output (SISO) system is defined by (1).

$$\begin{array}{c}\dot{\mathbf{x}}\triangleq \mathbf{F}\mathbf{x}+\mathbf{G}u\\ y\triangleq \mathbf{H}\mathbf{x}+Ju\end{array}$$

(1)

Accordingly, the dynamics of the buck converter can be represented in standard form as in (2).

$$\begin{array}{c}\left[\genfrac{}{}{0ex}{}{{\dot{x}}_1}{{\dot{x}}_2}\right]=[\genfrac{}{}{0ex}{}{0}{-1/L_1{C}_1}\hspace{1em}\genfrac{}{}{0ex}{}{1}{-1/R_1{C}_1}]\left[\genfrac{}{}{0ex}{}{x_1}{x_2}\right]+\left[\genfrac{}{}{0ex}{}{0}{V_i/L_1{C}_1}\right]u\\ y=[1\hspace{1em}0]\left[\genfrac{}{}{0ex}{}{x_1}{x_2}\right]\end{array}$$

(2)

where $x_1$ and $x_2$ denote the state variables representing the output voltage ($v_o$) and its time derivative (${\dot{v}}_o$), respectively.

For an ideal buck converter, the state equations can be derived from the state-space model, as given in (3).

$$\begin{array}{c}{\dot{x}}_1=x_2\\ {\dot{x}}_2=-{\displaystyle \frac{1}{L_1{C}_1}}{x}_1-{\displaystyle \frac{1}{R_1{C}_1}}{x}_2+{\displaystyle \frac{V_i}{L_1{C}_1}}u\end{array}$$

(3)

The generalized nonideal state-space model of the buck converter, which incorporates parameter uncertainties and external disturbances, is expressed as follows:

$$\begin{array}{c}{\dot{x}}_1=x_2\\ {\dot{x}}_2=f\left(x_1,x_2,d\right)+b_0.u\end{array}$$

(4)

Here, $d$ denotes the lumped disturbance that represents the effects of model uncertainties and external disturbances. The term $b_0$ denotes the system gain defined in (5).

$$b_0={\displaystyle \frac{V_i}{L_1{C}_1}}$$

(5)

2.2. Feedback Linearization

In the feedback linearization control approach, the nonlinear dynamics of a system, including the effects of disturbances, can be canceled such that the closed-loop dynamics are transformed into linear dynamics. Therefore, the closed-loop behavior of a nonlinear system can be analyzed and controlled using conventional linear control techniques. A second-order nonlinear system in the controllable canonical form is given by (6).

$$\begin{array}{c}{\dot{x}}_1=x_2\\ {\dot{x}}_2=f\left(\mathbf{x}\right)+b\left(\mathbf{x}\right).u\end{array}$$

(6)

where $\mathbf{x}={[x_1, x_2]}^T$ and $f\left(\mathbf{x}\right)$ is a function dependent on the state variables. The function $f\left(\mathbf{x}\right)$ may be either linear or nonlinear. Assuming $b\left(\mathbf{x}\right)\ne 0$, the control input can be selected as shown in (7).

$$u={\displaystyle \frac{1}{b\left(\mathbf{x}\right)}}(u_0-f\left(\mathbf{x}\right))$$

(7)

In this case,

$${\dot{x}}_2={\ddot{x}}_1=u_0$$

(8)

The system is then transformed into an integrator chain. If the system output $x_1$ is required to track a reference, $u_0$ can be chosen as in (9), enabling the tracking error to converge to zero by using linear control methods.

$$u_0={\ddot{x}}_r-k_0.\left(x_1-x_r\right)-k_1.({\dot{x}}_1-{\dot{x}}_r)$$

(9)

By substituting (9) into (8) with respect to reference $x_r$, the following expression is obtained:

$$({\ddot{x}}_1-{\ddot{x}}_r)+k_0.\left(x_1-x_r\right)+k_1.({\dot{x}}_1-{\dot{x}}_r)=\ddot{e}+k_1\dot{e}+k_{0}e=0$$

(10)

where $e$ denotes the tracking error. The coefficients $k_0$ and $k_1$ are selected such that the roots of (10) lie in the left half of the complex plane, ensuring that the tracking error $e$ converges to zero as $t\to \mathrm{\infty }$. As the reference of the buck converter is constant, it is clear that ${\ddot{x}}_r={\dot{x}}_r=0$.

The characteristic equation of the system given by (10) can be expressed as

$$\lambda \left(s\right)={s^2+k_{1}s+k_0=\left(s+{\omega }_c\right)}^2$$

(11)

For simplicity and to achieve the fastest response without overshoot, the roots of the characteristic equation are chosen to coincide with the real axis. Therefore, the feedback linearization gains can be expressed as $k_0={\omega }_c^2$ and $k_1=2{\omega }_c$, where ${\omega }_c$ is the closed-loop control bandwidth.

To implement feedback linearization, function $f$ in (7) must be measured. However, measuring $f$ is often impossible or costly. In this case, if $f$ can be estimated by an observer, the system can be controlled using feedback linearization. The Linear Extended State Observer (LESO) treats the unmeasurable function $f$ as an additional state and attempts to estimate it.

2.3. Linear Extended State Observer

The extended state equations of the system defined in (6), in which the lumped disturbances are treated as new state variables, can be expressed as follows:

$$\begin{array}{c}{\dot{x}}_1=x_2\\ {\dot{x}}_2=x_3+b\left(\mathbf{x}\right).u\\ {\dot{x}}_3=\dot{f}\\ y=x_1\end{array}$$

(12)

Here, $x_3$ represents the extended state that includes model uncertainties and external disturbances, referred to as lumped disturbances, and also corresponds to the function $f(x_1,x_2,d)$ given in (4). When the above set of equations is expressed in the vector–matrix form, the extended state-space model of the system is obtained, as shown in (13). It can be observed that although the buck converter to be controlled is a second-order system, the extended system formed by incorporating lumped disturbances has a third-order structure.

$$\begin{gathered} \left[\begin{array}{c}{\dot{x}}_1\\ {\dot{x}}_2\\ {\dot{x}}_3\end{array}\right]=\underset{\mathbf{A}}{\underbrace{\left[\begin{array}{ccc}0& 1& 0\\ 0& 0& 1\\ 0& 0& 0\end{array}\right]}}\left[\begin{array}{c}{x}_1\\ x_2\\ x_3\end{array}\right]+\underset{\mathbf{B}}{\underbrace{b_0\left[\begin{array}{c}0\\ 1\\ 0\end{array}\right]}}u+\underset{\mathbf{E}}{\underbrace{\left[\begin{array}{c}0\\ 0\\ 1\end{array}\right]}}\dot{f} \\ y=\underset{\mathbf{C}}{\underbrace{\left[\begin{array}{ccc}1& 0& 0\end{array}\right]}}\left[\begin{array}{c}{x}_1\\ x_2\\ x_3\end{array}\right] \end{gathered}$$

(13)

The extended system described in (13) along with its corresponding observer is depicted in the block diagram in Figure 2.

In the block diagram, let $\mathbf{x}=[x_1,x_2,x_3{]}^T$ and $\tilde{\mathbf{x}}=[{\tilde{x}}_1,{\tilde{x}}_2,{\tilde{x}}_3{]}^T$ denote the actual and estimated states of the system and let $y$ and $\tilde{y}$ represent the measured and estimated outputs, respectively. Accordingly, the continuous-time observer for the system can be designed as:

$$\dot{\tilde{\mathbf{x}}}=\mathbf{A}\tilde{\mathbf{x}}+\mathbf{B}u+\mathbf{L}(y-\tilde{y})$$

(14)

The error dynamics of the observer are given by Equation (15).

$$(\dot{\mathbf{x}}-\dot{\tilde{\mathbf{x}}})=(\mathbf{A}-\mathbf{L}\mathbf{C})(\mathbf{x}-\tilde{\mathbf{x}})+\mathbf{E}\dot{f}$$

(15)

Because the variations in the disturbances and estimation error are physically bounded, the system output is asymptotically stable [16].

If the observer gain matrix $L=[l_1,l_2,l_3{]}^T$ is chosen such that the eigenvalues of the observer lie in the left half of the complex plane, then the observer is guaranteed to be stable. For convenience and to achieve the fastest convergence without an overshoot, the observer poles can be selected as coincident on the left half of the complex plane, as indicated in (16), as follows:

$$\mathbf{P}=[-{\omega }_0{-\omega }_0{-\omega }_0]$$

(16)

The characteristic polynomial of the observer and corresponding gain matrix $\mathbf{L}$, which places this characteristic polynomial at the desired closed-loop pole locations denoted by P, can be determined as follows:

$$\begin{array}{c}\lambda \left(s\right)=\left|s\mathbf{I}-\left[\mathbf{A}-\mathbf{L}\mathbf{C}\right]\right|={\left(s+{\omega }_0\right)}^3=s^3+l_1{s}^2+l_{2}s+l_3\\ \mathbf{L}={\left[\begin{array}{ccc}{3\omega }_0& {3{\omega }_0}^2& {{\omega }_0}^3\end{array}\right]}^T\end{array}$$

(17)

2.4. Discretization of the LESO

The Linear Extended State Observer (LESO), designed in continuous time, must be discretized to enable its implementation on a microcontroller. In this study, the Zero-Order Hold (ZOH) method was employed for the discretization of the LESO. First, the discretization of a continuous-time system given in the standard state-space form using the ZOH method is addressed, and the discretization of the continuous-time LESO, as expressed in (13), is presented.

The discrete-time state-space representation of a continuous-time system, given in the standard form by (1), is presented in (18).

$$\begin{array}{c}\mathbf{x}\left(k+1\right)=\mathsf{\Phi }\mathbf{x}\left(k\right)+\mathsf{\Gamma }u\left(k\right)\\ y\left(k\right)=\mathbf{H}\mathbf{x}\left(k\right)+Ju\left(k\right)\end{array}$$

(18)

Here, $\mathsf{\Phi }$, $\mathsf{\Gamma }$, $\mathbf{H}$ and $J$ represent the matrices of the discrete time system. Assuming a sampling period of $\mathrm{T}$ and employing the ZOH method, the discrete-time system matrices can be expressed as:

$$\begin{array}{c}\mathsf{\Phi }=e^{\mathbf{F}\mathrm{T}}={\displaystyle \sum _{k=0}^{\infty }}{\displaystyle \frac{{\mathbf{F}}^k{\mathrm{T}}^k}{k!}}\\ \mathsf{\Gamma }={\int }_0^{\mathrm{T}}{e}^{\mathbf{F}\eta }d\eta \mathbf{G}={\displaystyle \sum _{k=0}^{\infty }}{\displaystyle \frac{{\mathbf{F}}^k{\mathrm{T}}^{k+1}}{\left(k+1\right)!}}\mathbf{G}\end{array}$$

(19)

Based on the above information, applying the ZOH to (13) yields the discrete-time LESO matrices as follows:

$$\begin{gathered} \mathsf{\Phi }=\left[\begin{array}{ccc}1& \mathrm{T}& {\displaystyle \frac{{\mathrm{T}}^2}{2}}\\ 0& 1& \mathrm{T}\\ 0& 0& 1\end{array}\right] \\ \mathsf{\Gamma }=b_0\left[\begin{array}{c}{\displaystyle \frac{{\mathrm{T}}^2}{2}}\\ \mathrm{T}\\ 0\end{array}\right] \\ \mathbf{H}=\mathbf{C},\hspace{1em}J=0 \end{gathered}$$

(20)

In discrete-time observer design, two types of estimators are commonly employed for state-variable estimation: the prediction and current estimators. While the Prediction Estimator relies on output measurements up to $y(k-1)$ to estimate the state variables, the Current Estimator makes use of the most recent measurements up to $y\left(k\right)$. In this study, the Current Estimator was selected to prevent additional delays and improve the system response in the discrete-time observer design. Figure 3 presents block diagrams of the discrete-time observer types and the dynamic equations of the Prediction Estimator, as illustrated in Figure 3a can be expressed as follows:

$$\overline{\mathbf{x}}\left(k+1\right)=\mathsf{\Phi }\overline{\mathbf{x}}\left(k\right)+\mathsf{\Gamma }u\left(k\right)+{\mathbf{L}}_{\mathbf{p}}[y\left(k\right)-\mathbf{H}\overline{\mathbf{x}}\left(k\right)]$$

(21)

Here, ${\mathbf{L}}_{\mathbf{p}}$ represents the feedback gain of the prediction estimator-based LESO, and $\overline{\mathbf{x}}\left(k\right)$ denotes the matrix of the estimated state variables. The error dynamics of the observer can be expressed as follows:

$$\mathbf{e}\left(k+1\right)=[\mathsf{\Phi }-{\mathbf{L}}_{\mathbf{p}}\mathbf{H}]\mathbf{e}\left(k\right)$$

(22)

By choosing ${\mathbf{L}}_{\mathbf{p}}={\left[l_{p1} l_{p2} l_{p3}\right]}^{\mathit{T}}$ such that the roots of the characteristic polynomial of (22) lie within the unit circle, the observer is ensured to be asymptotically stable, and for any initial error $e\left(0\right)$, the error $e\left(k\right)$ gradually converges to zero.

To simplify the design process, the poles of the prediction-Estimator-based LESO can be selected to be coincident and located inside the unit circle in the z-plane. Considering parameter $\beta$, which represents the closed-loop pole locations of the discrete-time LESO, the matrix $\mathbf{P}$ containing the desired pole locations for a third-order LESO is obtained as follows:

$$\mathbf{P}=\left[\beta \beta \beta \right]$$

(23)

The observer characteristic equation is given by (24).

$$\lambda \left(z\right)=\left|z\mathbf{I}-\mathsf{\Phi }+{\mathbf{L}}_{\mathbf{p}}\mathbf{H}\right|={(z-\beta )}^n$$

(24)

Thus, the LESO gain matrix derived from the prediction estimator is obtained as shown in (25).

$${\mathbf{L}}_{\mathbf{p}}=\left[\begin{array}{c}3(1-\beta )\\ {\displaystyle \frac{1}{2\mathrm{T}}}\left\{6{(1-\beta )}^2-{(1-\beta )}^3\right\}\\ {\displaystyle \frac{1}{{\mathrm{T}}^2}}{(1-\beta )}^3\end{array}\right]$$

(25)

A relationship exists between the feedback gain matrices of the prediction and current estimators, as expressed in (26).

$${\mathbf{L}}_{\mathbf{c}}={\mathsf{\Phi }}^{-1}{\mathbf{L}}_{\mathbf{p}}$$

(26)

The locations of the poles of the discrete-time LESO based on the prediction estimator can be calculated using the following equation, taking the continuous-time LESO poles given in (16) as a reference, with $\mathrm{T}$ as the sampling period:

$$\beta =e^{-{\omega }_0\mathrm{T}}$$

(27)

To validate discrete-time LESO structures a second order system was selected with a natural angular frequency ${\omega }_n=4000 \mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}$. For this second-order system, current estimator (CE) and prediction estimator (PE)-based third-order observers were obtained using zero-order hold (ZOH) and Euler discretization methods. Within this scope, four LESO variants were created: CE-LESO ZOH, CE-LESO Euler, PE-LESO ZOH, and PE-LESO Euler. For a fair comparison, a sampling period $T = 40 \mathsf{\mu }\mathrm{s}$ and an observer bandwidth ω₀ = 20,000 rad/s were selected for all observer types. The corresponding pole placement parameter β was calculated as 0.4493 for the given sampling period and bandwidth. A noise with an RMS value of 20 × 10⁻³ p.u. (2% of the output value) was injected into the output channel $\left(y\right)$. Note that 1 p.u. corresponds to the nominal output. The injected noise was modeled as band-limited white noise, and the bandwidth was selected as 10% of the sampling frequency ($f$). The noise sensitivity (NS) metric was calculated over a 100 ms evaluation period. The estimation error and recovery time metrics were obtained from the step-input disturbance. The results are presented in Figure 4 and summarized in

Table 1. Comparative evaluation of current- and prediction estimator-based discrete-time LESOs.

LESO Type	$\mathbf{Estimation} \mathbf{Error} \mathit{e}\left(\mathit{t}\right)=(\mathit{y}-\tilde{\mathit{y}})$	$\mathbf{Recovery} \mathbf{Time} (\mathit{\%}2)$${\mathit{t}}_{\mathit{r}}$ (ms)	Noise Sensitivity $\mathit{N}\mathit{S}={\mathit{y}}_{\left(\mathit{R}\mathit{M}\mathit{S}\right)}/{\mathit{n}}_{\left(\mathit{R}\mathit{M}\mathit{S}\right)}$
CE-LESO (ZOH)	~7.811 × 10−7	~30 ms	~1.004
CE-LESO (Euler)	~8.672 × 10−7	~30 ms	~1.004
PE-LESO (ZOH)	~86.111 × 10−7	~40 ms	~1.286
PE-LESO (Euler)	~95.598 × 10−7	~40 ms	~1.286

Test conditions: $T=40 \mu s$, ${\omega }_0=4000 \mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}$, $\beta =0.4493$. Injected noise $n_{\left(RMS\right)}=30\mathrm{m}\mathrm{p}.\mathrm{u}.$ where 1 p.u. corresponds to the nominal output of the system. The noise Sensitivity was computed over a 100 ms steady-state evaluation window.

. Accordingly, it has been demonstrated that the CE-LESO structures provide lower estimation errors, especially when used in conjunction with ZOH discretization. Furthermore, it has been observed that the CE-LESO structures exhibit lower sensitivity to measurement noise and faster recovery behavior for both ZOH and Euler discretization methods. In contrast, the PE- LESO structures showed poor performance in all evaluation metrics. This result demonstrates that a ZOH-discretized CE-LESO achieves a higher estimation accuracy, comparable noise sensitivity, and recovery time in digital control applications.

2.5. D-LADRC Parameter Tuning

In CE-LESO-based D-LADRC, three parameters need to be adjusted: ${\omega }_c$, ${\omega }_0$, and $\mathrm{T}$. Here, ${\omega }_c$ represents the bandwidth of the state feedback controller, ${\omega }_0$ is the bandwidth of the LESO, and $\mathrm{T}$ denotes the sampling time.

The appropriate selection of ${\omega }_c$ can be performed by trial and error according to the settling time criterion of the output voltage of the buck converter. ${\omega }_0$ can be determined as in (28) to ensure that the estimation error of LESO converges rapidly to zero [21].

$${\omega }_0=(2-5){\omega }_c$$

(28)

The sampling time T should be selected such that the pole locations given in (27) remain sufficiently distant from the unit circle. If the sampling time is too long, the pole locations given in (27) will be very close to the unit circle, making the observer excessively sensitive to parameter variations.

2.6. Design Procedure

In this section, the step-by-step design procedure of the D-LADRC is presented to guide researchers who intend to implement the controller in discrete time. In this context, the fundamental steps to be followed in the design of the discrete-time structure of the controller are explained in detail, and the key considerations during the implementation process are discussed.

Step 1. Determine system order ($n$) and gain $b_0$: Because active disturbance rejection control (ADRC) does not require a complete mathematical model of the system, the system order ($n$) and gain ($b_0$) can be determined through simulation-based methods such as sweep analysis. However, as mathematical models of power converters are widely available in the literature, it is recommended to determine these parameters based on a mathematical model.

Step 2. Determine closed-loop bandwidth, ${\omega }_c$: ${\omega }_c$ can be determined either through a trial-and-error approach or by applying optimization techniques. Based on our experimental observations, an initial estimate of ${\omega }_c=5{\omega }_n$, where ${\omega }_n$ denotes the natural frequency of the system, provides a reliable starting point for further tuning.

Step 3. Define $u_0$ linear function and its coefficients: To achieve feedback linearization, the $u_0$ function should be determined according to the order of the system. Once $u_0$ is defined, the gains $k_0,k_1,\dots ,k_{n-1}$ can be calculated according to the system order, as shown in (11).

Step 4. Define Closed-loop bandwidth of LESO, ${\omega }_0$: For the selection of ${\omega }_0$, a range of ${\omega }_0=(2-5){\omega }_c$ is recommended to enable the LESO to track the system rapidly [21].

Step 5. Determine the sampling time, $T$: The sampling period should be determined such that the discrete-time closed-loop control poles remain sufficiently within the unit circle in the z-domain. An excessively large sampling period causes the poles to approach the unit circle, thereby leading to slower system dynamics and reduced stability margin. Conversely, excessively small sampling times drive the poles too close to the origin, resulting in increased noise amplification and greater sensitivity to sampling and actuation delays. In this context, the sampling time should be considered to achieve a balanced placement that ensures closed-loop stability, dynamic response speed, and noise robustness. The sampling time should be selected such that the desired pole locations β of the discrete-time LESO remain inside the unit circle in the z-plane. The recommended range for β is 0.3–0.7.

Step 6. Calculate LESO matrices: The matrices $\mathsf{\Phi }$, $\mathsf{\Gamma }$, ${\mathbf{L}}_{\mathbf{p}}$, and ${\mathbf{L}}_{\mathbf{c}}$ are computed using (20), (25), and (26) respectively.

Figure 5 shows the block diagram of the buck converter controlled by a discrete-time current estimator-based LESO within the D-LADRC framework. Both simulation and experimental investigations were performed based on this block diagram. In this setup, an LESO incorporating a current estimator was employed to estimate the output voltage of the buck converter, its variations, and the states associated with the disturbances.

Subsequently, through feedback linearization, the buck converter was linearized with respect to the disturbances, enabling the output voltage dynamics to be addressed using linear control techniques. The control signals generated by these linear control methods are then converted into pulse-width modulation (PWM) signals via a comparator and applied to the buck converter.

3. Results

3.1. Simulation Studies

In this study, the performance of the CE-LESO-based D-LADRC was compared with that of a PI controller using MATLAB-Simulink. The coefficients of both controllers were tuned to achieve a settling time of 1 ms without an overshoot in response to a step input, thereby ensuring a fair comparison. The PI control path did not include any anti-windup mechanism, and no digital filtering was applied in either the PI or ADRC controllers. To mitigate high-frequency noise and preserve signal integrity, a simple analog RC filter with a cutoff frequency of 1 MHz was implemented at the microcontroller’s ADC measurement input. The parameters of the converter used in the simulation studies are presented in

Table 2. The Buck Converter Parameters.

Parameters	Symbol	Value
Nominal Input Voltage	$V_i$	20 V
Nominal Output Voltage	$V_o$	5 V
Nominal Output Power	$P_o$	25 W
Switching Frequency	$f_{sw}$	100 kHz
Sampling Frequency	$f_s$	200 kHz
Filter Capacitor	$C_1$	100 µF
Filter Inductor	$L_1$	200 µH
Nominal Load	$R_1$	1 Ω
System Gain	$b_0$	2.1277 × 108

.

The coefficients of the PI controller were tuned using the MATLAB tuning tool and are presented in

Table 3. Controllers Parameters.

Controller	Settling time	Overshot	Coefficient	Value
PI	1 ms	0%	$k_p$	0.0002
			$k_i$	$96$
D-LADRC	1 ms	0%	${\omega }_c$	$8000 \mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}$
			T	10 × 10−6 s
			${\omega }_o$	40,000 rad/s
			β	0.6703

. Accordingly, the coefficients of the CE-LESO-based D-LADRC were selected to achieve a settling time of 1 ms without overshooting.

In the simulations, the output voltage response of the converter to external disturbances, including input voltage and output current variations, as well as to internal dynamics caused by model parameter changes, was analyzed. The ADC quantization error and sensor noise were added to the measurement channel to evaluate the robustness of the D-LADRC. Additionally, the sampling-rate and delay sensitivity of the D-LADRC are examined by selecting a switching frequency of $f_s=100 \mathrm{kHz}$ and introducing a 2-PWM-cycle latency. The results are shown in Figure 6.

Figure 6a shows the step response of the buck converter under nominal operating conditions. For both controllers, the converter output voltage reached the 2% band in approximately 1 ms with almost no overshoot.

Figure 6b illustrates the disturbance rejection capabilities of the controllers for a 50% step-up disturbance in the input voltage. Owing to this disturbance, the converter output voltage exhibited a maximum overshoot of 0.3 V for the D-LADRC and 2 V for the PI. The time required for the output voltage to return to the 2% band was approximately 600 µs for the D-LADRC and 1.5 ms for PI.

Figure 6c shows the disturbance rejection performance for a 50% step-down disturbance in the input voltage. Owing to this disturbance, the converter output voltage experienced a maximum drop of 0.75 V for the D-LADRC and 2.3 V for PI. The time for the output voltage to return to the 2% band was approximately 1.5 ms for the D-LADRC and 3 ms for PI.

Figure 6d illustrates the disturbance rejection capabilities for a 50% step-up disturbance in the output current. The converter output voltage exhibited a maximum drop of 0.75 V for the D-LADRC and 1.6 V for the PI. The time required for the output voltage to return to the 2% band was approximately 800 µs for the D-LADRC and 1.4 ms for PI.

Figure 6e shows the disturbance rejection performance for a 50% step-down disturbance in the output current. Owing to this disturbance, the converter output voltage showed a maximum overshoot of 1.1 V for the D-LADRC and 2.1 V for the PI. The time required for the output voltage to return to the 2% band was approximately 800 µs for the D-LADRC and 2.2 ms for PI.

Figure 6f shows the model-based disturbance rejection capabilities of the controllers for 8% and 20% deviations in the inductor and capacitor values of the buck converter. The D-LADRC closely followed the nominal response curve for both the step response and 50% step-down output current disturbance, showing almost no deviation from the nominal response. By contrast, the PI controller exhibited a slightly higher overshoot and longer settling time than the nominal step response. For the 50% output current disturbance, the maximum voltage deviation remained almost unchanged, whereas the settling time increased by approximately 500 µs compared with the nominal case.

Figure 6g demonstrates the robustness of the D-LADRC against the ADC quantization error and measurement noise. The ADC quantization error is modeled by masking the least significant 4 bits of result register, while sensor noise is represented by band-limited white noise with an RMS amplitude of $n_{RMS}=100 \mathrm{m}\mathrm{V}$ and a bandwidth of $BW=0.1 f_s$. The output voltage did not show any noticeable degradation with the ADC quantization error alone. When both the quantization error and measurement noise are present, the D-LADRC maintains a satisfactory performance.

Figure 6h illustrates the sampling rate and PWM latency sensitivity of the D-LADRC at sampling frequencies of 100 and 200 kHz, with a 2-PWM-cycle latency. Both tests were conducted under a 50% step-down load current disturbance. Reducing the sampling frequency from 200 to 100 kHz caused no noticeable change in the output voltage response or settling time. The introduction of a two-PWM-cycle latency results in output voltage deviations that remain within acceptable limits. Under these conditions, the D-LADRC maintained a stable behavior with respect to the sampling frequency and PWM latency.

Table 4. Performance comparison of controllers (simulation).

Disturbance	Step Magnitudes	$\mathbf{Settling} \mathbf{Time} (\%2), {\mathit{t}}_{\mathit{s}}$ (ms),		Overshoot (%)
		D-LADRC	PI	ADRC	PI
Step Response	0 → 5 V	1	1	0	0
$V_i$ Step up	20 → 30 V	0.6	1.5	6	40
$V_i$ Step down	20 → 10 V	1	3	15	46
$I_o$ Step up	2.5→5 A	0.8	1.4	15	32
$I_o$ Step down	5→2.5 A	0.8	2.2	22	42
L1 = 216 uH/C1 = 80 uF	5→2.5 A	0.8	3.5	22	42

illustrates the closed-loop performance of the buck converter when subjected to various disturbance conditions, comparing the D-LADRC and PI controller performances.

Table 5. Output voltage metrics across test scenarios for D-LADRC (simulation).

Scenario	${\mathit{V}}_{0,\mathit{m}\mathit{i}\mathit{n}}\left(\mathbf{V}\right)$	${\mathit{V}}_{0,\mathit{m}\mathit{a}\mathit{x}}\left(\mathbf{V}\right)$	Peak Error	$\mathbf{Settling} \mathbf{Time} (\%2), {\mathit{t}}_{\mathit{s}}$ (µs)
Quantization Error + Sensor Noise	4.61 V	6.23 V	1.23 V	780 µs
$f_s=200 \mathrm{k}\mathrm{H}\mathrm{z}$ + 2-PWM Latency	4.62 V	6.25 V	1.25 V	800 µs
$f_s=100 \mathrm{k}\mathrm{H}\mathrm{z}$ + 2-PWM Latency	4.40 V	6.43 V	1.43 V	820 µs

Quantization error: 4-bit LSB masking; Sensor Noise: band-limited white noise $n_{RMS}=100 \mathrm{m}\mathrm{V}$, $BW=0.1 f_s$.

details the noise immunity and sensitivity to PWM latency of the D-LADRC.

3.2. Experimental Verificaiton

For the discrete implementation of the D-LADRC, a 25 W buck converter was selected as the power converter. The parameters of the converter were the same as those used in the simulation study and are listed in Table 2. In the experimental study, discrete implementations of both the D-LADRC and PI controller were performed using the TMS320F28377S microcontroller (Texas Instruments, Dallas, TX, USA). The converter output voltage was measured using an on-chip analog-to-digital converter (ADC) operating at a 12-bit resolution in the single-ended mode. The pulse-width modulation (PWM) module was configured with a switching frequency of 200 kHz. The control algorithm is executed at discrete times with a fixed sampling period synchronized to the PWM cycle. To ensure deterministic timing and minimize sampling jitter, the ADC sampling was triggered by a PWM event, providing cycle-accurate synchronization between measurement acquisition and control execution.

The real-time execution flow of the proposed controller, including the CE-LESO update and control law computation, follows the sequence outlined in Algorithm 1. A photograph of the experimental setup is presented in Figure 7.

In the experimental study, the dynamic performance of the D-LADRC and discrete-time PI controller was tested under input voltage and output current disturbances. In addition, the step response performances of both controllers were evaluated under the nominal operating conditions.

Algorithm 1: CE-LESO-Based Discrete-Time LADRC Algorithm

Parameters $\hspace{1em}-\mathrm{Sampling} \mathrm{period}, \mathrm{T}$: 10 µs $\hspace{1em}-\mathrm{PWM} \mathrm{frequency}, f_{sw}$: 200 kHz $\hspace{1em}-\mathrm{Observer} \mathrm{bandwidth}, {\omega }_0$: 40,000 rad/s $\hspace{1em}-\mathrm{Discrete} \mathrm{LESO} \mathrm{pole} \mathrm{locations}, \beta$: 0.6703 $\hspace{1em}-\mathrm{Plant} \mathrm{gain}, b_0:$ 1 × 109 $\hspace{1em}-\mathrm{Feedback} \mathrm{gains}: k_0:$$16 \times {10}^3, k_1$ = 64× 106 Control sequence (executed every T):  1. $\mathrm{Measure} \mathrm{output}, y\left(k\right)$  2. $\mathrm{Compute} \mathrm{estimation} \mathrm{error}, e\left(k\right)$  3. $\mathrm{Compute} \mathrm{states}, \widehat{x}\left(k\right)$  4. Compute virtual signal, u0(k)  5. Compute control signal, u(k)  6. $\mathrm{Compute} \mathrm{states}, \overline{x}\left(k\right)$  7. Update PWM using u(k)  8. return

Figure 8 shows the output voltage response of the converter under external disturbances, such as the input voltage and output current. Figure 8a shows the step response of the buck converter under nominal operating conditions. As observed, for both controllers, the output voltage of the converter reached the ±2% band in approximately 1.2 ms with almost no overshoot.

Figure 8b illustrates the disturbance rejection capabilities of the controllers for a 50% step-up disturbance in the input voltage. Owing to this disturbance, the output voltage of the converter exhibited a maximum overshoot of 0.25 V for the D-LADRC and 2 V for the PI controller. The output voltage returned to the ±2% band at approximately 500 µs for the D-LADRC and 1.2 ms for the PI controller.

Figure 8c presents the disturbance rejection capabilities of the controllers for a 50% step-down disturbance in the input voltage. Under this disturbance, the output voltage dropped by a maximum of 0.6 V for the D-LADRC and 2.4 V for the PI-controller. The recovery time to the ±2% band was approximately 1.3 ms for the D-LADRC and 3.4 ms for the PI-controller.

Figure 8d shows the disturbance rejection performance of the controllers for a 50% step-up disturbance in the output current. As a result of this disturbance, the output voltage decreased by a maximum of 0.7 V for the D-LADRC and 1.8 V for the PI controller. The output voltage returned to the ±2% band at approximately 700 µs for the D-LADRC and 1.2 ms for the PI controller.

Figure 8e illustrates the response of the controllers to a 50% step-down disturbance in the output current. Under this disturbance, the output voltage overshoot reached a maximum of 1 V for the D-LADRC and 2.3 V for the PI-controller. The output voltage returned to the ±2% band at approximately 600 µs for the D-LADRC and 1.8 ms for the PI controller.

Figure 8f demonstrates the robustness of the D-LADRC against the ADC quantization error and measurement noise. Both tests were conducted under a 50% step-down load current disturbance. The experimental study employed the same ADC quantization and band-limited white noise models as those used in the simulations. The output voltage remains largely unaffected by the ADC quantization error. Even in the presence of both quantization errors and measurement noise, the D-LADRC preserves an acceptable control performance.

Figure 8g shows how the D-LADRC responds to variations in the sampling rate and PWM latency at sampling frequencies of 100 and 200 kHz, with a latency of two PWM cycles. Both scenarios were tested under a 50% reduction in the load current. When a 2-PWM-cycle latency was introduced at a sampling frequency of 100 kHz, the output voltage deviations remained within acceptable bounds. Overall, the findings in Figure 8g indicate that the D-LADRC exhibits stable performance in terms of the sampling frequency and PWM latency under the specified operating conditions.

Table 6. Performance comparison of controllers (experimental).

Disturbance	Step Magnitudes	$\mathbf{Settling} \mathbf{Time} (\%2), {\mathit{t}}_{\mathit{s}}$(ms)		Overshoot (%)
		D-LADRC	PI	D-LADRC	PI
Step Response	0 → 5 V	1.2	1.2	0	0
$V_i$ Step up	20 → 30 V	0.5	1.2	5	40
$V_i$ Step down	20 → 10 V	1.3	3.4	12	48
$I_o$ Step up	2.5→5 A	0.7	1.2	14	36
$I_o$ Step down	5→2.5 A	0.6	1.8	20	46

summarizes the closed-loop performance of the buck converter under various disturbance conditions for the D-LADRC and PI controller.

Table 7. Output voltage metrics across test scenarios for D-LADRC (experimental).

Scenario	${\mathit{V}}_{0,\mathit{m}\mathit{i}\mathit{n}}\left(\mathbf{V}\right)$	${\mathit{V}}_{0,\mathit{m}\mathit{a}\mathit{x}}\left(\mathbf{V}\right)$	Peak Error	$\mathbf{Settling} \mathbf{Time} (\%2), {\mathit{t}}_{\mathit{s}}$ (µs)
Quantization Error+ Sensor Noise	4.98 V	6.18 V	1.18 V	670 µs
$f_s=200 \mathrm{kHz}$ + 2-PWM Latency	4.75 V	6.10 V	1.1 V	440 µs
$f_s=100 \mathrm{kHz}$ + 2-PWM Latency	4.96 V	6.24 V	1.24 V	700 µs

Quantization error: 4-bit LSB masking; Sensor Noise: band-limited white noise $n_{RMS}=100 \mathrm{m}\mathrm{V}$, $BW=0.1{ f}_s$.

summarizes the noise immunity and PWM latency sensitivity of the D-LADRC.

4. Discussion

A strong correlation was observed between the experimental and simulation results. As demonstrated by the experimental and simulation results, the D-LADRC exhibited a significantly superior disturbance rejection capability compared to the PI controller, as shown in Table 6. Considering the settling time and overshoot criteria, the CE-LESO-based D-LADRC was observed to provide an approximately 2–3 times faster dynamic response and a 50–80% reduction in overshoot compared with the PI controller.

In the experimental study, the computational loads of the D-LADRC and PI controller were compared, and the results are presented in

Table 8. Computational loads of controllers.

	PI	D-LARDC
CPU	TMS320F28377S	TMS320F28377S
CPU Frequency	200 MHz	200 MHz
Algorithm Clock Cycles (exact.)	36	155
Algorithm Time (approx.)	0.20 µs	0.85 µs
ISR Period	10 µs	10 µs
ISR Execution Time(approx.)	1.25 µs	1.85 µs
ISR Budget	%12.5	%18.5
Compiler Flags	off	off
Compiler Version	TI v22.6.2. LTS	TI v22.6.2. LTS

. The microcontroller used in the experimental setup operated at a frequency of 200 MHz, and the compiler version was TI v22.6.2. LTS. To ensure a fair comparison, no optimization was applied during the compilation of the controller code.

According to the results presented in Table 8, the computational load of the conventional PI controller was approximately 4.3 times lower than that of the D-LADRC. Nevertheless, the closed-loop performance evaluations summarized in Table 6 clearly indicate that the D-LADRC achieves a significantly superior control performance compared with the PI controller. In this context, it should be noted that current microcontroller technologies can handle the increased computational load associated with the D-LADRC, thereby enabling its practical implementation without compromising real-time performance.

5. Conclusions

This paper presents a discrete-time LADRC for power converters in a systematic manner. The main novelty lies in the zero-order-hold-based discretization of the continuous-time LESO and its formulation as a current estimator-based observer, enabling direct implementation on digital control platforms. In contrast to many existing studies that primarily focus on continuous-time formulations, this study explicitly addresses key discrete-time design aspects, including observer and controller parameter selection and sampling period considerations. Comprehensive simulation results and microcontroller-based experimental validations on a buck converter demonstrated that the proposed discrete-time LADRC achieved improved transient performance and enhanced disturbance rejection compared with a discrete-time PI controller while maintaining steady-state accuracy. These findings provide both methodological and experimental contributions to the limited literature on LESO-based discrete-time LADRC for digitally controlled high-frequency power converters.

Although the proposed discrete-time LESO-based method provides an effective disturbance estimation and fast dynamic response, it exhibits certain practical limitations. Increasing the observer bandwidth improves the estimation accuracy but also increases the sensitivity to the measurement noise and computational burden. In addition, high sampling frequencies impose stricter real-time constraints on microcontroller resources and execution timing. Therefore, the method should be implemented with careful consideration of the sampling time, observer parameter selection, and digital delays to achieve a balanced trade-off between stability, noise robustness, and computational complexity.