Optimizing Digital Systems Implemented in FPGA Through Effective Description of Finite State Machines

Abstract

In digital systems, finite state machines (FSMs) play a crucial role as controllers, control units, and independent sequential circuits. To efficiently implement these FSMs on advanced hardware platforms such as field-programmable gate arrays (FPGAs), it is essential to represent each FSM in a hardware description language (HDL). This article introduces innovative methods for describing FSMs in Verilog (SystemVerilog) HDL to significantly optimize both the area and performance of synthesized FSM circuits. The presented approach selects the optimal default values for the transition and output functions of an FSM and uses blocking assignment statements to assign these values to variables. This method provides an additional level of optimization independent of the techniques used to improve the FSM during the earlier design stages. Experimental studies on FSM benchmarks show that using this approach with the Quartus design tool reduces the average area of FSMs by approximately 2, and in some cases by up to 6.2. In addition, the average performance of FSMs improves by approximately 2 times and, in some examples, by more than 4 times.

1. Introduction

Every digital system includes a large number of controllers and control units, implemented as finite state machines (FSMs), that control individual devices, parts of the digital system, and the digital system as a whole. The development of FSMs remains one of the most critical tasks in the design of digital systems, since FSMs are not reused from project to project and are usually designed from scratch for each new digital system project. The characteristics of the entire system largely depend on the parameters of FSMs (area, performance, power consumption). Therefore, optimizing FSM parameters is a critical task in the design of digital systems [1].

There are several well-known strategies for optimizing FSMs that can be implemented at various stages of the FSM design process. These strategies include minimizing the number of states [2], state encoding [3,4,5], selecting the appropriate structural model [6], determining the target device for the FSM implementation, and choosing the synthesis method [7,8,9,10,11,12,13]. Additionally, minimizing the logic of the FSM [14] is another crucial factor. However, researchers often overlook the significance of the coding stage describing the FSM’s design using hardware description languages (HDLs) because they consider it too simple or obvious. Currently, the three most commonly used HDLs in practice are Verilog, SystemVerilog, and VHDL.

This paper examines the various styles of describing FSMs in Verilog, aiming to improve both the area (implementation cost) and performance (speed). These concepts can also be easily applied to describe FSMs in SystemVerilog language.

The proposed approach is based on a feature of the blocking assignment statement (‘=’) in the Verilog (SystemVerilog) language. If a blocking assignment statement is encountered in a ‘begin-end’ block of sequentially executed statements, the execution of the following statements is blocked until the assignment procedure is completed. This allows us, instead of using a ‘default’ construct in a ‘case’ statement, to assign a default value to a variable using a blocking assignment statement before the ‘case’ statement. In the description of FSMs, default values can be assigned to the variable of the next state and the output vector, which are most often encountered at the transitions of an FSM.

A key feature of the proposed approach is its independence from the FSM optimization methods used in previous design stages, such as state minimization, state encoding, synthesis methods, and logic minimization. This approach offers an additional way to optimize the synthesized circuit during the stage of describing FSMs in HDL. Currently, FSMs are implemented on various hardware platforms, including field-programmable gate arrays (FPGAs), system-on-chips (SoCs), and application-specific integrated circuits (ASICs). Notably, this approach is independent of the type of electronic device in which the FSM is implemented, whether an FPGA, SoC, or ASIC. Significantly, its effectiveness in reducing area and improving FSM performance is independent of the state-encoding method used.

The primary goal of this work is to develop and analyze different styles for describing FSMs in Verilog to reduce area and improve performance.

The main contributions of this work are as follows:

• The algorithms for creating code in Verilog and encoding states to optimize the area and performance of FSMs.
• Three styles of describing FSMs in Verilog: when the default value of the next state (dstate) is assigned, when the default value of the output vector (dout) is assigned, and when the default values of both the next state and the output vector (dstate_out) are assigned simultaneously.
• Evaluations of the effectiveness of the proposed styles of describing FSMs, determined based on the parameters of FSMs.
• Research in Quartus and Vivado design tools on the efficiency of the considered styles of FSM description using FSM benchmarks when encoding states with one-hot and binary codes.
• Recommendations for the practical use of the proposed styles of describing FSMs.

The paper is organized as follows: Section 2 provides an analysis of related works. Section 3 focuses on proposed styles for describing FSMs and compares them with the traditional approach. Section 4 presents experimental results and their analysis. Finally, Section 5 summarizes the findings and offers recommendations for the practical application of the discussed styles for describing FSMs.

2. Related Works

This section reviews the various styles for describing FSMs in Verilog, SystemVerilog, and VHDL HDLs.

In [15], the features for describing FSMs in the Verilog and VHDL languages, provided by Synopsys design tools, are considered. The primary style involves three processes: the description of FSM memory (state register), the transition functions, and the output functions. It outlines the general principles for representing FSMs in HDLs and proposes two structural models: one with a single combinational circuit and another with two combinational circuits. Various state-encoding methods are discussed, including binary, one-hot, and almost one-hot encodings. The paper also explores the use of ‘case’ and ‘if’ statements to describe transition functions across different state encoding methods, as well as considerations for asynchronous and unknown inputs, register outputs, and default output values. Furthermore, it addresses the issues of FSM recovery after errors and the exit of FSMs from illegal states.

In [16], implicit styles for describing combinational circuits and FSMs in Verilog are discussed. Five classes of FSMs are proposed, where class0 is a conventional combinational circuit, class1 is a signal delay of one clock cycle, class2 is an FSM that has no inputs and cyclically passes through a set of states, class3 is a Moore FSM, and class4 is a Mealy FSM.

The standardized FSM coding style in Verilog, used in Cisco design tools, is discussed in [17]. In this style, FSM transitions are described using a ‘case’ statement, and states are declared as local parameters. Transitions within the FSM are represented by two variables: current and next. The work also introduces the use of cisco_fsm compiler directives. This standardized FSM style facilitates the analysis of state reachability, verification of coverage for all FSM transitions, identification of final states (from which there are no exits), and the construction of a state transition graph (STG).

In [18], two styles for describing FSMs with one and two processes are analyzed, highlighting the advantages and disadvantages of each approach. The work outlines potential methods for state encoding and discusses the use of the Synopsys FSM tool to encode states using binary, Gray, and one-hot codes. Additionally, a coding style is proposed for synthesizing register outputs of a Mealy FSM. The work by [18] recommends against using the full_case and parallel_case attributes in FSM descriptions, as their use can lead to discrepancies between synthesis and modeling results. The FSM encoding styles discussed in [18] were further refined in [19], where it is proposed to use FSM register outputs to prevent failures during state transitions. Two methods are proposed for this purpose. The first method follows the style from [18] for the register outputs of a Mealy FSM, while the second method uses the output values of a Moore FSM to encode states.

Reference [20] considers new possibilities for describing FSMs provided by the SystemVerilog language. These features include the enumerated type ‘enum’ for declaring states, the use of ‘always_comb’ and ‘always_ff’ procedures, and implicit port connections, among others.

In [21], the styles for describing Moore FSMs in VHDL with combinational and register outputs, and their impact on the area and performance of FSMs, are investigated. Reference [22] explores different methods of describing FSMs in VHDL using one or two processes. Additionally, it discusses state encoding techniques, which include binary, one-hot, two-hot, and Gray codes. Moreover, a comparison is made between VHDL and Verilog languages in describing FSMs.

In [23], a converter for transforming FSM representations from the KIS2 format [24] into a Verilog language description is detailed, along with a method for verifying FSMs and constructing an STG.

In [25], seven styles for describing combinational circuits for FSMs in Verilog were presented, utilizing both ‘if’ and ‘case’ statements. These styles are labeled as IF_1, IF_2, IF_3, IF_4, CASE_1, CASE_2, and CASE_3. From this selection, the two most effective styles—IF_4 and CASE_3—were empirically chosen to optimize the area and performance of FSMs. Based on these two styles, six FSM coding styles were developed: M_1, M_2, M_3, M_4, M_5, and M_6.

In [26], Verilog-based description styles for fault-tolerant FSMs are discussed, which detect and eliminate faults in the FSM’s state register, input, and output vectors. Two styles, safe0 and safe1, are proposed for describing fault-tolerant FSMs in Verilog. These approaches also neutralize the design errors that may arise when the FSM’s transitions and outputs are not defined for all possible values of the input variables.

In [27], Verilog description styles are proposed for structural models of reliable FSMs that enable the detection of faults in input and output vectors, in present-state and next-state codes, and in invalid state transitions.

The review shows that there are currently no styles for describing FSMs that specifically focus on minimizing area and improving performance, except for reference [25]. In contrast to [25], this work introduces new styles for describing FSMs in HDLs that aim to reduce area and improve the performance of FSM circuits. These new styles are based on different principles, including the default assignment of both the next state value and the output vector value.

3. Styles of Describing FSMs for Optimizing Area and Performance

This section discusses the proposed styles for describing FSMs in Verilog, compared to the traditional three-process description.

3.1. Traditional Description of FSMs

Let X = {x₀, …, x_L−1} be the set of input variables of the FSM, Y = {y₀, …, y_N−1} be the set of output variables of the FSM, and S = {s₀, …, s_M−1} be the set of states of the FSM, where s₀ is the initial state of the FSM.

The generalized structure of an FSM is shown in Figure 1, where register Rs represents the memory of the FSM (the state register), which stores the code state of the present (current) state of the FSM. The combinational circuit λ determines the code next of the next state based on the values of the input variables of the set X and the code state of the present state. The combinational circuit δ calculates the values of the output variables of the set Y based on the code state of the present state and the values of the input variables of the set X (only for FSMs of Mealy type).

As an example, consider the FSM, whose STG is shown in Figure 2. Our FSM is a Mealy FSM (the most common case). It has five states s₀, …, s₄, three input variables x₀, …, x₂, and three output variables y₀, …, y₂. The vertices of the graph in Figure 2 denote the states of the FSM, and the arcs of the graph correspond to the transitions between the FSM states. Next to each arc, the input vector that initiates this transition is written, and after a slash, the output vector that is formed at this transition is written. A hyphen (‘-’) in an input or output vector indicates a don’t care value.

The specification for FSM synthesis is often described as a transition list, as shown in

Table 1. Transition list for the Mealy FSM from our example.

ps	X(ps, ns)	ns	Y(ps, ns)
s0	--0	s1	001
s0	--1	s3	111
s1	-0-	s2	010
s1	-1-	s3	111
s2	0--	s4	011
s2	1--	s3	111
s3	000	s3	111
s3	111	s0	101
s4	-00	s3	111
s4	-11	s0	100

, where ps (present state) is the initial state of the transition, ns (next state) is the final state of the transition, X(ps, ns) is the input vector that initiates this transition, and Y(ps, ns) is the output vector that is formed at this transition.

Traditionally, an FSM in Verilog is described using three separate processes (state register, transition functions, and output functions), as shown in Listing 1.

Listing 1. A traditional description of the FSM from our example.

module Mealy_3proc (  // declaration of ports  input clk, reset,      // clock and reset signals  input [2:0] x,     // input vector  output reg [2:0] y);   // output vector  reg [2:0] state, next;  // state variables  localparam [2:0] s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4; // states  always @(posedge clk, negedge reset)   // state register   if (~reset)  state <= s0;   else      state <= next;  always @(*)    // description of transition functions   case (state)    s0: casex (x)          3′b??0:  next = s1;         3′b??1:  next = s3;     endcase   s1: casex (x)          3′b?0?:  next = s2;         3′b?1?:  next = s3;     endcase   s2: casex (x)          3′b0??:  next = s4;         3′b1??:  next = s3;     endcase   s3: casex (x)          3′b000:  next = s3;         3′b111:  next = s0;     endcase   s4: casex (x)          3′b?00:  next = s3;         3′b?11:  next = s0;     endcase   endcase  always @(*)    // description of output functions   case (state)    s0: casex (x)          3′b??0:  y = 3′b001;         3′b??1:  y = 3′b111;     endcase   s1: casex (x)          3′b?0?:  y = 3′b010;         3′b?1?:  y = 3′b111;     endcase   s2: casex (x)          3′b0??:  y = 3′b011;         3′b1??:  y = 3′b111;     endcase   s3: casex (x)          3′b000:  y = 3′b111;         3′b111:  y = 3′b101;     endcase   s4: casex (x)          3′b?00:  y = 3′b111;         3′b?11:  y = 3′b100;     endcase   endcase endmodule

In Listing 1, the input and output functions are described using ‘case’ statements, which are arranged on two levels. First-level ‘case’ statements check the variable state (the code of the present state) and, depending on its value, determine the necessary actions in each state. The second-level ‘case’ statements check the input vector x and, depending on its value, calculate the value of the variable next (the code of the next state) in the second process and the value of the variable y (the value of the output vector) in the third process.

Considering that ‘case’ and ‘if’ statements are interchangeable in Verilog, an ‘if-else-if’ chain can be used instead of a ‘case’ statement throughout the proposed approach. In this article, we use the ‘case’ statement for clarity.

3.2. Creating Code in Verilog to Optimize an FSM Circuit

The proposed approach is based on the following assumptions:

• Reducing the number of transitions in the FSM description leads to a decrease in the area and an increase in the performance of the synthesized FSM circuit;
• Specifying default values for the variables next and y reduces the number of transitions in the FSM description.

In the proposed approach, combinational circuits λ and δ are described as ‘begin-end’ blocks of the ‘always’ procedure. In the ‘begin-end’ block, the variables next and y are first assigned default values using a blocking assignment operator (‘=’), followed by a ‘case’ statement describing the logic of combinational circuits λ and δ. The descriptions of combinational circuits λ and δ do not include assignments to the variables next and y of values that were previously defined as default values.

The default value for the variable next is selected as the state of the FSM in which the largest number of transitions ends. If there are several such states, the state whose code contains the largest number of ones is selected. The default value for the variable y is selected as the output vector that is most frequently formed at the transitions of the FSM. If there are several such output vectors, the vector that contains the largest number of ones is selected.

Let the FSM be specified by the transition list, as shown in Table 1. Then, the creation of the Verilog code for optimizing the parameters (area and performance) of the FSM can be represented as Algorithm 1.

Algorithm 1. Creating FSM code in Verilog to optimize the synthesized circuit

If the state codes are not defined, perform Algorithm 2 for state encoding to optimize the parameters of the FSM. Find the state smax that occurs most frequently in the ns column of the transition list. If there are several such states, select the state with the largest number of ones in the state code. Find the output vector ymax that occurs most often in the Y(ps, ns) column of the transition list. If there are several such output vectors, select the vector that contains the largest number of ones. Describe the ports, state variables, state codes, and state register of the FSM in the traditional way. Describe the transition functions (combinational circuit λ) of the FSM using the ‘begin-end’ block of the ‘always’ procedure. At the beginning of the ‘begin-end’ block, use the blocking assignment operator (‘=’) to assign the value smax to the variable next. This is followed by ‘case’ statements describing the logic of the transition functions, in which the ‘case’ statements do not assign the state smax to the variable next. Similarly, describe the output functions (combinational circuit δ), where assign the output vector ymax to the variable y at the beginning of the ‘begin-end’ block, and the ‘case’ statements do not assign the output vector ymax to the variable y. End.

Algorithm 2 for encoding states to optimize the FSM parameters is based on the assumption that assigning the code with the minimum number of ones to the state that occurs most frequently in the ns column of the transition list helps to reduce the area and increase the performance of the FSM.

Algorithm 2. Encoding states to optimize FSM parameters

Define the set K of binary codes for the FSM states, where $\left|K\right|=2^R, R=⌈{\log }_{2}M⌉, \left|A\right|$ is the cardinality of set A, and ⌈B⌉ is the smallest integer greater than or equal to B. Assign the initial state s0 the zero code k0: s0 ← k0; assume S:= S\{s0}, K:= K\{k0}.

while (|S|!= 0) do

3. In the set S, find the state si that occurs most frequently in the column ns of the transition list.  4. In the set K, find the code kj with the minimum number of ones.  5. Assign the code kj to the state si: si ← kj; assume S:= S\{si}, K:= K\{kj}.

end while.

Let us consider applying Algorithm 1 to describe the FSM from our example. Suppose that the state codes are not specified, so Algorithm 2 is performed. For our example, M = 5, R = 3, and |K| = 8. We assign the zero code ‘000’ to the initial state s₀. State s₃ in column ns of Table 1 occurs most frequently, so we assign state s₃ the code ‘001’ with the smallest number of ones. States s₁, s₂, and s₄ in column ns of Table 1 occur only once, so we assign them the codes ‘010’, ‘100’, and ‘011’, sequentially.

In step 2 of Algorithm 1, we select state s₃ as the s_max state, which occurs most often in column ns of Table 1. Similarly, in step 3 of Algorithm 1, we select vector ‘111’ as the output vector y_max, which occurs most frequently in column Y(ps, ns) of Table 1. Executing steps 4–6 of Algorithm 1 results in the construction of the FSM project code, which is shown in Listing 2.

Listing 2. Description of the FSM for parameter optimization.

module Mealy_3proc (  // declaration of ports  input clk, reset,    // clock and reset signals  input [2:0] x,      // input vector  output reg [2:0] y);    // output vector  reg [2:0] state, next;  // state variables  localparam [2:0] s0 = 3′b000,      // state codes s1 = 3′b010, s2 = 3′b100, s3 = 3′b001, s4 = 3′b011;   always @(posedge clk, negedge reset) // state register   if (~reset)    state <= s0;   else     state <= next;  always @(*)  // description of transition functions  begin   next = s3;  // default value for the next variable   case (state)    s0: casex (x)          3′b??0: next = s1;    endcase   s1: casex (x)          3′b?0?: next = s2;    endcase   s2: casex (x)          3′b0??: next = s4;    endcase   s3: casex (x)          3′b111: next = s0;    endcase   s4: casex (x)          3′b?11: next = s0;    endcase   endcase  end always @(*)    // description of output functions  begin   y = 3′b111; // default value for the y variable   case (state)    s0: casex (x)          3′b??0: y = 3′b001;    endcase   s1: casex (x)          3′b?0?: y = 3′b010;    endcase   s2: casex (x)          3′b0??: y = 3′b011;    endcase   s3: casex (x)          3′b111: y = 3′b101;    endcase   s4: casex (x)          3′b?11: y = 3′b100;    endcase   endcase  end endmodule

The description of FSMs, where default values are defined for both the next and y variables (as in Listing 2), is called the dstate_out (default state and output) style. Let us define two more description styles for optimizing FSM parameters: dstate and dout. In the dstate (default state) style, the default value is defined only for the variable next, and in the dout (default output) style, the default value is defined only for the variable y. Thus, we have four styles for describing FSMs: 3proc (Listing 1), dstate, dout, and dstate_out (Listing 2).

The results of implementing the FSM from our example using the Quartus Prime design tool version 24.1 in the Cyclone 10 LP family FPGA for different description styles are shown in

Table 2. Parameters of the FSM designs from our example for different description styles.

FSM	A	F
Mealy_3proc	24	181
Mealy_dstate	16	543
Mealy_dout	19	237
Mealy_dstate_out	11	651

, where A is the number of look-up tables (LUTs) in the FSM circuit (area) and F is the maximum operating frequency (in megahertz) of the FSM (performance).

Table 2 shows that the dstate, dout, and dstate_out styles significantly outperform the traditional 3proc style for describing FSMs in both area and performance. At the same time, the most significant FSM parameter optimization is achieved with the dstate_out style, followed by the dstate and dout styles. Note that the results of both the functional and timing simulations for all FSM description styles are entirely identical.

The optimization of combinational circuits λ and δ in the dstate_out style is explained by the fact that the synthesizer of a design tool only generates the logic that is explicitly defined in ‘case’ statements, since the default value has already been described earlier using the blocking assignment statement (‘=’) in the corresponding ‘begin-end’ block before the first-level ‘case’ statement. As a result, the logic of combinational circuits λ and δ is simplified, the area is reduced, and the performance of FSMs is increased.

Applying the proposed approach results in the generation of project code in which the assignment of values to the variables next and y in second-level ‘case’ statements is not defined for all possible combinations of input variables (such ‘case’ statements are marked as incomplete by the synthesizer). The traditional solution to this problem is for the synthesizer to automatically insert latches into the project circuit to save the previous values of the variables next and y. However, when using the Quartus Synthesizer, assigning default values to the variables next and y using a blocking assignment statement before the first-level ‘case’ statements allows us to avoid introducing latches into the FSM circuit.

A significant difference between the proposed approach and the known methods for describing FSMs and recommendations from developers of design tool synthesizers is that the default values for the variables next and y are not assigned using ‘default’ (for ‘case’ statements) or ‘else’ (for ‘if’ statements) constructs, but rather by using a blocking assignment statement in a ‘begin-end’ block before the first-level ‘case’ statement. Reference [28] also points out the possibility of assigning default values before ‘case’ and ‘if’ statements. However, reference [28] does not aim to optimize the FSM circuit; the initial or undefined state is used as the default value for the variable next, and the zero vector is used for the variable y. Of course, the proposed approach depends on the synthesizer of a design tool.

One disadvantage of the proposed approach is that the synthesizer generates messages about incomplete ‘case’ statements that do not affect the synthesis or simulation results. In addition, in the case of incomplete ‘case’ statements, the Vivado Synthesizer introduces latches to hold the values of the next and y variables.

The proposed approach has proven highly effective for describing FSMs in SystemVerilog. It can be assumed that the strategy under consideration will also be effective when using VHDL. However, the latter assumption requires further research.

4. Experimental Results

The FSM description styles—3proc, dstate, dout, and dstate_out—were evaluated using FSM benchmarks from the Microelectronics Center of North Carolina (MCNC) [29]. The FSMs were implemented on the Cyclone 10 LP FPGA family using the Quartus design tool, version 24.1. The FSM area was measured by counting the number of look-up tables (LUTs) used in the FSM circuit, while the maximum operating frequency assessed performance. The states of the FSMs were encoded using one-hot and binary codes. All parameters of FSMs are given after the complete implementation of the FSM in the FPGA, i.e., after synthesis, placement, and routing.

4.1. FSM Parameters and Efficiency Estimates of the Proposed Description Styles

Table 3. Parameters and effectiveness estimates of FSM description styles.

FSM	L	N	T	M	Ts	To	λs	λo	λso
bbsse	7	7	56	16	28	14	1.500	1.250	1.750
beecount	3	4	28	7	12	19	1.429	1.679	2.107
cse	7	7	91	16	47	31	1.516	1.341	1.857
dk14	3	5	56	7	13	6	1.232	1.107	1.339
dk16	2	3	108	27	9	34	1.083	1.315	1.398
dk512	1	3	30	15	6	17	1.200	1.567	1.767
ex1	9	19	233	18	45	32	1.193	1.137	1.330
ex2	2	2	72	18	32	59	1.444	1.819	2.264
ex3	2	2	36	10	16	30	1.444	1.833	2.278
ex4	6	9	21	14	4	6	1.190	1.286	1.476
ex5	2	2	32	9	15	18	1.469	1.563	2.031
ex6	5	8	34	8	10	7	1.294	1.206	1.500
ex7	2	2	36	10	18	23	1.500	1.639	2.139
keyb	7	2	170	19	112	111	1.659	1.653	2.312
lion	2	1	11	4	3	7	1.273	1.636	1.909
lion9	2	1	25	9	3	17	1.120	1.680	1.800
planet	7	19	115	48	8	11	1.070	1.096	1.165
planet1	7	19	115	48	8	11	1.070	1.096	1.165
pma	8	8	73	24	21	5	1.288	1.068	1.356
s1	8	6	107	20	12	12	1.112	1.112	1.224
s27	4	1	34	6	10	27	1.294	1.794	2.088
s208	11	2	153	18	99	75	1.647	1.490	2.137
s1488	8	19	251	48	121	62	1.482	1.247	1.729
sand	11	9	184	32	32	30	1.174	1.163	1.337
sse	7	7	56	16	28	14	1.500	1.250	1.750
styr	9	10	166	30	44	46	1.265	1.277	1.542
tbk	6	3	1569	32	567	1274	1.361	1.812	2.173
tma	7	6	44	20	9	4	1.205	1.091	1.295
train4	2	1	14	4	4	10	1.286	1.714	2.000
train11	2	1	25	11	5	18	1.200	1.720	1.920
Av							1.317	1.421	1.738
Max	11	19	1569	48	567	1274	1.659	1.833	2.312

presents the parameters of the studied FSM benchmarks, where L is the number of inputs, N is the number of outputs, T is the number of transitions between states, M is the number of states, Ts is the maximum number of transitions to the same state, To is the maximum number of transitions that yield the same output vector, Av denotes the arithmetic mean value of the parameter, and Max refers to the maximum value of the parameter.

The preliminary effectiveness of the proposed styles for describing FSMs can be represented using the following expressions:

$$\lambda s={\displaystyle \frac{Ts+T}{T}},$$

(1)

$$\lambda o={\displaystyle \frac{To+T}{T}},$$

(2)

$$\lambda so={\displaystyle \frac{Ts+To+T}{T}}$$

(3)

where λs is the efficiency estimate of the dstate style, λo is the efficiency estimate of the dout style, and λso is the efficiency estimate of the dstate_out style.

Efficiency here refers to reducing the area and increasing the performance of the FSM. Estimates (1)–(3) reflect how many lines the FSM description is reduced by when using the dstate, dout, and dstate_out styles compared to the traditional description, with a higher estimate for a particular FSM indicating a more efficient use of the corresponding description style for that FSM.

The values of the estimates λs, λo, and λso for the evaluated FSM benchmarks are presented in Table 3. Based on the average values of these estimates, we can propose the following hypotheses:

Hypothesis 1.

The dstate_out style is more effective than the dstate and dout styles for improving FSM parameters.

Hypothesis 2.

The dout style shows a slight advantage over the dstate style in improving the FSM parameters.

4.2. Area of FSMs

The area of the FSMs using the considered styles and encoding states with one-hot code is presented in Table 4, where A3, As, Ao, and Aso are the areas of FSMs (in the number of LUTs) described in styles 3proc, dstate, dout, and dstate_out, respectively; Amin is the minimum area value for a specific example; A3/As, A3/Ao, and A3/Aso, are the ratios of the corresponding parameters; Av and Max denote the previous values; Best is the number of best solutions when using a specific description style; and Unique is the number of unique solutions. Here, a unique solution is understood to be the best solution obtained using a particular style and cannot be achieved using other FSM description styles. In Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9, the best solutions and the parameter values Av and Max are highlighted in bold.

Table 4. Area of FSMs with one-hot encoding.

FSM	A3	As	Ao	Aso	Amin	A3/As	A3/Ao	A3/Aso
bbsse	42	27	40	27	27	1.556	1.050	1.556
beecount	42	25	36	18	18	1.680	1.167	2.333
cse	111	84	103	72	72	1.321	1.078	1.542
dk14	44	44	44	44	44	1.000	1.000	1.000
dk16	65	35	65	35	35	1.857	1.000	1.857
dk512	21	11	21	11	11	1.909	1.000	1.909
ex1	135	82	125	60	60	1.646	1.080	2.250
ex2	78	39	76	30	30	2.000	1.026	2.600
ex3	42	26	42	20	20	1.615	1.000	2.100
ex4	57	15	47	11	11	3.800	1.213	5.182
ex5	36	22	36	25	22	1.636	1.000	1.440
ex6	63	58	61	48	48	1.086	1.033	1.313
ex7	41	26	40	25	25	1.577	1.025	1.640
lion	17	11	15	9	9	1.545	1.133	1.889
lion9	57	27	56	21	21	2.111	1.018	2.714
planet	121	87	125	90	87	1.391	0.968	1.344
planet1	121	87	125	90	87	1.391	0.968	1.344
pma	147	101	145	89	89	1.455	1.014	1.652
s1	118	63	118	63	63	1.873	1.000	1.873
s27	23	23	23	23	23	1.000	1.000	1.000
s208	49	55	32	32	32	0.891	1.531	1.531
s1488	157	166	168	167	157	0.946	0.935	0.940
sand	238	152	239	134	134	1.566	0.996	1.776
sse	70	46	62	37	37	1.522	1.129	1.892
styr	212	100	197	105	100	2.120	1.076	2.019
tbk	295	151	292	112	112	1.954	1.010	2.634
tma	157	69	161	75	69	2.275	0.975	2.093
train4	19	11	17	8	8	1.727	1.118	2.375
train11	48	28	46	22	22	1.714	1.043	2.182
Av						1.661	1.055	1.930
Max						3.800	1.531	5.182
Best	3	11	3	23
Unique	1	5	0	16

Table 4. Area of FSMs with one-hot encoding.

FSM	A3	As	Ao	Aso	Amin	A3/As	A3/Ao	A3/Aso
bbsse	42	27	40	27	27	1.556	1.050	1.556
beecount	42	25	36	18	18	1.680	1.167	2.333
cse	111	84	103	72	72	1.321	1.078	1.542
dk14	44	44	44	44	44	1.000	1.000	1.000
dk16	65	35	65	35	35	1.857	1.000	1.857
dk512	21	11	21	11	11	1.909	1.000	1.909
ex1	135	82	125	60	60	1.646	1.080	2.250
ex2	78	39	76	30	30	2.000	1.026	2.600
ex3	42	26	42	20	20	1.615	1.000	2.100
ex4	57	15	47	11	11	3.800	1.213	5.182
ex5	36	22	36	25	22	1.636	1.000	1.440
ex6	63	58	61	48	48	1.086	1.033	1.313
ex7	41	26	40	25	25	1.577	1.025	1.640
lion	17	11	15	9	9	1.545	1.133	1.889
lion9	57	27	56	21	21	2.111	1.018	2.714
planet	121	87	125	90	87	1.391	0.968	1.344
planet1	121	87	125	90	87	1.391	0.968	1.344
pma	147	101	145	89	89	1.455	1.014	1.652
s1	118	63	118	63	63	1.873	1.000	1.873
s27	23	23	23	23	23	1.000	1.000	1.000
s208	49	55	32	32	32	0.891	1.531	1.531
s1488	157	166	168	167	157	0.946	0.935	0.940
sand	238	152	239	134	134	1.566	0.996	1.776
sse	70	46	62	37	37	1.522	1.129	1.892
styr	212	100	197	105	100	2.120	1.076	2.019
tbk	295	151	292	112	112	1.954	1.010	2.634
tma	157	69	161	75	69	2.275	0.975	2.093
train4	19	11	17	8	8	1.727	1.118	2.375
train11	48	28	46	22	22	1.714	1.043	2.182
Av						1.661	1.055	1.930
Max						3.800	1.531	5.182
Best	3	11	3	23
Unique	1	5	0	16

Table 4 shows that, using the dstate_out style and one-hot encoding, the average area of FSMs is reduced by a factor of 1.93 (or by 93%); the most significant decrease, by a factor of 5.182, is observed in the ex4 example. When using the dstate style, the maximum area is reduced by a factor of 3.8, also for the ex4 example. For the dout style, the maximum area is reduced by a factor of 1.531, as shown in the s208 example. Note that when using the dstate_out style, 11 of 29 cases (37.9%) show a reduction of more than a factor of 2 in area.

The area of the FSMs using the proposed styles and binary state encoding is presented in Table 5.

Table 5. Area of FSMs with binary encoding.

FSM	A3	As	Ao	Aso	Amin	A3/As	A3/Ao	A3/Aso
bbsse	60	30	63	32	30	2.000	0.952	1.875
beecount	32	19	28	15	15	1.684	1.143	2.133
cse	103	108	97	97	97	0.954	1.062	1.062
dk14	43	43	43	43	43	1.000	1.000	1.000
dk16	85	51	85	51	51	1.667	1.000	1.667
dk512	16	13	16	13	13	1.231	1.000	1.231
ex1	147	118	133	92	92	1.246	1.105	1.598
ex2	92	40	91	39	39	2.300	1.011	2.359
ex3	44	26	47	25	25	1.692	0.936	1.760
ex4	62	16	57	10	10	3.875	1.088	6.200
ex5	34	22	37	23	22	1.545	0.919	1.478
ex6	71	67	66	51	51	1.060	1.076	1.392
ex7	45	21	45	18	18	2.143	1.000	2.500
lion	11	7	10	5	5	1.571	1.100	2.200
lion9	57	16	57	14	14	3.563	1.000	4.071
planet	224	90	232	91	90	2.489	0.966	2.462
planet1	224	90	232	91	90	2.489	0.966	2.462
pma	162	272	164	269	162	0.596	0.988	0.602
s1	168	91	168	91	91	1.846	1.000	1.846
s27	10	10	10	10	10	1.000	1.000	1.000
s208	14	14	14	14	14	1.000	1.000	1.000
s1488	223	223	230	167	167	1.000	0.970	1.335
sand	257	180	258	164	164	1.428	0.996	1.567
sse	77	40	69	30	30	1.925	1.116	2.567
styr	229	108	213	108	108	2.120	1.075	2.120
tbk	303	197	302	199	197	1.538	1.003	1.523
tma	172	111	182	112	111	1.550	0.945	1.536
train4	13	7	11	5	5	1.857	1.182	2.600
train11	52	28	49	24	24	1.857	1.061	2.167
Av						1.732	1.023	1.976
Max						3.875	1.182	6.200
Best	4	13	4	22
Unique	1	6	0	14

Table 5. Area of FSMs with binary encoding.

FSM	A3	As	Ao	Aso	Amin	A3/As	A3/Ao	A3/Aso
bbsse	60	30	63	32	30	2.000	0.952	1.875
beecount	32	19	28	15	15	1.684	1.143	2.133
cse	103	108	97	97	97	0.954	1.062	1.062
dk14	43	43	43	43	43	1.000	1.000	1.000
dk16	85	51	85	51	51	1.667	1.000	1.667
dk512	16	13	16	13	13	1.231	1.000	1.231
ex1	147	118	133	92	92	1.246	1.105	1.598
ex2	92	40	91	39	39	2.300	1.011	2.359
ex3	44	26	47	25	25	1.692	0.936	1.760
ex4	62	16	57	10	10	3.875	1.088	6.200
ex5	34	22	37	23	22	1.545	0.919	1.478
ex6	71	67	66	51	51	1.060	1.076	1.392
ex7	45	21	45	18	18	2.143	1.000	2.500
lion	11	7	10	5	5	1.571	1.100	2.200
lion9	57	16	57	14	14	3.563	1.000	4.071
planet	224	90	232	91	90	2.489	0.966	2.462
planet1	224	90	232	91	90	2.489	0.966	2.462
pma	162	272	164	269	162	0.596	0.988	0.602
s1	168	91	168	91	91	1.846	1.000	1.846
s27	10	10	10	10	10	1.000	1.000	1.000
s208	14	14	14	14	14	1.000	1.000	1.000
s1488	223	223	230	167	167	1.000	0.970	1.335
sand	257	180	258	164	164	1.428	0.996	1.567
sse	77	40	69	30	30	1.925	1.116	2.567
styr	229	108	213	108	108	2.120	1.075	2.120
tbk	303	197	302	199	197	1.538	1.003	1.523
tma	172	111	182	112	111	1.550	0.945	1.536
train4	13	7	11	5	5	1.857	1.182	2.600
train11	52	28	49	24	24	1.857	1.061	2.167
Av						1.732	1.023	1.976
Max						3.875	1.182	6.200
Best	4	13	4	22
Unique	1	6	0	14

Table 5 shows that with binary encoding and the use of the dstate_out style, the average area of FSMs is reduced by a factor of 1.976 (or 97.6%), with the maximum area reduction by a factor of 6.2 in example ex4. For the dstate style, the maximum decrease in area by a factor of 3.875 is also observed for the ex4 benchmark. In the dout style, the most significant reduction in the area observed is a factor of 1.182 in the train4 example. Note that when using the dstate_out style, in 12 out of 29 examples (41.4% of cases), the area decreased by more than two times.

4.3. Performance of FSMs

The performance of the FSMs using the proposed styles and one-hot state encoding is shown in Table 6, where F3, Fs, Fo, and Fso are the maximum operating frequencies of FSMs (in megahertz), described in styles 3proc, dstate, dout, and dstate_out, respectively; Fmax is the maximum performance value for a specific example; Fs/F3, Fo/F3, Fs/F3, and Fso/F3 are the ratios of the corresponding parameters; and Av, Max, Best, and Unique denote the previous values.

Table 6. Performance of FSMs with one-hot encoding.

FSM	F3	Fs	Fo	Fso	Fmax	Fs/F3	Fo/F3	Fso/F3
bbsse	476	609	550	650	650	1.279	1.155	1.366
beecount	200	522	165	623	623	2.610	0.825	3.115
cse	144	512	161	505	512	3.556	1.118	3.507
dk14	511	511	511	511	511	1.000	1.000	1.000
dk16	527	648	527	648	648	1.230	1.000	1.230
dk512	734	812	734	812	812	1.106	1.000	1.106
ex1	305	521	222	511	521	1.708	0.728	1.675
ex2	467	623	467	728	728	1.334	1.000	1.559
ex3	476	546	476	657	657	1.147	1.000	1.380
ex4	604	1300	615	1300	1300	2.152	1.018	2.152
ex5	500	689	500	656	689	1.378	1.000	1.312
ex6	218	502	196	559	559	2.303	0.899	2.564
ex7	475	523	475	667	667	1.101	1.000	1.404
lion	489	733	485	734	734	1.499	0.992	1.501
lion9	180	552	149	567	567	3.067	0.828	3.150
planet	733	724	700	727	733	0.988	0.955	0.992
planet1	733	724	700	727	733	0.988	0.955	0.992
pma	106	453	87	466	466	4.274	0.821	4.396
s1	426	532	426	532	532	1.249	1.000	1.249
s27	557	557	541	541	557	1.000	0.971	0.971
s208	440	481	456	456	481	1.093	1.036	1.036
s1488	436	434	419	485	485	0.995	0.961	1.112
sand	154	447	277	466	466	2.903	1.799	3.026
sse	505	506	505	531	531	1.002	1.000	1.051
styr	168	524	184	618	618	3.119	1.095	3.679
tbk	320	372	320	436	436	1.163	1.000	1.363
tma	142	461	147	475	475	3.246	1.035	3.345
train4	207	809	291	690	809	3.908	1.406	3.333
train11	363	524	271	555	555	1.444	0.747	1.529
Av						1.857	1.012	1.934
Max						4.274	1.799	4.396
Best	4	11	1	21
Unique	2	6	0	16

Table 6. Performance of FSMs with one-hot encoding.

FSM	F3	Fs	Fo	Fso	Fmax	Fs/F3	Fo/F3	Fso/F3
bbsse	476	609	550	650	650	1.279	1.155	1.366
beecount	200	522	165	623	623	2.610	0.825	3.115
cse	144	512	161	505	512	3.556	1.118	3.507
dk14	511	511	511	511	511	1.000	1.000	1.000
dk16	527	648	527	648	648	1.230	1.000	1.230
dk512	734	812	734	812	812	1.106	1.000	1.106
ex1	305	521	222	511	521	1.708	0.728	1.675
ex2	467	623	467	728	728	1.334	1.000	1.559
ex3	476	546	476	657	657	1.147	1.000	1.380
ex4	604	1300	615	1300	1300	2.152	1.018	2.152
ex5	500	689	500	656	689	1.378	1.000	1.312
ex6	218	502	196	559	559	2.303	0.899	2.564
ex7	475	523	475	667	667	1.101	1.000	1.404
lion	489	733	485	734	734	1.499	0.992	1.501
lion9	180	552	149	567	567	3.067	0.828	3.150
planet	733	724	700	727	733	0.988	0.955	0.992
planet1	733	724	700	727	733	0.988	0.955	0.992
pma	106	453	87	466	466	4.274	0.821	4.396
s1	426	532	426	532	532	1.249	1.000	1.249
s27	557	557	541	541	557	1.000	0.971	0.971
s208	440	481	456	456	481	1.093	1.036	1.036
s1488	436	434	419	485	485	0.995	0.961	1.112
sand	154	447	277	466	466	2.903	1.799	3.026
sse	505	506	505	531	531	1.002	1.000	1.051
styr	168	524	184	618	618	3.119	1.095	3.679
tbk	320	372	320	436	436	1.163	1.000	1.363
tma	142	461	147	475	475	3.246	1.035	3.345
train4	207	809	291	690	809	3.908	1.406	3.333
train11	363	524	271	555	555	1.444	0.747	1.529
Av						1.857	1.012	1.934
Max						4.274	1.799	4.396
Best	4	11	1	21
Unique	2	6	0	16

Table 6 shows that when using the dstate_out style and one-hot encoding, the average performance improves by a factor of 1.934 (or 93.4%), with the maximum performance increase by a factor of 4.396 in the pma example. For the dstate style, the highest performance increase noted is a factor of 4.274, again for the pma example. In contrast, the dout style highlights a maximum performance increase of 1.799 for the sand example. Notably, in 10 of 30 cases (33.3%), performance improved by more than 2 times, and in 8 cases (26.7%) by more than 3 times.

The performance of the FSMs using the offered styles and binary state encoding is shown in Table 7.

Table 7. Performance of FSMs with binary encoding.

FSM	F3	Fs	Fo	Fso	Fmax	Fs/F3	Fo/F3	Fso/F3
bbsse	333	536	334	447	536	1.003	1.610	1.342
beecount	658	789	608	598	789	0.924	1.199	0.909
cse	155	249	217	310	310	1.400	1.606	2.000
dk14	480	780	480	480	780	1.000	1.625	1.000
dk16	380	378	380	378	380	1.000	0.995	0.995
dk512	578	552	578	552	578	1.000	0.955	0.955
ex1	240	273	244	337	337	1.017	1.138	1.404
ex2	219	272	298	404	404	1.361	1.242	1.845
ex3	233	388	239	531	531	1.026	1.665	2.279
ex4	419	450	419	731	731	1.000	1.074	1.745
ex5	335	335	335	500	500	1.000	1.000	1.493
ex6	226	412	232	433	433	1.027	1.823	1.916
ex7	222	453	230	501	501	1.036	2.041	2.257
lion	677	486	664	814	814	0.981	0.718	1.202
lion9	209	435	209	590	590	1.000	2.081	2.823
planet	238	295	226	296	296	0.950	1.239	1.244
planet1	238	295	226	296	296	0.950	1.239	1.244
pma	111	165	92	219	219	0.829	1.486	1.973
s1	249	296	249	296	296	1.000	1.189	1.189
s27	240	540	537	537	540	2.238	2.250	2.238
s208	716	716	721	721	721	1.007	1.000	1.007
s1488	221	221	223	480	480	1.009	1.000	2.172
sand	211	209	192	239	239	0.910	0.991	1.133
sse	488	353	446	462	488	0.914	0.723	0.947
styr	203	317	184	317	317	0.906	1.562	1.562
tbk	210	237	210	202	237	1.000	1.129	0.962
tma	119	277	151	326	326	1.269	2.328	2.739
train4	262	474	271	816	816	1.034	1.809	3.115
train11	230	385	310	490	490	1.348	1.674	2.130
Av						1.074	1.393	1.649
Max						2.238	2.328	3.115
Best	3	7	3	21
Unique	1	5	0	18

Table 7. Performance of FSMs with binary encoding.

FSM	F3	Fs	Fo	Fso	Fmax	Fs/F3	Fo/F3	Fso/F3
bbsse	333	536	334	447	536	1.003	1.610	1.342
beecount	658	789	608	598	789	0.924	1.199	0.909
cse	155	249	217	310	310	1.400	1.606	2.000
dk14	480	780	480	480	780	1.000	1.625	1.000
dk16	380	378	380	378	380	1.000	0.995	0.995
dk512	578	552	578	552	578	1.000	0.955	0.955
ex1	240	273	244	337	337	1.017	1.138	1.404
ex2	219	272	298	404	404	1.361	1.242	1.845
ex3	233	388	239	531	531	1.026	1.665	2.279
ex4	419	450	419	731	731	1.000	1.074	1.745
ex5	335	335	335	500	500	1.000	1.000	1.493
ex6	226	412	232	433	433	1.027	1.823	1.916
ex7	222	453	230	501	501	1.036	2.041	2.257
lion	677	486	664	814	814	0.981	0.718	1.202
lion9	209	435	209	590	590	1.000	2.081	2.823
planet	238	295	226	296	296	0.950	1.239	1.244
planet1	238	295	226	296	296	0.950	1.239	1.244
pma	111	165	92	219	219	0.829	1.486	1.973
s1	249	296	249	296	296	1.000	1.189	1.189
s27	240	540	537	537	540	2.238	2.250	2.238
s208	716	716	721	721	721	1.007	1.000	1.007
s1488	221	221	223	480	480	1.009	1.000	2.172
sand	211	209	192	239	239	0.910	0.991	1.133
sse	488	353	446	462	488	0.914	0.723	0.947
styr	203	317	184	317	317	0.906	1.562	1.562
tbk	210	237	210	202	237	1.000	1.129	0.962
tma	119	277	151	326	326	1.269	2.328	2.739
train4	262	474	271	816	816	1.034	1.809	3.115
train11	230	385	310	490	490	1.348	1.674	2.130
Av						1.074	1.393	1.649
Max						2.238	2.328	3.115
Best	3	7	3	21
Unique	1	5	0	18

Table 7 shows that when using the dstate_out style and binary encoding, the average performance improves by 1.649 (64.9%), with the maximum performance increase of 3.115 in the train4 example. For the dstate style, the maximum performance increase reaches a factor of 2.238 in the s27 example, while the dout style achieves a maximum improvement factor of 2.328 in the tma example. Notably, in 9 out of 29 examples (31% of cases), the performance improves by more than double.

The effectiveness of the considered styles, as measured by the number of best and unique solutions achieved, is illustrated in Figure 3 and Figure 4.

Figure 3 and Figure 4 demonstrate that the dstate_out and dstate styles significantly outperform the 3proc and dout styles in terms of the number of best and unique solutions achieved.

The analysis in Table 4, Table 5, Table 6 and Table 7 of the average values (parameter Av) of the area and performance ratios indicates that Hypothesis 1 was fully confirmed. In contrast, Hypothesis 2 was confirmed only with respect to performance when encoding FSMs with binary codes.

Note that the high efficiency of the considered approach has been confirmed for both minimum (binary) and maximum (one-hot) length codes. Therefore, the efficiency of the proposed approach for reducing the area and enhancing the performance of FSMs is independent of the method of state encoding.

4.4. Research on the Effectiveness of the Proposed Approach in the Vivado Design Tool

All of the experimental results presented above were obtained using the Quartus Prime system. Section 3 noted that the proposed approach depends on the synthesizer used by the design tool. For comparison, Table 8 and Table 9 present the results of experimental studies of the proposed approach performed using the Vivado design tool version 2025.1 when implementing FSMs in the Artix 7 family of FPGAs.

Table 8. Area of FSMs with one-hot encoding in the system Vivado.

FSM	A3	As	Ao	Aso	Amin	A3/As	A3/Ao	A3/Aso
bbsse	29	22	30	23	22	1.318	0.967	1.261
beecount	8	16	10	14	8	0.500	0.800	0.571
cse	51	49	47	37	37	1.041	1.085	1.378
dk14	21	21	21	20	20	1.000	1.000	1.050
dk16	39	17	42	15	15	2.294	0.929	2.600
dk512	13	7	11	6	6	1.857	1.182	2.167
ex1	58	37	72	44	37	1.568	0.806	1.318
ex2	10	8	9	7	7	1.250	1.111	1.429
ex3	10	8	9	7	7	1.250	1.111	1.429
ex4	11	12	13	14	11	0.917	0.846	0.786
ex5	8	8	8	7	7	1.000	1.000	1.143
ex6	25	24	25	23	23	1.042	1.000	1.087
ex7	4	4	4	4	4	1.000	1.000	1.000
lion	3	2	3	2	2	1.500	1.000	1.500
lion9	11	14	11	10	10	0.786	1.000	1.100
planet	83	50	88	52	50	1.660	0.943	1.596
planet1	83	50	88	52	50	1.660	0.943	1.596
pma	35	52	63	74	35	0.673	0.556	0.473
s1	63	34	63	34	34	1.853	1.000	1.853
s27	119	130	120	130	119	0.915	0.992	0.915
s208	10	11	9	13	9	0.909	1.111	0.769
s1488	7	7	7	6	6	1.000	1.000	1.167
sand	94	98	87	83	83	0.959	1.080	1.133
sse	25	23	26	23	23	1.087	0.962	1.087
styr	88	53	98	53	53	1.660	0.898	1.660
tbk	128	156	116	153	116	0.821	1.103	0.837
tma	26	41	48	56	26	0.634	0.542	0.464
train4	13	14	11	10	10	0.929	1.182	1.300
train11	5	5	4	3	3	1.000	1.250	1.667
Av						1.175	0.979	1.253
Max						2.294	1.250	2.600
Best	6	9	3	18
Unique	5	4	2	13

Table 8. Area of FSMs with one-hot encoding in the system Vivado.

FSM	A3	As	Ao	Aso	Amin	A3/As	A3/Ao	A3/Aso
bbsse	29	22	30	23	22	1.318	0.967	1.261
beecount	8	16	10	14	8	0.500	0.800	0.571
cse	51	49	47	37	37	1.041	1.085	1.378
dk14	21	21	21	20	20	1.000	1.000	1.050
dk16	39	17	42	15	15	2.294	0.929	2.600
dk512	13	7	11	6	6	1.857	1.182	2.167
ex1	58	37	72	44	37	1.568	0.806	1.318
ex2	10	8	9	7	7	1.250	1.111	1.429
ex3	10	8	9	7	7	1.250	1.111	1.429
ex4	11	12	13	14	11	0.917	0.846	0.786
ex5	8	8	8	7	7	1.000	1.000	1.143
ex6	25	24	25	23	23	1.042	1.000	1.087
ex7	4	4	4	4	4	1.000	1.000	1.000
lion	3	2	3	2	2	1.500	1.000	1.500
lion9	11	14	11	10	10	0.786	1.000	1.100
planet	83	50	88	52	50	1.660	0.943	1.596
planet1	83	50	88	52	50	1.660	0.943	1.596
pma	35	52	63	74	35	0.673	0.556	0.473
s1	63	34	63	34	34	1.853	1.000	1.853
s27	119	130	120	130	119	0.915	0.992	0.915
s208	10	11	9	13	9	0.909	1.111	0.769
s1488	7	7	7	6	6	1.000	1.000	1.167
sand	94	98	87	83	83	0.959	1.080	1.133
sse	25	23	26	23	23	1.087	0.962	1.087
styr	88	53	98	53	53	1.660	0.898	1.660
tbk	128	156	116	153	116	0.821	1.103	0.837
tma	26	41	48	56	26	0.634	0.542	0.464
train4	13	14	11	10	10	0.929	1.182	1.300
train11	5	5	4	3	3	1.000	1.250	1.667
Av						1.175	0.979	1.253
Max						2.294	1.250	2.600
Best	6	9	3	18
Unique	5	4	2	13

Table 9. Area of FSMs with binary encoding in the system Vivado.

FSM	A3	As	Ao	Aso	Amin	A3/As	A3/Ao	A3/Aso
bbsse	29	22	30	23	22	1.318	0.967	1.261
beecount	8	8	10	9	8	1.000	0.800	0.889
cse	51	49	47	37	37	1.041	1.085	1.378
dk14	11	10	11	9	9	1.100	1.000	1.222
dk16	15	7	15	7	7	2.143	1.000	2.143
dk512	4	2	4	2	2	2.000	1.000	2.000
ex1	58	37	72	44	37	1.568	0.806	1.318
ex2	6	6	6	5	5	1.000	1.000	1.200
ex3	6	5	7	6	5	1.200	0.857	1.000
ex4	11	12	13	14	11	0.917	0.846	0.786
ex5	5	5	5	5	5	1.000	1.000	1.000
ex6	25	24	25	23	23	1.042	1.000	1.087
ex7	5	4	5	4	4	1.250	1.000	1.250
lion	3	2	3	2	2	1.500	1.000	1.500
lion9	4	6	5	5	4	0.667	0.800	0.800
planet	83	50	88	52	50	1.660	0.943	1.596
planet1	83	50	88	52	50	1.660	0.943	1.596
pma	35	52	63	74	35	0.673	0.556	0.473
s1	63	34	63	34	34	1.853	1.000	1.853
s27	119	130	120	130	119	0.915	0.992	0.915
s208	10	11	9	13	9	0.909	1.111	0.769
s1488	7	7	7	6	6	1.000	1.000	1.167
sand	94	98	87	83	83	0.959	1.080	1.133
sse	25	23	26	23	23	1.087	0.962	1.087
styr	88	53	98	53	53	1.660	0.898	1.660
tbk	128	156	116	153	116	0.821	1.103	0.837
tma	26	41	48	56	26	0.634	0.542	0.464
train4	6	6	6	5	5	1.000	1.000	1.200
train11	4	2	3	2	2	2.000	1.333	2.000
Av						1.227	0.953	1.227
Max						2.143	1.333	2.143
Best	7	15	3	16
Unique	5	4	2	7

Table 9. Area of FSMs with binary encoding in the system Vivado.

FSM	A3	As	Ao	Aso	Amin	A3/As	A3/Ao	A3/Aso
bbsse	29	22	30	23	22	1.318	0.967	1.261
beecount	8	8	10	9	8	1.000	0.800	0.889
cse	51	49	47	37	37	1.041	1.085	1.378
dk14	11	10	11	9	9	1.100	1.000	1.222
dk16	15	7	15	7	7	2.143	1.000	2.143
dk512	4	2	4	2	2	2.000	1.000	2.000
ex1	58	37	72	44	37	1.568	0.806	1.318
ex2	6	6	6	5	5	1.000	1.000	1.200
ex3	6	5	7	6	5	1.200	0.857	1.000
ex4	11	12	13	14	11	0.917	0.846	0.786
ex5	5	5	5	5	5	1.000	1.000	1.000
ex6	25	24	25	23	23	1.042	1.000	1.087
ex7	5	4	5	4	4	1.250	1.000	1.250
lion	3	2	3	2	2	1.500	1.000	1.500
lion9	4	6	5	5	4	0.667	0.800	0.800
planet	83	50	88	52	50	1.660	0.943	1.596
planet1	83	50	88	52	50	1.660	0.943	1.596
pma	35	52	63	74	35	0.673	0.556	0.473
s1	63	34	63	34	34	1.853	1.000	1.853
s27	119	130	120	130	119	0.915	0.992	0.915
s208	10	11	9	13	9	0.909	1.111	0.769
s1488	7	7	7	6	6	1.000	1.000	1.167
sand	94	98	87	83	83	0.959	1.080	1.133
sse	25	23	26	23	23	1.087	0.962	1.087
styr	88	53	98	53	53	1.660	0.898	1.660
tbk	128	156	116	153	116	0.821	1.103	0.837
tma	26	41	48	56	26	0.634	0.542	0.464
train4	6	6	6	5	5	1.000	1.000	1.200
train11	4	2	3	2	2	2.000	1.333	2.000
Av						1.227	0.953	1.227
Max						2.143	1.333	2.143
Best	7	15	3	16
Unique	5	4	2	7

Table 8 shows that using the dstate_out style of FSM description with one-hot encoding results in an average area reduction of 1.253 times (or 25.3%). The most significant area reduction, 2.6 times, is observed in the example dk16. Similarly, Table 9 shows that using the dstate_out style of FSM description with binary encoding results in an average area reduction of 1.227 times (or 22.7%), and the most significant reduction, 2.143 times, is also observed in the example dk16.

When using the proposed approach, even after assigning default values to the variables next and y before the ‘case’ statements, the synthesizer in Vivado introduces latches if the ‘case’ statements for next and y do not define values for all possible combinations of input variables. The introduction of latches into the FSM circuit prevents the maximum operating frequency of the FSMs from being calculated. Therefore, there is no data on the performance of the FSMs here. However, despite the Vivado Synthesizer introducing latches into the FSM circuit, the proposed approach reduces the average area of FSMs, allowing us to draw the following conclusion.

Inference. Introducing latches into the FSM circuit requires fewer area resources than the proposed approach for minimizing FSM logic. In other words, regardless of the synthesizer used, the proposed approach significantly reduces the area of FSMs.

4.5. Comparison of the Proposed Approach with Known Methods

Table 10. Reducing the area and increasing performance in various methods of FSM optimization.

Methods	Area		Performance
	Av	Max	Av	Max
[1]	79.6%	-	22.4%	-
[2]	15.0%	-	8%	-
[3]	25.0%	-	-	-
[4]	30.0%	-	-	-
[5]	30.0%	-	-	-
[6]	25.8%	100%	-	-
[8]	50.0%	-	-	-
[9]	5.0%	-	-	-
[10]	67.0%	-	-	-
[11]	30.0%	-	-	-
[12]	87.0%	-	-	-
[13]	50.6%	-	19.7%	-
[25]	26.0%	3.1 times	21.0%	60%
[26]	77.4%	4.8 times	19.3%	2.4 times
[30]	3.7%	71.4%	4.4%	51.6%
Doh	93.0%	5.2 times	93.4%	4.4 times
Db	97.6%	6.2 times	64.9%	3.1 times

shows the reductions in the area and increases in the performance of FSMs reported in the literature when using various methods, as well as when applying the proposed approach, where Av and Max denote the average and maximum value of the parameter. Table 10 also presents the results obtained using the JEDI program [30] for encoding FSM states. For comparison, Table 10 presents the results obtained using the proposed approach, where Doh denotes the parameter values for one-hot encoding, and Db denotes those for binary encoding.

Table 10 shows that the proposed approach surpasses all other methods in reducing the area and improving FSM performance. Note that this approach does not replace the existing FSM optimization methods—such as state minimization, state encoding, logic minimization, and synthesis—but rather complements them. Consequently, this approach can be applied at the stage of describing the FSM project in HDL, regardless of other FSM optimization methods.

5. Conclusions

This paper introduces three styles for describing FSMs in Verilog HDL to enhance their parameters: dstate, where the default value is the next state; dout, where the default value is the output vector; and dstate_out, where the default values include both the next state and the output vector. Algorithms are presented for creating FSM project code in Verilog and encoding states to optimize the area and performance of FSMs.

Experimental studies in the Quartus design tool on MCNC benchmarks demonstrate that the dstate_out style reduces the average area of FSMs by a factor of 1.93 when states are encoded in one-hot code and by 1.976 when encoded in binary. For specific examples, this reduction can be as much as a factor of 5.182 and 6.2, respectively. Additionally, the dstate_out style enhances FSM performance by an average of 1.934 with one-hot encoding and 1.649 with binary encoding, with individual examples showing increases of up to 4.396 and 3.115, respectively.

It has been shown that the proposed approach depends on the synthesizer used in the design tool. For example, in the Vivado system, the average area reduction is 25.3% for one-hot encoding (2.6 times for individual examples) and 22.7% for binary encoding (2.143 times for individual examples). It has also been shown that the proposed approach outperforms all known methods in terms of area reduction and performance improvement of FSMs.

We recommend using the dstate_out and dstate styles to describe FSMs. We do not recommend using the dout style due to its minimal effectiveness in improving FSM parameters. Since the proposed styles can lead to incomplete ‘case’ statements, we recommend using the considered styles for describing FSMs in the final stages of design, when the user is completely confident in the correct functioning of the FSM. Traditional methods of describing FSMs can be used during the project verification stages and in complex projects.

Future research will focus on developing new styles for describing FSMs in HDL and structural models that aim to optimize FSM parameters.