Research on a High-Frequency High-Voltage Plasma Power Supply Based on SPWM Modulation

Abstract

Plasma power supplies find extensive applications across industrial, energy, environmental, and medical domains. This study addresses limitations of conventional plasma power supplies, including high harmonic current content, neutral-point potential imbalance, and manufacturing complexity. A novel design approach for high-frequency, high-voltage plasma power supplies is proposed, based on three-level sinusoidal pulse width modulation (SPWM) technology. First, the design distinctions between the input-side Boost power factor correction circuit and Diode Rectifier circuits are analyzed. Subsequently, an integrated SPWM driver-controller architecture and a design methodology for high-frequency transformers are introduced. A single-phase three-level SPWM modulation strategy is then presented. Based on this modulation technique, a high-frequency, high-voltage plasma power supply prototype incorporating air pumps and rotary motors was developed. Experimental validation demonstrated stable generation of plasma gas at a frequency of 25 kHz, with an output voltage of 10.79 kV and an output power of 1.75 kW. Results indicate that the refined power supply enhances electrical utilization efficiency, resolves neutral-point imbalance issues, and simplifies manufacturing through its integrated driver-controller design. This work offers a valuable reference for advancing high-frequency, high-voltage plasma technologies.

1. Introduction

Plasma power supplies have broad application value in industry, energy, environmental protection, and medicine due to their unique characteristics, driving advancement in related sectors. Within the industrial domain, this technology can markedly enhance the efficiency and quality of processes such as material surface modification and welding. Particularly in the context of promoting green economy development, improving the efficiency of plasma power supplies is critically important. Optimizing its efficiency involves multiple aspects, with input rectifier circuits and power inverters being especially crucial.

Diode Rectifier Circuits are structurally simple and cost-effective for low-demand applications but suffer from high input current harmonic distortion and low power factor. Power factor is defined as the ratio of real power to apparent power, reflecting the efficiency of electrical energy utilization [1]. These issues not only lead to energy wastage but also adversely affect grid power quality. Based on the preceding analysis, non-sinusoidal current waveforms can be decomposed into a fundamental component and a series of harmonic components [2]. In contrast, Boost power factor correction (PFC) rectifier circuits based on the Boost converter topology utilize periodic switching operations of power semiconductor devices to control inductor energy storage and release. This approach effectively improves power factor and significantly reduces input current harmonics [3].

For inverter modulation, three-level sinusoidal pulse width modulation (SPWM) technology offers advantages over conventional two-level modulation, including lower voltage stress on power semiconductor devices, reduced harmonic distortion, and better neutral-point potential stability [4,5]. Sinusoidal Pulse Width Modulation generates modulated signals by comparing sinusoidal reference waveforms with high-frequency triangular carriers [6]. It produces voltage waveforms more closely approximating a sinusoidal shape, effectively reducing harmonic content and improving output power quality. Furthermore, employing symmetrical SPWM modulation ensures balanced ON-state durations for positive and negative voltage levels within each switching cycle. This symmetry suppresses neutral-point potential fluctuations, effectively mitigating neutral-point imbalance, and consequently enhances the operational stability of the power supply system in plasma generators.

Regarding inverter and drive control technologies, traditional plasma power supplies are typically configured with a discrete design approach, where driver circuits and control circuits operate independently. This separation often compromises system stability and reliability due to signal transmission issues. Conversely, an integrated driver-controller design effectively simplifies circuit complexity, increases system integration, and improves operational stability.

Compared to the recent plasma power supply design by Li et al. (2023, IEEE Trans. Ind. Electron.) [7], the proposed system achieves significant advancements in integration, stability, and efficiency. While the reference utilizes a two-level inverter with a discrete driver-control architecture at 15 kHz, this work implements a three-level SPWM topology operating at 25 kHz. The higher switching frequency reduces the size of magnetic components due to the inverse relationship between frequency and inductance/capacitance requirements. Moreover, 25 kHz lies within the optimal excitation band of plasma, which minimizes discharge instability caused by frequency mismatch, thereby ensuring more stable plasma generation compared to the 15 kHz configuration in Li et al.’s work [7]. A key innovation is the integrated ARM Cortex-M4-based architecture, which reduces inter-board connections, thereby minimizing interference and enhancing reliability.

This paper aims to design and develop a high-performance plasma power supply by integrating a Boost PFC Circuit, three-level sinusoidal pulse width modulation SPWM technology, and an integrated driver-controller design. The article is structured as follows. Section 2 details the high-frequency, high-voltage plasma power supply system, presents a comparative analysis of the Boost PFC Circuit and Diode Rectifier Circuits, introduces the integrated SPWM driver-controller design and the high-frequency transformer design [8]. Section 3 elaborates on the operational principles of three-level sinusoidal pulse width modulation (SPWM) technology and conducts simulation studies. Section 4 presents the system performance optimization and prototype implementation of the SPWM-based high-frequency, high-voltage plasma power supply, including key performance enhancements and the prototype design. Section 5 presents the experimental results, including the three-level SPWM drive signals, output voltage waveform characteristics, and the overall system performance of the prototype. Section 6 summarizes the operational results and system performance of the experimental prototype and discusses its application value and development prospects in plasma technology.

2. High-Frequency High-Voltage Plasma Power Supply Design

2.1. System Architecture

To establish the basis for subsequent circuit topology selection, parameter calculation, and performance verification, this section begins by defining the system-level design constraints and core performance objectives, ensuring the relevance and feasibility of the design solution, as detailed in

Table 1. Key Performance Indicators.

Parameters	Specifications
Output power	1.7 kW
Peak Output Voltage	10 kV
Switching frequency	25 kHz

.

Figure 1 depicts the block diagram of the high-frequency, high-voltage plasma power supply system based on three-level sinusoidal pulse width modulation SPWM technology. The system primarily comprises the Boost power factor correction circuit, a three-level drive control circuit utilizing SPWM modulation, and a high-frequency transformer voltage-boosting circuit. The AC mains supply (220 V) serves as the input source. The Boost PFC Circuit rectifies the 220 V AC input into a 380 V DC voltage signal. Subsequently, the SPWM-based three-level drive control circuit converts this DC signal into a three-level SPWM voltage signal. A custom-designed high-frequency transformer, constructed with a ferrite PL-13 U-core, is integrated at the output stage of the subsequent Type I three-level half-bridge inverter circuit. The three-level SPWM voltage signal is applied to the primary side of the transformer [9]. Here, the transformer boosts the peak-to-peak 380 V three-level SPWM signal to a 10 kV high-voltage output. A rotating plasma spray gun acting as the load is connected to the transformer’s secondary side. Gas within the nozzle ionizes under this high voltage to form plasma.

The main components of this SPWM-modulated high-frequency, high-voltage plasma power supply are detailed below:

(1)

Boost PFC circuit: This stage rectifies the 220 V AC mains voltage, boosts it, and delivers a stable 380 V DC output. This DC voltage serves as the input for the subsequent Type I three-level inverter circuit.

(2)

SPWM-Based Three-Level Drive Control Circuit: This design employs an ARM Cortex-M4F 32-bit microcontroller (AT32F403ARCT7) as the core of the MCU control system. The control module MCU generates 25 kHz SPWM drive signals to switch the power semiconductor devices on and off. This action converts the 380 V DC input into an AC SPWM voltage signal.

(3)

High-Frequency Transformer Voltage-Boosting Circuit: This circuit steps up the SPWM signal to 10 kV, delivering the high-voltage output to the rotating plasma spray gun.

2.2. Boost PFC Circuit Versus Diode Rectifier

2.2.1. Conventional Topology

Diode Rectifier Circuits typically employ a large capacitor to achieve a relatively smooth DC output voltage. However, this configuration combines nonlinear components with energy storage elements. Although the input AC voltage is sinusoidal, the input AC current becomes severely distorted and exhibits a pulsed waveform. This distortion pollutes the grid and degrades the power factor.

In practical circuits where source impedance is non-negligible, the circuit current $i\left(t\right)$ and the voltage across the load $v\left(t\right)$ are jointly determined by the characteristics of both the source and the load [10,11]. Energy flow within the circuit can be bidirectional, transferring from the source to the load or vice versa. For sinusoidal AC circuits, both voltage and current are periodic functions [12]. These signals, $v\left(t\right)$ and $i\left(t\right)$, can be expanded via Fourier series into the sum of a DC component and higher-order harmonic components.

$$v\left(t\right)=V_0+{\sum }_{n=1}^{\mathrm{\infty }}{\mathrm{V}}_n\mathrm{c}\mathrm{o}\mathrm{s}(n\omega t-{\phi }_n)$$

(1)

$$i\left(t\right)=I_0+{\sum }_{n=1}^{\mathrm{\infty }}{I}_n\mathrm{c}\mathrm{o}\mathrm{s}\left(n\omega t-{\theta }_n\right)$$

(2)

Let the voltage period T be defined as:

$$T={\displaystyle \frac{2\pi }{\omega }}$$

(3)

The root mean square (RMS) value ($V_{rms}$) of a periodic voltage waveform $v\left(t\right)$ with period $T$ is given by:

$$V_{rms}=\sqrt{{\displaystyle \frac{1}{T}}{\int }_0^T{v}^2\left(t\right)dt}$$

(4)

Using Fourier series analysis, this expression expands to:

$$V_{rms}=\sqrt{V_0^2+{\sum }_{n=1}^{\mathrm{\infty }}{\displaystyle \frac{V_n^2}{2}}}$$

(5)

Similarly, the root mean square (RMS) value ($I_{rms}$) of a periodic current waveform $i\left(t\right)$ with period T is given by:

$$I_{rms}=\sqrt{I_0^2+{\sum }_{n=1}^{\mathrm{\infty }}{\displaystyle \frac{I_n^2}{2}}}$$

(6)

Non-sinusoidal current consists of a fundamental component and multiple harmonic components (integer multiples of the fundamental frequency). These harmonics are injected into the power grid, causing grid voltage distortion [13]. When harmonic content within the grid reaches excessive levels, it can interfere with other equipment connected to the same grid. This interference manifests as degraded communication signal quality, increased noise, or data corruption. Furthermore, it disrupts the normal operation of sensitive electronic devices [14]; for instance, the measurement accuracy of electronic instruments and meters may be compromised.

Power factor, a key indicator of electrical energy utilization efficiency, characterizes the matching degree between active power and apparent power in the circuit. A reduction in power factor results in excessive reactive power circulating within the circuit. This circulation generates additional losses on circuit components. Since this energy is not effectively utilized, the overall efficiency of the power supply is diminished [15]. Additionally, without power factor correction rectifier circuit compensation, the rectified DC voltage exhibits significant ripple. This ripple becomes particularly pronounced during load transients, leading to increased output voltage fluctuations. Such fluctuations are highly undesirable for electronic devices requiring a stable DC power supply, potentially causing abnormal operation or even damage.

Power factor correction rectifier circuits improve the power factor by shaping the input current waveform to more closely approximate a sinusoid, synchronizing its phase with the input voltage. This action reduces harmonic distortion, minimizes reactive power waste, and consequently enhances the power factor [16].

A Simulink simulation of the Diode Rectifier Circuit was conducted using the parameters specified in

Table 2. Diode Rectifier Simulation Parameters.

Parameters	Specifications
Input signal	AC 220 V
Simulation type	Discrete
Sampling time	1 × 10−6 s
Termination time	1 s

.

Figure 2 illustrates the simulation topology, which consists of an AC input source, four rectifier diodes, a capacitor, and a load resistor. To facilitate observation of input-output dynamics, the input current (${\mathrm{I}}_{\mathrm{A}\mathrm{C}}$), input voltage (${\mathrm{V}}_{\mathrm{A}\mathrm{C}}$), and output voltage across the load (${\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}$) were monitored using oscilloscopes.

Figure 3 displays the simulated waveforms of input current and input voltage for the Diode Rectifier Circuit. Among them, X-axis: Time (s); Y-axis: Output voltage (V). The upper trace shows the input current waveform, while the lower trace depicts the input voltage waveform [17]. The simulation results demonstrate severe distortion of the input current, manifesting as a pulsed waveform. Additionally, a significant phase deviation is observed between the input current and input voltage [18].

As shown in Figure 4, the Diode Rectifier Circuit exhibits a significant output voltage ripple with a peak-to-peak value ($U_1$) of 16.76 V.

2.2.2. Boost Power Factor Correction Circuit

As established in the preceding analysis, when AC current passes through a Diode Rectifier Circuit, the current waveform becomes severely distorted. This distortion pollutes the grid and reduces the system power factor [19]. Introducing a Boost PFC Circuit at the input side effectively mitigates this issue [20]. For non-sinusoidal circuits, the grid-side power factor (PF) is defined as:

$$PF={\displaystyle \frac{P}{S}}$$

(7)

Let P denote the real power and S represent the apparent power [21]. If the input AC voltage is sinusoidal and harmonic-free, the power factor (PF) is defined as:

$$PF={\displaystyle \frac{P}{S}}={\displaystyle \frac{U_e{I}_{e}cos\varphi }{U_{e}I}}={\displaystyle \frac{I_{e}cos\varphi }{I}}=\mu cos\varphi$$

(8)

In Equation (9), $U_{\mathrm{e}}$ and $I_{\mathrm{e}}$ represent the fundamental RMS values of voltage and current, respectively, $I$ denotes the total RMS current [22], $\varphi$ is the phase displacement angle of the fundamental component, and $\mu$ signifies the current sinusoidal factor. The sinusoidal factor $\mu$ is defined as:

$$\mu ={\displaystyle \frac{I_{\mathrm{e}}}{I}}={\displaystyle \frac{I_{\mathrm{e}}}{\sqrt{I_{\mathrm{e}}^2+{\sum }_{n=2}^{\mathrm{\infty }}{I}_n^2}}}={\displaystyle \frac{1}{\sqrt{1+TH{D}^2}}}$$

(9)

In Equation (10), THD denotes Total Harmonic Distortion [23], defined as:

$$THD=\sqrt{{\sum }_{n=2}^{\mathrm{\infty }} ({\displaystyle \frac{I_n}{I_{\mathrm{e}}}}{)}^2}$$

(10)

If the grid-side current contains no harmonics, the Total Harmonic Distortion becomes zero and the sinusoidal factor $\mu$ equals unity. Therefore, the power factor is given by [24]:

$$PF=\cos {\varphi }_1$$

(11)

The power factor correction rectifier circuit controls the switching devices’ turn-on/off states and leverages the characteristics of inductive and capacitive components, synchronizing the input current phase with the input voltage waveform [25]. This phase synchronization minimizes the voltage-current phase difference, driving the power factor toward unity. It also reduces reactive power transmission in the grid, lowering line losses and improving overall power supply efficiency. Simultaneously, the power factor correction rectifier circuit suppresses harmonic oscillations and mitigates voltage fluctuations, providing stabilized power to downstream equipment and significantly improving system stability and reliability.

Simulink simulations of the Boost PFC Circuit were performed with identical control variables and parameters (Table 1) as the Diode Rectifier for comparative analysis.

Figure 5 illustrates the Simulink simulation topology of the Boost PFC Circuit [26]. During switch turn-on, the inductor stores energy, increasing the current $I_L$ [27]. During switch turn-off, the inductor releases energy to the output through the diode, elevating the voltage $V_{out}$ [28]. PWM duty cycle regulation dynamically maintains output voltage stability by controlling energy transfer. The topology primarily comprises the Boost power factor correction rectifier main circuit and a dual-loop PI control module. This control module utilizes the output voltage signal $V_{out}$ and the full-bridge rectified current $I_L$ as negative feedback signals to adjust the input current waveform and phase for synchronization with the voltage. The dual-loop PI control module consists of three functional subsystems:

Section A: Voltage Outer Loop Control. The voltage outer loop control consists of the following three components [29]:

(1)

Input Stage: The output voltage ($V_{out}$) is compared with the reference voltage $V_{ref}$ (380 V) to generate an error signal.

(2)

Processing Stage: The error signal is regulated through a PI controller, where the PI output increases when $V_{out}$ < $V_{ref}$ and decreases otherwise.

(3)

Output Stage: The PI output serves as the reference current amplitude input for the inner current loop [30].

Section B: Input Voltage Processing. This subsystem comprises three components:

(1)

Peak Detection: The input AC voltage (VAC) is processed by a peak detection module to extract $V_{max}$, followed by computation of the reciprocal ${\displaystyle \frac{1}{V_{max}}}$.

(2)

Reference Current Generation: Multiplication of ${\displaystyle \frac{1}{V_{max}}}$ by the Boost circuit’s input voltage ($V_{in}$) and subsequently by the PI output from Section A yields the reference current $I_{ref}$ the inner current loop. This forces the current waveform to track the input voltage, enabling power factor correction [31].

Section C: Current Inner Loop Control. The current inner loop control incorporates three functional stages:

(1)

Input Stage: The reference current $I_{ref}$ is compared with the actual inductor current $I_L$ to generate an error signal.

(2)

Processing Stage: The error signal is conditioned through a PI controller and amplitude limiter before being fed to the PWM generator.

(3)

Output Stage: The resulting PWM signal modulates the duty cycle of the MOSFET switch in the Boost circuit, thereby regulating the inductor current $I_L$ and stabilizing the output voltage $V_{out}$.

Figure 6 displays the simulated input current and voltage waveforms of the Boost PFC circuit. The upper trace represents the input current waveform, while the lower trace corresponds to the input voltage waveform [32]. By adjusting the input current waveform to approximate a sinusoidal profile, the power factor correction rectifier circuit effectively reduces harmonic distortion. Simultaneously, the input AC current remains phase-synchronized with the input voltage [33].

To quantify the output voltage ripple reduction effect of the Boost PFC circuit, the ripple reduction ratio u is defined as Equation (12), where $U_1$ is the peak-to-peak output voltage ripple of the Diode Rectifier (16.76 V). As shown in Figure 7, the output voltage ripple of this circuit exhibits a peak-to-peak value $U_2$ of 7.99 V.

$$u={\displaystyle \frac{U_1-U_2}{U_1}}$$

(12)

According to Equation (12), this represents a 52.3% ripple reduction relative to the Diode Rectifier.

2.2.3. Comparative Analysis of PF, THD, and FFT Between Boost PFC and Conventional Rectifiers

Quantitative metrics of power factor (PF) and total harmonic distortion (THD) of input current were measured through Simulink simulations. All data were obtained based on the simulation parameters specified in Table 2.

To ensure the reliability and reproducibility of the results, a brief cross-validation of PF and THD was conducted. The PF and THD values were measured using custom-built simulation modules based on the formulas derived in Section 2.2.2 (Equations (7)–(11) for PF; Equation (10) for THD). The steady-state calculation time window was strictly defined as 0.5 s to 1.0 s (excluding the initial transient phase of 0–0.5 s) to eliminate interference from start-up dynamics. Cross-validation was implemented by repeating the simulation Confirmed that no explanation is requiredthree times under identical parameters; the measured PF and THD values exhibited a maximum fluctuation of ±1%, confirming result consistency.

The PF and THD measurement results for the conventional full-bridge rectifier are given in Figure 8, and the corresponding results for the Boost power-factor-correction rectifier are provided in Figure 9.

Based on the above analysis, the Simulink simulation results for the Diode Rectifier and the Boost power factor correction rectifier are summarized in

Table 3. Key Performance Simulation Results for Diode Rectifier and Boost PFC Rectifier.

Parameters	Diode Rectifier	Boost PFC Rectifier
PF	0.40	0.99
Output Voltage Ripple	16.76 V	7.99 V
THD of Input Current	222.80%	14.91%

, respectively.

2.2.4. Input Voltage Fluctuation Test

Analysis of input voltage fluctuations demonstrates that:

(a)

As shown in Figure 10, at 10% above rated voltage, the Boost PFC Circuit rectifier maintains a power factor of 0.98 and total harmonic distortion (THD) of 16.73% with stable output voltage.

(b)

As shown in Figure 11, at 10% below rated voltage, it sustains a power factor of 0.99 and THD of 14.04% while preserving output voltage stability.

Based on comparative simulation analysis, the Boost PFC Circuit implemented in this study demonstrates significant performance improvements over a conventional full-bridge rectifier. Key metrics include an increase in power factor from 0.4 to 0.99, a reduction in output voltage ripple from 16.76 V to 7.99 V (a 52.3% decrease), and a substantial drop in input current total harmonic distortion from 222.80% to 14.91%. These results confirm that the Boost PFC Circuit effectively corrects the power factor, stabilizes the DC output voltage, and drastically suppresses grid harmonic pollution. Consequently, it provides a stable, elevated DC bus voltage (≈380 V) for the subsequent three-level inverter stage, making it the preferred front-end design for this power supply.

2.3. Integrated SPWM Driver-Control Implementation

The AT32F403ARCT7 is adopted as the primary MCU in this design, a high-performance 32-bit ARM Cortex-M4 microcontroller operating at up to 240 MHz. Figure 12 presents the integrated driver-control circuit layout. Consolidating the driver and control boards enables resource sharing, such as a common power supply and microcontroller, which leads to a more compact design, fewer components, and a simplified architecture. This integration enhances operational synergy between driving and control functions, minimizing electromagnetic interference and signal transmission delay while improving response speed. Furthermore, the reduced inter-board connectivity decreases failure risks associated with loose connections or poor contacts, significantly enhancing system reliability.

The integrated layout consolidates control and driver boards on a single PCB. While control circuits require low-voltage, low-noise power supplies, driver circuits demand high-voltage, high-current sources. This integration necessitates strict isolation between power domains to prevent crosstalk. Our system employs isolated power modules to ensure segregation between low-voltage and high-voltage supplies. As shown in Figure 13 and Figure 14, the F2415S-2WR2 isolated buck converter steps down 24 V to 15 V to power four PWM driver modules. Simultaneously, the F2405S-2WR2 module converts 24 V to 5 V for auxiliary power. Crucially, the high-voltage ground (HGND) of driver circuits and low-voltage ground (LGND) of control circuits are physically segregated in the PCB layout as a critical isolation measure.

The integrated design necessitates rigorous thermal management and electromagnetic interference mitigation. Power MOSFETs in driver circuits generate substantial heat, posing risks to temperature-sensitive control components, like microcontrollers and driver ICs. To address thermal challenges, power MOSFETs are mounted on heat sinks for efficient dissipation, while a distributed architecture for isolated power modules reduces energy loss and operating temperatures. Concurrently, high-frequency switching operations induce EMI that may disrupt control circuitry. Critical countermeasures encompass PCB-level shielding, filtering and wiring techniques, notably through physical isolation of high-speed traces from sensitive analog lines to preserve signal integrity and switching accuracy.

Following the integrated driver-control architecture design, the high-frequency transformer—critical for voltage boosting—was optimized for the specific requirements of plasma generation, as detailed in the subsequent section.

2.4. High-Frequency Transformer Design Considerations

A switching frequency of 25 kHz is selected for the plasma power supply, balancing transformer miniaturization against core loss while maintaining stable plasma discharge. This frequency optimally distributes switching, core, and conduction losses. Compared to lower frequencies, it reduces passive component size; relative to higher frequencies, it lowers core loss and electromagnetic interference. Lying within the plasma’s preferred excitation band, 25 kHz promotes discharge stability, extends electrode life, and delivers a cost-effective, high-power-density solution for industrial use.

To achieve the required high-frequency step-up, a UY16 ferrite transformer with a PC40 core is implemented. Its core cross-section of 3.4 cm² is tailored to meet the power and efficiency targets at 25 kHz, enabling efficient conversion from the low-voltage input to the high voltage needed for plasma excitation.

2.4.1. Turns Calculation

The symbol definitions of electrical quantities are listed in

Table 4. Symbol Definitions of Electrical Quantities.

Parameters	Definition
${\mathrm{U}}_{\mathrm{i}\mathrm{n}}$	Primary Winding Input Voltage Peak-to-Peak Value
$\mathrm{U}$	Required Secondary Winding High Voltage (Peak Value)
${\mathrm{U}}_0$	Air Breakdown Field Strength (Peak Value)

.

According to the design requirements specified earlier, the waveform factor $K_f$ is set to 4. The operating frequency $f$ is 25 kHz, and the magnetic flux density $B$ is 0.4 T. With the peak-to-peak primary voltage $U_{in}$ at 380 V, substitution into Equation (13) yields a primary winding turns $N_p$ of 28 [34].

$$N_p={\displaystyle \frac{U_{in}}{K_{f}Bf{A}_c}}$$

(13)

Under standard atmospheric conditions (20 °C, 1 atm, 50% relative humidity), the air breakdown voltage $U_0$ approximates 3 kV/mm. This indicates that an electrode spacing of 1 mm requires approximately 3 kV to initiate breakdown. Given an electrode spacing D of 3.3 mm at 50% humidity and 1 atm pressure, Equation (14) yields a calculated breakdown voltage $U$ of approximately 10 kV.

$$U=U_0\times D$$

(14)

Additionally, accounting for the dead time in the full-bridge inverter circuit, the maximum duty cycle $D_{max}$ is set to 0.47. Substitution into Equation (15) yields a transformer turns ratio K of 28.

$$K={\displaystyle \frac{U}{{2U}_{in}{D}_{max}}}$$

(15)

$$N_S=K\times N_P$$

(16)

In the calculations above, Equations (13)–(15) are uniformly defined according to Table 4. From Equation (13), the primary turns $N_P$ = 28 are derived. Equation (15) yields a turns ratio K = 28, demonstrating internal consistency. These results jointly determine the secondary turns $N_S$ = 784. This design satisfies the requirement for the secondary peak voltage $U$ = 10 kV specified in Equation (14) and is closely aligned with the measured output voltage of approximately 10.79 kV in the prototype test.

2.4.2. Conductor Sizing

With the wire cross-sectional area $A_{wp}$ set to 0.04 ${\mathrm{c}\mathrm{m}}^2$ and the bus current $I_{P-P}$ at 17 A, Equation (17) yields a current density J of 425 ${\mathrm{A}/\mathrm{c}\mathrm{m}}^2$.

$$J={\displaystyle \frac{I_{P-P}}{A_{wp}}}$$

(17)

Given the skin effect inherent in transformer windings, Equation (18) yields a skin depth δ of 0.41 mm.

$$\delta =\sqrt{{\displaystyle \frac{2}{2\pi f\mu {\gamma }_{Cu}}}}$$

(18)

Parameters are defined as follows: operating frequency $f$ = 25 kHz, vacuum permeability $\mu$ = 4π × ${10}^{-7}$ H/m, and copper conductivity ${\gamma }_{Cu}$ = $58\times {10}^6 \mathrm{S}/\mathrm{m}$.

The transformer design implements a stranded parallel winding configuration for the primary coil, utilizing polyamide film insulation rated for 180 °C. Application of Equation (19) yields a strand count N of 8, confirming the implementation of eight parallel conductors.

$$N={\displaystyle \frac{I_{P-P}}{J\pi {\delta }^2}}$$

(19)

2.4.3. Selection of Magnetic Cores and Ferrite Materials

The UY16 core with PC40 ferrite was selected for this design based on a comprehensive evaluation under the operating conditions of 25 kHz and 0.4 T magnetic flux density. According to the Steinmetz equation,

$$P_V=k\times f^{\alpha }\times B^{\beta }$$

(20)

where $P_V$ is the core loss per unit volume; f is the excitation frequency; B is the peak magnetic flux density; k is the proportionality constant; α is the frequency loss exponent; β is the magnetic flux density loss exponent.

PC40 ferrite exhibits high volume resistivity (approximately 1 × 10⁴ Ω·m), which effectively suppresses high-frequency eddy-current losses and yields a core loss of 180 mW/cm³ under the given conditions. In contrast, nanocrystalline alloy FJ50, despite its lower hysteresis loss coefficient, has a resistivity only about 1/125th that of PC40, leading to substantially higher eddy-current losses and a 3–5 times higher cost, which results in an inferior cost-performance ratio.

Magnetically, PC40 provides a sufficient safety margin with a saturation flux density of ~0.5 T and stable permeability, ensuring accurate turns ratio and output voltage. FJ50 requires additional air gaps to stabilize its frequency-dependent permeability, increasing leakage inductance and switching losses. PC40’s inherent insulation also enables compact winding design, whereas metallic FJ50 necessitates larger winding clearances.

Manufacturing-wise, PC40 is a mature, thermally stable material suitable for mass production, while FJ50 is brittle and prone to magnetic degradation at elevated temperatures, demanding extra cooling and adding system complexity.

In summary, PC40 achieves an optimal balance of loss, cost, stability, and manufacturability for this high-frequency, high-voltage application, making it the preferred material paired with the UY16 core for a high-efficiency, reliable transformer.

2.5. Rotating Plasma Spray Gun

The rotating plasma spray gun functions as the core load of the high-frequency, high-voltage plasma power supply and a key terminal device for plasma generation in industrial applications. Its design is fully integrated with the power supply system to ensure stable and efficient operation. The gun comprises an alloy body, a motor drive module, uniformly distributed gas delivery channels, and a central high-voltage electrode assembly. Using PWM signals from the MCU, the drive module provides precise speed control from 500 to 2000 r/min. The central electrode is supplied with 10.79 kV from the secondary side of the high-frequency transformer, and the inter-electrode gap is optimized to 3.3 mm to match the required air-breakdown voltage. In operation, the applied high voltage breaks down the working gas inside the gun to form a plasma. Driven by the rotary motor, the gun rotates uniformly, and the combined action of centrifugal force and gas pressure ejects a stable plasma plume that acts directly on the target.

3. Single-Phase Three-Level SPWM Modulation

3.1. Operational Principles and Advantages

The core principle of three-level SPWM modulation is to generate modulated signals whose pulse width varies with the amplitude of the reference wave by comparing the sinusoidal reference wave with the high-frequency triangular carrier wave. In three-level inverters, neutral-point potential imbalance introduces low-order harmonics, degrades power quality, and accelerates capacitor aging due to uneven voltage stress. Symmetrical SPWM stabilizes the neutral point by ensuring equal conduction times for positive and negative voltage levels in each switching cycle, thereby enhancing system stability.

This three-level approach reduces harmonic content, producing an output that approximates a sinusoidal waveform, lowering grid pollution and electromagnetic interference while improving electromagnetic compatibility and operational efficiency via reduced reactive power losses. Additionally, precise output control is achieved by modulating the signal’s amplitude and frequency, where frequency stability helps maintain consistent plasma discharge properties.

A comparative analysis confirms symmetrical SPWM is suitable: it inherently stabilizes neutral-point potential (vs. Carrier-Based PWM), avoids Space-Vector PWM’s computational complexity, and offers better dynamic response/robustness than Selective Harmonic Elimination PWM under varying loads.

In summary, symmetrical SPWM provides an optimal balance of stability, low loss, and ease of implementation, making it the most suitable modulation method for this high-frequency, high-voltage plasma power supply.

3.2. Simulink Implementation

Figure 15 illustrates the Type-I three-level inverter topology, comprising four MOSFETs, two fast-recovery diodes, two identical DC-link capacitors, and a load resistor. The driving signals are generated by SPWM modulation techniques.

System simulation parameters are detailed in

Table 5. Simulation parameters for Type-I three-level inverter.

Parameters	Specifications
Input signal	DC 380 V
Simulation type	Discrete
Sampling time	1 × 10−7 s
Termination time	1 s

.

System simulation parameters are detailed in Table 5. An 80 Ω resistive simulation load was adopted for Simulink validation, with no plasma torch motor operation and no plasma generation (pure electrical simulation).

The driving signal tmr1(t) is generated using sinusoidal pulse width SPWM modulation [35]. Here, a 25 kHz sinusoidal signal sin1(t) serves as the modulation reference, while a 500 kHz triangular carrier wave up(t) with normalized amplitude [0, 1] constitutes the high-frequency carrier. Comparison of sin1(t) and up(t) via Equation (21) yields the driving signal tmr1(t).

$$tmr1(t)=\{\begin{array}{c}1 if sin1\left(t\right)>up\left(t\right)\\ 0 if sin1\left(t\right)\le up\left(t\right)\end{array}$$

(21)

As specified in Equation (21), a logic high (1) is output when the amplitude of the sinusoidal signal sin1(t) exceeds that of the carrier wave up(t), whereas a logic low (0) is produced when sin1(t) amplitude is less than or equal to up(t). The thus generated driving signaltmr1(t) is depicted in Figure 16.

Analogously, the driving signal tmr8c(t) is generated via sinusoidal pulse width SPWM modulation [36]. Here, a 25 kHz sinusoidal signal sin8(t) functions as the modulation reference, while a 500 kHz negative-polarity triangular carrier wave down(t) with normalized amplitude [0, −1] serves as the high-frequency carrier. Comparison of sin8(t) and down(t) through Equation (22) yields the driving signal tmr8c(t).

$$tmr8c(t)=\{\begin{array}{c}1 if sin8\left(t\right)>down\left(t\right)\\ 0 if sin8\left(t\right)\le down\left(t\right)\end{array}$$

(22)

As governed by Equation (22), a logic high (1) is output when the amplitude of the sinusoidal signal sin8(t) exceeds that of the negative-polarity carrier down(t), while a logic low (0) is produced when sin8(t) amplitude is less than or equal to down(t). The resultant driving signal tmr8c(t) is illustrated in Figure 17.

The signal tmr1(t) undergoes logical inversion via a Logical Operator module, yielding its complementary waveform tmr1c(t). Analogously, tmr8c(t) is similarly inverted to generate its complementary waveform tmr8(t). Simulink simulations (Figure 18) demonstrate two pairs of 25 kHz complementary driving waveforms exhibiting symmetrical pulse widths, with equal positive and negative level conduction durations per cycle.

Under driving signal control, a logic high (1) actuates NMOS transistor turn-on, while a logic low (0) commands turn-off. Voltage levels are defined as P for positive voltage ($+U_{dc}/2$) and N for negative voltage ($-U_{dc}/2$). The output voltage Vout(t) corresponding to the different states of the four driving signals (tmr1(t), tmr8c(t), tmr1c(t), tmr8c(t) is presented in

Table 6. Switching states of Type-I three-level inverter.

Switching States	tmr1	tmr8c	tmr1c	tmr8	Vout
P	1	1	0	0	$+U_{dc}/2$
0	0	1	1	0	0
N	0	0	1	1	$-U_{dc}/2$

.

The simulated output voltage Vout(t) in Figure 19 demonstrates a three-level waveform generated from 380VDC through SPWM modulation. This waveform operates at 25 kHz with matched positive and negative half-cycle amplitudes of 190.3 V, yielding a peak-to-peak voltage of 380.6 V. Symmetrical half-cycle amplitudes confirm successful neutral-point potential balancing [37]. These results validate that the symmetrical SPWM technique achieves balanced positive/negative level conduction durations per switching cycle, ensuring stable neutral-point potential and demonstrating the modulation strategy’s effectiveness.

3.3. FFT Analysis and Harmonic Suppression

The three-level topology, by generating three output voltage levels ($+U_{dc}/2$, 0, $-U_{dc}/2$), produces an output waveform that more closely approximates a sinusoidal wave. This is achieved through the mutual cancellation of low-order harmonics and significant attenuation in the amplitude of high-order harmonics. Furthermore, the harmonic frequencies are shifted farther away from the fundamental frequency, making them easier to suppress further with simple filtering.

As shown in Figure 20 and Figure 21, under an 80 Ω resistive simulation load condition without output filtering (no real plasma load or motor operation). Fast Fourier Transform analyses were performed for both three-level SPWM modulation and conventional two-level inverter modulation. The THD values were measured using the Powergui Block’s FFT Analyzer in Simulink, with the configuration set to start time = 0 s and number of cycles = 2. The results show that the total harmonic distortion of the three-level SPWM output is 67.77%, whereas that of the conventional two-level modulation reaches 109.35%. This demonstrates that the three-level SPWM modulation effectively suppresses harmonic components compared to the two-level topology, even in the unfiltered state.

Notably, the 67.77% THD is an experimental result of the unfiltered inverter output (from Simulink simulations) for the unfiltered inverter output. In practical applications, an output LC filter and the actual load (high-frequency transformer + rotating plasma spray gun) act as low-pass filters to significantly attenuate high-order harmonics, ensuring the plasma-exciting voltage has sufficiently low THD for stable discharge. Specifically, the custom-designed high-frequency transformer (UY16 core with PC40 ferrite) refines the waveform via its leakage inductance and distributed capacitance—these inherently dampen residual high-frequency harmonics from the inverter—while the PC40 ferrite’s high resistivity suppresses eddy-current-induced distortion, resulting in a smoother 10.79 kV voltage waveform for consistent plasma generation.

Compared to the traditional two-level topology, the three-level SPWM modulation not only reduces grid pollution but also decreases the harmonic losses in transformers and filter components. This provides high-quality electrical energy input for the subsequent high-frequency transformer boosting stage and stable plasma discharge. These quantitative results validate the engineering value of the three-level SPWM modulation.

4. System Performance Optimization and Prototype Implementation

4.1. DC Bus Neutral-Point Stability and Capacitor Long-Term Reliability

The long-term reliability of the DC bus capacitor is closely coupled with the stability of its neutral-point potential. Together, they ensure output voltage symmetry, balanced device stress, and system safety under 25 kHz high-frequency operation. The capacitor is subjected to three primary stresses: thermal stress from high ripple current, voltage stress induced by neutral-point potential imbalance, and thermal coupling stress from adjacent power devices.

Symmetrical SPWM modulation fundamentally suppresses neutral-point deviation by enforcing symmetrical conduction times for positive and negative voltage levels within each switching cycle. This maintains the voltages of the two series bus capacitors at half of the DC link voltage (190 V). During startup and shutdown transients—phases prone to imbalance—the modulation logic dynamically adapts to ensure balanced capacitor charging and discharging, thereby directly mitigating voltage stress on the capacitors.

During startup, the simulation shows a maximum ±2.8 V voltage imbalance between the two DC-link capacitors, rapidly suppressed by symmetrical SPWM’s dynamic adaptation. Capacitor voltages revert to the target 190 V (half the DC-link voltage) within 3 switching cycles (120 μs). Such a small voltage deviation ensures that the capacitor voltage stress remains within safe limits during the transient phase.

A multi-dimensional optimization strategy addresses these stresses: low-ESR 450 V polypropylene film capacitors are selected to avoid electrolyte aging; strict series capacitor parameter matching ensures even voltage distribution; the Boost PFC Circuit reduces the voltage ripple to a peak-to-peak value of 7.99 V, lowering thermal stress; and forced air cooling combined with an optimized PCB layout alleviates thermal coupling stress.

In summary, the synergy between the neutral-point stabilization achieved through symmetrical SPWM and the integrated capacitor stress mitigation strategy ensures robust DC bus performance across both steady-state and transient conditions. This approach meets industrial requirements for long-term reliability. Future work may explore aging-adaptive control algorithms and advanced materials, such as solid polymers, to further extend capacitor lifespan.

4.2. Thermal Analysis of Power Devices and Cooling Performance Evaluation

In this design, a thermal analysis was conducted for the GC2M0040120D MOSFETs used in the three-level inverter circuit, including power loss estimation and cooling performance evaluation. The total loss per MOSFET ($P_{total\_FET}$) primarily consists of conduction loss ($P_{cond}$) and switching loss ($P_{SW}$).

The root-mean-square drain-source current per device is calculated as

$$I_{ds\_rms}={\displaystyle \frac{I_{prms}}{\sqrt{2}}}$$

(23)

As shown in

Table 7. Experimental parameters of high-frequency high-voltage plasma power supply.

Parameters	Measured Value
Bus current ${\mathrm{I}}_{\mathrm{P}-\mathrm{P}}$	17.0 A
Bus voltage ${\mathrm{U}}_{\mathrm{P}-\mathrm{P}}$ Primary-Side RMS Current $I_{prms}$	380.8 V 12.0 A
Secondary-Side Peak Voltage $U_{P-S}$	10.79 kV
Secondary-Side Peak Current $I_{P-S}$	0.6 A
Transformer Apparent Power $S_{in}$	2.05 kVA
System Output Power $P_{out}$	1.75 kW
Switching Frequency $f$	25.0 kHz

, the Primary-Side RMS Current $I_{prms}$ is 12.0 A. Substituting the data yields $I_{ds\_rms}\approx 8.5A$.

Under normal conditions, the on-state resistance of the selected MOSFET is Rds(on) = 20 mΩ, the switching frequency is $f_{SW}$ = 25 kHz, and the DC bus voltage is $V_{DC}$ = 380 V. Conduction Loss:

$$P_{cond}=I_{ds\_rms}^2\ast R_{ds\left(on\right)}$$

(24)

Substituting the data yields $P_{cond}\approx 1.45 \mathrm{W}$.

The energy per switching transition, denoted as $E_{SW}$ is approximately 0.4 mJ. This value is estimated from the typical values provided in the datasheet under the given operating conditions. The switching loss is calculated as:

$$P_{SW}=E_{SW}\ast f_{SW}$$

(25)

Substituting the data yields $P_{SW}\approx 10.0 \mathrm{W}$.

Therefore, the total power loss per device is:

$$P_{total\_FET}\approx P_{cond}+P_{SW}$$

(26)

Substituting the data yields $P_{total\_FET}\approx 11.45 W$. Therefore, the total power loss of the four MOSFETs is approximately 45.8 W.

The junction temperature is estimated with

$$T_j=T_a+\left(P_{total\_FET}\ast R_{\theta ja}\right)$$

(27)

Under an ambient temperature $T_a$ = 25 °C and with a total junction-to-ambient thermal resistance $R_{\theta ja}\approx$ 1.5 °C/W, the calculated $T_j$ is approximately 42.2 °C. This remains well below the maximum rated junction temperature $T_{j\_max}$ of 150 °C. Thus, the safety margin at the operating junction temperature is approximately $T_{j\_max}-T_j\approx 107.8 °\mathrm{C}$.

A ±20% sensitivity analysis of total thermal resistance ($R_{\theta ja}$) verifies the robustness of the MOSFET thermal safety margin. When $R_{\theta ja}$ decreases by 20% to 1.2 °C/W, the junction temperature is calculated as $T_j$ (−20%) = 25 + (11.45 × 1.2) = 38.74 °C, with a safety margin of 150–38.74 = 111.26 °C. When $R_{\theta ja}$ increases by 20% to 1.8 °C/W, the junction temperature becomes 45.61 °C, and the safety margin is 104.39 °C. Both scenarios confirm that the junction temperature remains significantly below the maximum rated value (150 °C), and the safety margin maintains a sufficient buffer (exceeding 100 °C) even under ±20% variations of $R_{\theta ja}$, verifying the robustness of the thermal design conclusions.

The effectiveness of forced air cooling is directly reflected in the reduction in convective thermal resistance. Under natural convection conditions, the thermal resistance $R_{\theta ja\_nat}$ $\approx$ 3.0 °C/W. With the implementation of forced air cooling, the thermal resistance $R_{\theta ja\_for}$ $\approx$ 1.5 °C/W. The corresponding junction temperature reduction is quantified as:

$${∆T}_j\approx P_{total\_FET}\ast \left(R_{\theta ja\_nat}-R_{\theta ja\_for}\right)$$

(28)

The calculated temperature reduction of ${∆T}_j\approx 17.2 °\mathrm{C}$ significantly enhances device reliability and enables operation under higher ambient conditions.

Infrared thermal measurements after 30 min at 2.05 kW showed a maximum heat-sink temperature of about 40 °C and a MOSFET case temperature of about 43 °C, aligning with theoretical estimates and confirming the effectiveness of forced-air cooling. An integrated monitoring circuit triggers the fan to full speed if the temperature exceeds 50 °C, providing additional cooling capacity when required.

In summary, the thermal management strategy maintains a substantial safety margin for the MOSFETs, effectively controlling temperature rise under rated conditions and ensuring long-term system reliability and stable performance.

4.3. System Performance Integration and Analysis

4.3.1. Energy Performance Estimation

The energy performance is evaluated based on energy consumption per unit volume of generated plasma. Compared to conventional non-PFC two-level supplies, this design achieves lower specific energy consumption, primarily due to the Boost PFC circuit, low-harmonic three-level SPWM modulation, and integrated driver-control design that reduces transmission losses. These features improve energy conversion efficiency, meet industrial energy-saving demands, and support applications such as material processing and welding.

4.3.2. Electromagnetic Compatibility Optimization

EMC is critical in this high-frequency, high-voltage design due to interference from fast switching and high-power conversion. Key EMI sources include MOSFET switching, transformer radiation, and input/output harmonics. To address these, a systematic strategy is employed: the three-level topology halves dv/dt stress; low-parasitic SiC MOSFETs reduce switching noise; the Boost PFC maintains low-THD input current; and the transformer uses a PC40 core with shielding, sectional windings, and Litz wire to suppress leakage and skin-effect losses. PCB layout separates high- and low-voltage areas with single-point grounding, and EMI filters are installed at both input and output.

4.3.3. Electrical Stability for Plasma Uniformity

The uniformity of the generated plasma is directly governed by the electrical stability of the power supply. The three-level SPWM modulation produces a near-sinusoidal output with very low harmonic content, ensuring a smooth and stable inter-electrode electric field. This prevents arc deflection and promotes stable combustion, as evidenced by the uniform flame morphology observed experimentally. Furthermore, the Boost PFC Circuit limits the DC bus ripple to 7.99 V, while the inverter provides a stable 380.8 V peak-to-peak output. This stable and clean power input ensures consistent gas ionization, resulting in spatially uniform plasma density and electron temperature distribution.

4.4. Plasma Power Supply Prototype Design

Figure 22 illustrates the high-frequency high-voltage plasma power supply system based on three-level sinusoidal pulse width modulation (SPWM) technology, comprising a Boost power factor correction rectifier converter, three-level driver control circuit, high-frequency transformer, and switching power supply. To ensure thermal reliability, an aluminum-fin forced-air cooling system is implemented, incorporating cooling fans, cylindrical fin arrays, and temperature sensors. The rotating plasma torch load is connected to the transformer’s high-voltage secondary output. Precise regulation of torch motor speed via the microcontroller enables uniform plasma gas generation.

5. Results and Analysis

5.1. Characteristics of Three-Level SPWM Gate Signals

Figure 23 shows two pairs of complementary three-level SPWM driving signals with 13 V amplitude and 25 kHz frequency, serving as gate drive signals for the power MOSFETs. The measured drive signal amplitude of 13 V and stable 25.0 kHz switching frequency match the design target in Table 1, providing a reliable foundation for the subsequent inverter and high-voltage stage.

To prevent simultaneous conduction of upper and lower arm power MOSFETs that would cause direct supply short-circuiting and device failure, a dead time of 110 ns is configured as illustrated in Figure 24.

5.2. Output Voltage Analysis of Three-Level Converter

To ensure reliable waveform measurements, all voltage and current signals were synchronized using dedicated, bandwidth-matched instrumentation. The core measurement platform was a Keysight DSOX2024A oscilloscope (KEYSIGHT TECHNOLOGIES, Santa Rosa, CA, USA) with a 200 MHz bandwidth. High-voltage differential signals were acquired using a Siglent DPB5150A probe (SIGLENT Technologies, Shenzhen, China), whose bandwidth was matched to the oscilloscope. Bus currents were measured with a Micsig RCP600XS Rogowski coil (Shenzhen Micsig Technology Co., Ltd., Shenzhen, China), selected for its high-frequency response and low insertion loss. Signal synchronization was achieved via the oscilloscope’s internal edge-trigger function with 5 ns resolution, resulting in a temporal synchronization error below 10 ns between voltage and current channels. All instruments and probes were calibrated against traceable standards prior to testing to guarantee measurement accuracy.

Primary and secondary bus currents were measured peak-to-peak using current probes, while the primary bus voltage was measured with a high-voltage differential probe. Direct measurement of the elevated secondary-side voltage was impractical; therefore, it was derived theoretically using the transformer’s turns ratio and the measured primary-side voltage. Controlled by the four driving signals, the Type-I three-level inverter produced the output waveform shown in Figure 25, operating at 25 kHz with a measured peak-to-peak voltage of 380.8 V. This particular measurement was conducted under an 80 Ω resistive load, consistent with the Simulink simulation setup and without plasma torch operation.

Experimental measurements in Figure 26 and Figure 27 confirm symmetrical half-cycle amplitudes of 190.4 V for both positive and negative phases in the three-level output. These results demonstrate successful neutral-point potential balancing achieved through symmetrical SPWM modulation, establishing agreement with prior simulation findings.

5.3. Performance Assessment of Plasma Power Supply

Building on the validated voltage waveform characteristics, the overall performance of the plasma power supply prototype was systematically evaluated under nominal operating conditions.

The prototype was tested under its intended load—a rotating plasma spray gun. With the torch motor operating at a controlled speed of 1000 r/min and the system delivering the rated 1.75 kW output power, stable plasma generation was achieved, producing a uniform plume.

Figure 28 shows the measured transformer primary bus current, with a peak-to-peak value of 17 A. Given the design turns ratio of K = 28 and a primary-side input SPWM voltage of 380.8 V peak-to-peak, the resulting secondary-side peak voltage reaches 10.79 kV. This voltage is sufficient to break down the working gas within the spray gun’s 3.3 mm electrode gap and form a stable plasma discharge.

For the transformer (turns ratio K = 28), the primary-side SPWM voltage (380.8 V peak-to-peak) has a fundamental RMS value of ≈190.4 V. The theoretical peak output voltage on the secondary side under no-load conditions can be estimated as:

$$U_{p-s}\approx \sqrt{2}\times K\times U_{prms}$$

(29)

Substituting into the formula yields $U_{p-s}\approx 10.79 \mathrm{k}\mathrm{V}$.

The measured peak amplitude of the three-level output voltage is 190.4 V. After being boosted by the custom-designed high-frequency transformer, the peak voltage on the secondary side reaches 10.79 kV, which exceeds the 10 kV target specified in Table 1. This result verifies that the high-voltage boosting capability of the system meets the design requirements for plasma generation.

For output power calculation, the active power input to the transformer ($P_{in}$) is derived from the apparent power ($S_{in}$) multiplied by the power factor (PF), where $S_{in}$ is calculated as the product of the primary-side RMS voltage ($U_{prms}$) and RMS current ($I_{prms}$). The apparent power input to the transformer is:

$$S_{in}\approx U_{prms}\times I_{prms}$$

(30)

As summarized in Table 7, the primary-side RMS current $I_{prms}$ = 12.0 A and primary voltage RMS value $U_{prms}$ = 190.4 V.

The active power input to the transformer is:

$$P_{in}=S_{in}\times PF$$

(31)

Considering the nonlinear characteristics of the high-frequency transformer and the subsequent plasma load, the output power $P_{out}$ is approximately 85% of $P_{in}$. Thus, $P_{out}$ ≈ 1.75 kW.

Experimentally, as shown in Figure 29, the experimentally measured secondary-side transformer current exhibits a peak-to-peak value $I_{P-S}$ of 0.6 A. With the bus current peak−to−peak value $I_{P-P}$ established as 17 A from Figure 28, Equations (32) and (33) yield a secondary−side peak−to−peak voltage $U_{P-S}$ of 10.79 kV.

$$N={\displaystyle \frac{I_{P-P}}{I_{P-S}}}$$

(32)

$${\displaystyle \frac{U_{P-S}}{U_{P-P}}}={\displaystyle \frac{I_{P-P}}{I_{P-S}}}$$

(33)

Experimental measurements indicate that the key parameters of SPWM Based High-Frequency High-Voltage Plasma Power Supply are summarized in Table 7.

The prototype was tested against the key performance targets listed in Table 1. It achieved an output power of 1.75 kW, exceeding the design target of 1.7 kW, a secondary-side peak voltage of 10.79 kV, which satisfies the 10 kV requirement, and a stable switching frequency of 25.0 kHz, matching the design specification. These results verify that all intended performance indicators have been met.

The input stage employs the Boost PFC Circuit previously validated through simulation, where it demonstrated a power factor of 0.99 and an input current THD of 14.91%. The successful experimental attainment of the target performance indicates that the Boost PFC Circuit maintains its effectiveness in harmonic suppression and power-factor correction under actual operating conditions, thereby contributing to the stable and efficient operation of the overall system.

The sampling module acquires system signals for MCU processing, with resultant data displayed via serial communication. Key measurements include an output power of 1.75 kW, switching frequency of 25.0 kHz, and system temperature of 31 °C, collectively confirming nominal operation of the high-frequency high-voltage plasma power supply within optimal parameters.

Figure 30 depicts the rotating plasma torch experiment, demonstrating a uniform and stable plasma plume morphology. These results confirm consistent spatial uniformity of plasma density and temperature throughout the generated plume.

While the prototype demonstrates stable plasma generation and meets core performance targets under nominal conditions, it has three key limitations. First, direct global efficiency measurements (encompassing PFC, inverter, transformer, and load stages) are not provided, with efficiency inferred indirectly from component-level loss analysis. Second, dynamic tests under abrupt plasma load variations (e.g., sudden changes in gas pressure or electrode gap) are absent, leaving the transient response capability unvalidated. Third, no dedicated output filter is integrated, relying instead on the inherent filtering effects of the transformer and plasma load. These limitations restrict the conclusions to steady-state operations with nominal parameters (3.3 mm electrode gap, 500–2000 r/min motor speed, 1.75 kW rated power), excluding dynamic loads, precise global efficiency quantification, and applications requiring ultra-low harmonic distortion beyond the load’s inherent filtering.

6. Conclusions

This study presents a high-frequency high-voltage plasma power supply design based on three-level sinusoidal pulse width modulation technology, targeting key limitations of conventional plasma power supplies such as high harmonic distortion, neutral-point potential imbalance, and structural complexity. The design integrates three core technical solutions: a Boost PFC Circuit at the input stage, symmetric three-level SPWM modulation, and an integrated driver-control architecture combined with an optimized high-frequency transformer.

Experimental results validate the design: the prototype achieves stable plasma discharge at 10.79 kV peak voltage and 1.75 kW output power, with uniform plasma and good conversion performance. It fully meets all core design targets specified in Table 1 while suppressing current harmonics to reduce grid pollution, mitigating neutral-point potential drift to enhance power device safety and output voltage stability, and simplifying manufacturing through the integrated driver-control architecture.

A key strength of the proposed design lies in its inherent extensibility for demanding scenarios. To scale toward higher power and voltage, the neutral-point-clamped three-level topology will be upgraded to an active neutral-point-clamped (ANPC) configuration by replacing passive clamping diodes with additional MOSFETs, ensuring uniform device stress and introducing structural redundancy for fault tolerance. Redundant MOSFETs enable the system to reconfigure and maintain operation if a single device fails, critical for mission-critical industrial applications. Control performance will be enhanced with advanced algorithms including Model Predictive Control, Sliding Mode Control for improved robustness against disturbances, and Adaptive Backstepping Control for dynamic parameter adjustment. Foundational scalability modifications include upgrading to high-current MOSFETs or parallel configurations, adopting larger PFC inductors, low-ESR film capacitors and multi-core parallel transformers, and fine-tuning key parameters to adapt to diverse operating conditions.

Future research will optimize these scalable modifications, enhance system robustness through aging-adaptive strategies for key components, and investigate dynamic load response to improve anti-interference. As three-level SPWM drive-control technology matures, the efficient, stable and reliable plasma power supply proposed herein is expected to play an increasingly prominent role in industrial material processing, high-efficiency energy conversion, biomedical applications and other fields, ultimately promoting the engineering application and industrial scaling of plasma technology.