Distributed Quantum-Assisted Multi-SAPF Architecture Based on Deterministic Current Control and Asynchronous QUBO–QAOA–VQE Supervisory Optimization

Abstract

The increasing penetration of nonlinear industrial loads, distributed renewable generation, and intelligent electrical infrastructures requires active power filters capable of simultaneously providing high-performance harmonic mitigation, reactive power compensation, coordinated operation of multiple converters, and deterministic real-time implementation. Conventional centralized shunt active power filters (SAPFs) exhibit limited scalability, while optimization-based approaches often compromise deterministic execution because of their computational complexity. To address these challenges, this paper proposes a Distributed Quantum Multi-Shunt Active Power Filter (Quantum Multi-SAPF) that combines deterministic-based local current control with asynchronous quantum-assisted supervisory optimization. The proposed architecture employs four distributed SAPF units operating under a hierarchical cyber–physical framework. The lower control layer, implemented on a MATLAB R2026a, includes all fast electrical functions—signal acquisition, SOGI-based synchronization, Clarke transformation, instantaneous $p$–$q$ current reference generation, current regulation, interleaved PWM modulation, and protection—which are executed deterministically at a switching frequency of 15 kHz. The upper supervisory layer operates asynchronously at 20 Hz and formulates converter coordination as a quadratic unconstrained binary optimization (QUBO) problem solved using Quantum Approximate Optimization Algorithm (QAOA) allocation together with Variational Quantum Eigensolver (VQE) predictive correction. This multi-rate architecture separates fast electrical dynamics from slow supervisory optimization, ensuring that uncertain optimization latency does not affect converter stability. The proposed controller is validated through comprehensive switching-level simulations on the MATLAB R2026a platform. Numerical results demonstrate a reduction in source current total harmonic distortion from 24.615% to 0.142%, corresponding to a 99.423% harmonic reduction, while improving the source power factor to 0.99999 and achieving 99.999% reactive power compensation. The distributed four-SAPF synchronization network maintains coherent phase alignment among all converter units throughout the simulation, thereby supporting coordinated compensation and balanced current sharing. This synchronized operation contributes to highly accurate compensation current tracking, with an RMS tracking error of only 0.026 A, while limiting the source current unbalance to 0.026%. These results confirm the effectiveness of the distributed synchronization and local control architecture in maintaining coordinated and balanced operation of the four parallel SAPFs. The proposed interleaved modulation strategy, combined with optimized current sharing, maintains balanced converter utilization while suppressing circulating currents without requiring a dedicated circulating current controller. The proposed Distributed Quantum Multi-SAPF establishes a scalable framework that combines deterministic industrial control with quantum-assisted supervisory optimization. The architecture provides high harmonic compensation capability, near-unity power factor, balanced converter utilization, comprehensive Safe Operating Area supervision, and practical industrial feasibility, making it a promising solution for future smart grids, renewable energy integration, electric vehicle charging infrastructures, and intelligent power quality conditioning systems.

1. Introduction

1.1. Background and Motivation

The rapid electrification of modern society, together with the widespread deployment of renewable energy systems, electric vehicle charging stations, variable-speed motor drives, industrial automation, and power electronic converters, has fundamentally transformed the operating conditions of electrical distribution networks. Although these technologies significantly improve energy efficiency and system flexibility, they also introduce considerable harmonic current distortion, reactive power demand, voltage fluctuations, current imbalance, and electromagnetic interference, leading to increased power losses, accelerated equipment aging, reduced system reliability, and deterioration of power quality. Consequently, maintaining compliance with international harmonic standards has become an increasingly important requirement for both utilities and industrial consumers [1,2,3]. International standards provide complementary requirements and assessment procedures for power quality at the point of common coupling (PCC). IEEE Std 519-2022 specifies harmonic-control recommendations and distortion limits [1], whereas IEEE Std 1547-2018 establishes interconnection and interoperability requirements for distributed energy resources, including power-quality provisions [2]. IEC TR 61000-3-6 provides guidance for assessing harmonic emission limits in medium-, high-, and extra-high-voltage systems [3], while IEC 61000-4-7 specifies instrumentation and measurement methods for harmonics and interharmonics [4].

Meeting these requirements has stimulated extensive research on active compensation techniques capable of mitigating harmonic currents while simultaneously improving power factor and reducing reactive power demand.

Among the available compensation technologies, Shunt Active Power Filters (SAPFs) have become the preferred solution because they simultaneously suppress harmonic currents, compensate reactive power, balance three-phase currents, and improve the source power factor without introducing the resonance problems typically associated with passive filters. Since the pioneering work of Akagi and co-workers on the instantaneous reactive power theory [5], active filtering has evolved into one of the principal technologies for industrial power quality improvement.

1.2. Evolution of Active Power Filtering

The first generation of SAPFs was primarily based on the instantaneous active–reactive power ($p$-$q$) theory proposed by Akagi et al. [5]. Subsequent research established active filters as an important technology for power conditioning, with Akagi identifying emerging converter configurations, control strategies, and application trends [5,6]. The theoretical foundations and practical applications of instantaneous power theory were subsequently consolidated and extended in the comprehensive treatment by Akagi, Watanabe, and Aredes [6].

The original instantaneous reactive-power compensation principle was established in the seminal work of Akagi, Kanazawa, and Nabae [7]. Its mathematical framework was further developed for three-phase four-wire systems by Akagi, Ogasawara, and Kim [8]. In parallel, Peng and Lai proposed a generalized instantaneous reactive-power theory for three-phase power systems [9], extending the theoretical basis for power-component identification and compensation-reference generation.

Together, these contributions established the theoretical foundations for modern SAPF control, particularly instantaneous power calculation, harmonic-current identification, reactive-power compensation, and reference-current generation.

In [10] the generalized formulations for three-phase four-wire systems can be found These contributions established the mathematical foundation for reference current generation and harmonic compensation, enabling active filters to replace bulky passive harmonic filters in many industrial applications.

Subsequent research expanded the concept toward hybrid active filters [5], distributed compensation strategies [6], damping of harmonic propagation [9], and practical implementation issues [10]. Comprehensive reviews published by Singh et al. [11], Akagi [12], Miret et al. [13], and El-Habrouk et al. [14] demonstrated that active filters offer significant advantages over passive solutions, including adaptive harmonic compensation, improved dynamic response, and simultaneous reactive power correction.

Despite these advances, early SAPFs were mainly implemented as single high-power converters, making scalability, thermal management, maintenance, and redundancy increasingly challenging as industrial power ratings continued to increase. Modern industrial installations, therefore, require distributed compensation architectures capable of sharing the filtering effort among multiple converters while preserving overall system stability and harmonic mitigation performance.

1.3. Advances in SAPF Control Strategies

Control strategies have evolved considerably during the last two decades. Conventional synchronous reference frame proportional–integral (PI) controllers remain attractive because of their deterministic implementation and relatively low computational burden. However, their performance deteriorates under distorted supply voltages, frequency deviations, and parameter uncertainties, requiring accurate tuning and decoupling compensation [15,16].

Alternative controllers, including proportional–resonant (PR), hysteresis, repetitive, sliding mode, adaptive, and predictive controllers, have significantly improved transient response and harmonic rejection [17,18,19,20,21]. Recent predictive control techniques, particularly model predictive control (MPC), directly determine optimal switching actions while considering converter constraints, achieving superior dynamic performance compared with classical controllers [17,18,19]. Nevertheless, predictive methods exhibit rapidly increasing computational complexity as the number of switching states, prediction horizon, and parallel converters increases.

The development of active power filtering has been accompanied by advances in hierarchical control, coordinated converter operation, and grid synchronization. Hierarchical control strategies for AC and DC microgrids provide a framework for coordinating local and supervisory control functions [20]. Virtual-impedance methods and robust droop control have been investigated to improve the operation and proportional load sharing of parallel converters [21,22]. In addition, harmonic compensation using distributed-generation interfacing inverters has been reviewed as an approach to improving power quality in distribution systems [23].

Accurate synchronization is essential for grid-connected converter control. Research has addressed the stability of grid converters employing phase-locked loops (PLLs) [24], the decoupled double synchronous reference frame PLL for operation under unbalanced grid conditions [25], and synchronization structures based on second-order generalized integrators (SOGIs) [26]. Further developments in SOGI-PLL-based grid synchronization [27] and synchronization techniques for distributed-generation systems [28] provide additional foundations for coordinated converter operation.

These developments are relevant to SAPF architectures because compensation performance depends not only on reference-current generation but also on synchronization accuracy, current-control dynamics, and interactions among grid-connected converters. A broader treatment of power-quality enhancement using custom power devices is provided by Ghosh and Ledwich [29].

1.4. Distributed Converter Architectures

To address the limitations of a single high-power SAPF, distributed converter architectures employ multiple lower-power converters operating cooperatively at the point of common coupling (PCC). Such architectures can provide modularity, scalability, and redundancy, although their practical performance depends on appropriate coordination, current sharing, synchronization, and stability management. Centralized current- and power-control schemes for parallel inverters and AC microgrids have been comprehensively reviewed by Elnady et al. [30], while Guo and Chen examined control strategies for multiple power inverters in power-electronics-based systems [31]. These studies provide a foundation for investigating coordinated multi-SAPF architectures [30,31].

However, distributed operation introduces several additional control challenges that are largely absent in single-converter systems. These include coordinated current sharing, suppression of circulating currents, synchronization among local controllers, DC-link voltage balancing, communication latency, and optimal allocation of the overall compensation effort [32,33,34,35,36].

Recent studies on parallel voltage source converters have demonstrated that improper synchronization or unequal current sharing may produce significant internal circulating currents, increased converter losses, and degraded harmonic compensation [32,33,34,35]. Consequently, distributed control cannot be achieved simply by duplicating independent SAPF controllers; instead, coordinated supervisory control becomes essential.

Another important aspect concerns synchronization. Reviews of converter synchronization and phase-locked loop (PLL) stability indicate that converter-dominated systems require accurate phase tracking and coherent synchronization to ensure stable operation under both normal and disturbed grid conditions [37,38]. These observations strongly motivate the development of distributed synchronization mechanisms for large SAPF arrays.

1.5. Emerging Role of Quantum Optimization

In parallel with developments in power electronics, quantum computing has emerged as a promising computational paradigm for solving large-scale optimization problems. Among the available quantum algorithms, the Variational Quantum Eigensolver (VQE) [39] and the Quantum Approximate Optimization Algorithm (QAOA) [40] have attracted particular interest because they are specifically designed for noisy intermediate-scale quantum (NISQ) hardware.

Recent reviews identify QAOA as a prominent variational approach for combinatorial problems that admit QUBO/Ising representations, while VQE and related variational quantum algorithms provide hybrid expectation value minimization mechanisms whose practical usefulness depends strongly on encoding, ansatz design, noise, measurement cost, and classical optimization [41,42,43,44,45,46,47]. Power system applications remain predominantly simulation or proof-of-concept studies, and a practical quantum computational advantage has not yet been established. Ref. [48] illustrates a complementary quantum-enhanced direction: a robust short-term voltage stability assessment using a quantum-enhanced Transformer. That learning/assessment problem is fundamentally different from the present constrained supervisory optimization problem. Together, the two directions illustrate possible quantum-enhanced roles at different layers of future intelligent power systems without implying that the present SAPF study establishes quantum computational superiority.

Nevertheless, most reported applications remain focused on high-level power system optimization. Real-time supervisory control of power electronic converters, especially distributed SAPFs operating under realistic switching conditions, has received very limited attention. Existing studies rarely consider converter dynamics, PWM switching, semiconductor non-idealities, synchronization constraints, or industrial control architectures.

1.6. Research Gap

The above literature review reveals that substantial progress has been achieved independently in four major research directions:

• Advanced SAPF current controllers [15,16,17,18,19,20,21];
• Artificial intelligence for converter control [20,21,22,23,24,25,26];
• Distributed converter architectures and synchronization [30,31,32,33,34,35,36,37,38,49];
• Quantum optimization algorithms [39,40,41,42,43,44,45,46,47,50].

However, these developments have largely evolved independently.

Current SAPF research predominantly addresses either local current regulation, predictive control, intelligent optimization, distributed converters, or quantum computing, while very few studies combine these technologies within a unified industrial framework. In particular, no reported work simultaneously integrates:

• Distributed multi-SAPF architectures;
• Hierarchical supervisory control;
• QAOA-based converter participation optimization;
• VQE-assisted predictive reference generation;
• Realistic switching-level converter models, including semiconductor non-idealities;
• Deterministic local current control;
• Distributed PLL synchronization;
• Finite state operational management;
• Comprehensive harmonic, thermal, and safe operating area validation.

This scientific gap forms the principal motivation for the present research.

1.7. Originality of the Proposed Work

To address the above limitations, this paper proposes a Quantum Multi-SAPF Hybrid-Switching architecture for coordinated harmonic compensation in industrial distribution systems. Unlike previously reported SAPFs, the proposed system combines four distributed shunt active power filters connected at a common PCC through dedicated coupling inductors and coordinated by a hierarchical supervisory framework.

The supervisory layer uses an ideal state vector QAOA formulation for discrete profile/configuration selection and a VQE-assisted finite dimensional variational formulation for bounded continuous predictive refinement. The resulting candidates are subjected to deterministic feasibility filtering before reference packets are issued. Fast deterministic local controllers operate at 15 kHz, whereas the supervisor is updated at 20 Hz. The present work demonstrates this hybrid architecture numerically; it does not claim execution on physical quantum hardware, NISQ deadline compliance, or quantum computational speed advantage.

Furthermore, the proposed model incorporates a realistic switching-level representation including semiconductor conduction losses, dead time, PWM modulation, ADC quantization, sensor noise, deterministic parameter tolerances, distributed SOGI-PLL synchronization, finite state startup management, and coherent FFT-based harmonic evaluation. The introduction of four distributed shunt active power filters (SAPFs) is justified by the need to combine high power quality performance with modularity, current sharing, thermal management, switching ripple reduction, redundancy, and safe converter operation. A single sufficiently rated SAPF could theoretically generate the required compensating current; therefore, the scientific justification for four units is not mathematical necessity, but the additional physical and supervisory degrees of freedom created by a distributed architecture.

Therefore, the originality of this work lies not merely in applying quantum algorithms to active power filtering, but in developing a complete distributed cyber–physical architecture that integrates realistic converter modeling, hierarchical deterministic control, quantum-assisted supervisory optimization, synchronized multi-converter operation, and comprehensive industrial-oriented numerical validation within a unified framework suitable for next-generation intelligent power quality conditioning.

1.8. Critical Analysis of Existing Control Strategies

The literature reviewed in the previous sections demonstrates that the development of shunt active power filters has evolved from classical harmonic compensation toward intelligent and distributed power-conditioning systems. Nevertheless, despite more than four decades of research following the introduction of the instantaneous reactive power theory [4], several scientific and technological challenges remain unresolved.

The earliest SAPF controllers were based on synchronous reference frame PI regulators and the instantaneous active–reactive power theory, providing reliable compensation under balanced operating conditions [4,10,12]. These methods remain attractive because of their simple implementation and deterministic computational requirements. However, their compensation accuracy deteriorates under distorted supply voltages, frequency deviations, parameter uncertainties, and rapidly varying nonlinear loads. Furthermore, PI-based controllers require careful gain tuning and accurate decoupling networks, limiting their adaptability to practical industrial environments [15,16].

Proportional–resonant (PR), repetitive, hysteresis, and sliding mode controllers have subsequently been proposed to improve harmonic rejection and transient response [17,18,19,20,21]. Although these methods outperform conventional PI regulators in several operating scenarios, they also introduce new limitations. PR controllers require multiple resonant branches to compensate higher-order harmonics, increasing computational complexity and reducing numerical robustness. Hysteresis controllers achieve excellent dynamic response but operate with variable switching frequency, making electromagnetic compatibility and filter design more difficult. Consequently, none of these approaches simultaneously satisfy the requirements of low computational burden, fixed switching frequency, high harmonic attenuation, and robust industrial implementation.

Model Predictive Control (MPC) represents one of the most significant advances in converter control because switching decisions are obtained through online optimization rather than cascaded linear regulators [17,18,19]. Predictive methods naturally incorporate converter constraints, improve transient response, and reduce steady-state tracking errors. Nevertheless, the computational complexity of MPC grows exponentially with prediction horizon and converter number. This limitation becomes particularly important in distributed active filtering systems, where several converters must be coordinated simultaneously within the sampling interval.

Artificial intelligence has emerged as an alternative approach for improving controller adaptability and robustness. Neural networks, reinforcement learning, fuzzy logic, evolutionary optimization, and adaptive machine learning techniques have demonstrated promising results in harmonic estimation, controller tuning, disturbance rejection, and parameter identification [20,21,22,23,24,25,26]. However, these techniques generally require extensive offline training, representative datasets, and hyperparameter optimization. Their deterministic execution, explainability, and certification for industrial converter control remain active research topics.

1.9. Distributed Active Power Filtering

Recent industrial trends indicate a gradual transition from single high-power active filters toward distributed converter architectures. Instead of concentrating the entire compensation capability within one converter, multiple lower-power SAPFs connected in parallel at the PCC improve scalability, redundancy, reliability, thermal distribution, and maintenance flexibility [30,31].

Despite these advantages, distributed SAPFs introduce additional coordination problems that are considerably more complex than those encountered in conventional single-converter systems. In particular, compensation currents must be shared among several converters while simultaneously avoiding circulating currents, maintaining balanced DC-link voltages, limiting converter temperatures, respecting semiconductor operating limits, and preserving global harmonic compensation performance.

Existing distributed control strategies generally employ equal current sharing, master–slave coordination, droop control, or centralized supervisory algorithms [30,31]. Although these approaches successfully distribute the total load among several converters, they rarely formulate current sharing as a multi-objective optimization problem considering harmonic distortion, converter utilization, thermal loading, DC-link balancing, and safe operating area constraints simultaneously.

Another important issue concerns circulating currents. Parallel voltage source converters connected to a common PCC may exchange undesirable internal currents caused by parameter mismatches, modulation differences, common mode voltages, or synchronization errors. Numerous studies have, therefore, investigated dedicated circulating current suppression techniques based on coordinated modulation, common mode voltage control, and optimized PWM strategies [32,33,34,35,36]. These investigations demonstrate that simply connecting converters in parallel does not guarantee stable cooperative operation.

The proposed architecture addresses these issues through dedicated three-phase coupling inductors, deterministic current controllers, interleaved PWM carriers, distributed synchronization, and a supervisory optimization layer that explicitly determines the participation factor of each converter. Consequently, current sharing is optimized rather than imposed a priori, allowing unequal but physically optimal converter loading under varying operating conditions.

1.10. Distributed Synchronization.Background and Existing Approaches

Reliable synchronization is fundamental for distributed converter systems because harmonic compensation accuracy depends directly on the phase coherence of all injected currents. Independent PLLs operating without coordination may accumulate small phase and frequency errors that generate circulating currents, increase converter stress, and reduce compensation performance.

Recent investigations of converter synchronization have emphasized that PLL dynamics significantly influence the stability of converter-dominated electrical systems, particularly under weak-grid conditions and large disturbances [37,38]. These studies recommend coordinated synchronization mechanisms capable of maintaining phase coherence among multiple converters rather than treating each converter as an isolated unit.

The proposed architecture adopts a distributed SOGI-PLL synchronization network in which each SAPF estimates the grid phase independently while continuously exchanging synchronization information with the supervisory layer.

1.11. Hierarchical Control Architectures

Modern distributed power electronic systems increasingly employ hierarchical control structures in which different control objectives are executed at different time scales. Fast inner loops regulate converter currents and voltages, whereas slower supervisory layers coordinate power sharing, synchronization, optimization, and energy management [49].

This hierarchical organization significantly reduces computational burden because global optimization is performed only at relatively slow update rates, while high-bandwidth current regulation remains deterministic and independent. Such architectures have become common in distributed microgrids and parallel inverter systems but have only rarely been applied to active power filters.

The proposed Quantum Multi-SAPF architecture follows this principle by separating deterministic local control from quantum-assisted supervisory optimization. Local current controllers execute every 66 μs (15 kHz), while the supervisory optimization layer updates converter participation factors every 50 ms (20 Hz). This separation preserves real-time current regulation while allowing computationally intensive optimization to be performed without compromising switching-frequency requirements.

1.12. Quantum Optimization for Converter Coordination

Recent progress in quantum computing has introduced variational quantum algorithms as powerful tools for solving complex optimization problems. Among these algorithms, the Variational Quantum Eigensolver (VQE) [39] and the Quantum Approximate Optimization Algorithm (QAOA) [40] have emerged as the two principal hybrid quantum–classical optimization techniques for noisy intermediate-scale quantum processors.

Comprehensive reviews have demonstrated that QAOA is particularly effective for combinatorial optimization problems formulated as quadratic unconstrained binary optimization (QUBO), whereas VQE provides efficient solutions for continuous nonlinear optimization under multiple constraints [41,42,43,44]. These algorithms have already been investigated for optimal power flow, scheduling, resource allocation, and energy management problems [45,46,47,50].

Despite these advances, virtually all reported applications remain focused on high-level optimization of electrical power systems. Very limited research has addressed real-time supervisory coordination of multiple power electronic converters, and existing studies generally neglect switching dynamics, semiconductor non-idealities, synchronization constraints, and deterministic industrial control requirements.

The proposed work extends the application of variational quantum algorithms from power system optimization to distributed active filtering. Specifically, QAOA determines the optimal converter participation factors through a QUBO formulation, while VQE computes predictive current reference corrections satisfying harmonic, thermal, electrical, and DC-link energy constraints.

Focused Analytical Synthesis of Literature

Shunt active power filters remain an established solution for compensating harmonic and reactive currents generated by nonlinear loads. Instantaneous p–q reference generation [4,10] offers a physically transparent real-time framework, while deterministic PI-based current regulation [12,51] remains attractive for industrial implementation. However, increasingly demanding operating conditions have motivated predictive and intelligent controllers [15,16,17,18,19,20,21,22,23,24,25,26], particularly when constraints, nonlinearities, and parameter variation must be considered. These methods improve local converter performance, but computational burden, tuning dependence, training requirements, and interpretability become increasingly important when several converters must be coordinated simultaneously.

Parallel and distributed converter research [30,31,32,33,34,35,36,37,38,49] addresses complementary problems including current sharing, circulating current suppression, interleaved modulation, PLL synchronization, and hierarchical coordination. These results establish the technical basis for multi-converter operation, but the literature reviewed in the manuscript does not provide a unified four-SAPF framework that simultaneously coordinates harmonic compensation, independent DC-link energy, non-equal participation, thermal/SOA constraints, synchronization, and realistic switching-level non-idealities. The relevant gap is, therefore, not the parallel connection of converters itself but the coordinated supervisory allocation of a common compensation task under heterogeneous physical constraints.

Hybrid quantum–classical optimization provides a possible supervisory mechanism for this coordination problem. QAOA is naturally associated with discrete QUBO-type decisions, whereas VQE and related variational formulations provide a framework for finite dimensional optimization [39,40,41,42,43,44,45,46,47,50]. Existing power system applications are concentrated mainly on planning, scheduling, optimal power flow, and energy/resource allocation; converter-level applications under realistic switching constraints remain limited. This motivates the present multi-rate architecture, in which QAOA addresses discrete participation/profile decisions and a VQE-assisted branch refines continuous predictive references at 20 Hz, while all time-critical synchronization, current regulation, PWM generation, and protection functions remain deterministic at 15 kHz.

This focused narrative leads directly to the research gap: the cited literature provides strong individual solutions for SAPF control, constrained optimization, distributed converter coordination, and quantum optimization, but these research directions are largely separated. The proposed contribution is their integration within a physically constrained four-SAPF supervisory architecture, evaluated through deterministic switching-level simulation. The contribution is, therefore, architectural and methodological; the present study does not claim physical quantum hardware validation or quantum computational advantage.

The revised Introduction should end with testable objectives rather than additional literature. In the reported benchmark, the load-side current THD is 24.615%, and the compensated source current THD is 0.142%. The harmonic reduction is, therefore,

$${\eta }_{THD}={\displaystyle \frac{24.615-0.142}{24.615}}\times 100=99.423\%$$

(1)

The source power factor is 0.99999, residual source reactive power is 0.31 var, the current tracking RMS error is 0.026 A, the maximum modulation index is 0.763 pu, and the reported electrical SOA status is PASS. These values should not be used as literature-review claims; they are included at the end of the Introduction only as a concise statement of the validation objectives subsequently demonstrated in the Results section.

$$u_{I,pk}={\displaystyle \frac{7.664 \mathrm{A}}{44 \mathrm{A}}}\times 100=17.42\%$$

(2)

$$h_m=(1-0.763)\times 100=23.7\%$$

(3)

1.13. Scientific Gap and Motivation

The critical analysis presented above demonstrates that significant advances have been achieved independently in active filtering, predictive control, artificial intelligence, distributed converters, synchronization, and quantum optimization. However, the literature also reveals that these research directions have largely evolved separately.

Current SAPF research predominantly focuses on improving local current controllers, whereas distributed converter studies mainly address power sharing and synchronization. Quantum-computing research, in turn, concentrates primarily on high-level optimization problems rather than converter-level supervisory control. Consequently, no comprehensive framework currently combines distributed SAPFs, realistic switching-level models, hierarchical deterministic control, QAOA-based current allocation, VQE-assisted predictive optimization, distributed PLL synchronization, finite state industrial operation, and complete power quality validation within a unified cyber–physical architecture.

This identified gap directly motivates the proposed Quantum Multi-SAPF Hybrid-Switching system. By integrating deterministic local current regulation with quantum-assisted supervisory optimization, realistic converter modeling, distributed synchronization, and industrial-oriented numerical validation, the proposed architecture extends the state of the art beyond isolated controller improvements toward a fully coordinated intelligent power quality conditioning platform suitable for future smart industrial distribution systems. In

Table 1. Critical comparison of existing SAPF control strategies.

Method	Main Advantages	Main Limitations	Gap Addressed by Proposed Work
Instantaneous p–q Theory [4,10]	Simple reference generation; real-time implementation	Sensitive to voltage distortion and synchronization errors	Distributed synchronization and adaptive supervisory optimization
Classical PI Current Control [12,51]	Mature industrial implementation; deterministic execution	Limited harmonic rejection; parameter-dependent tuning	Predictive optimization and quantum-assisted allocation
Model Predictive Control [17,18,19]	Fast dynamics; explicit constraint handling	Computational complexity increases rapidly with converter number	QAOA–VQE supervisory optimization with deterministic local control
AI-based Controllers [20,21,22,23,24,25,26]	Adaptive and robust to nonlinear operating conditions	Offline training; computational burden; limited interpretability	Hybrid deterministic–quantum architecture without AI training dependence
Hierarchical Quantum Multi-SAPF (This Work)	Distributed optimization, deterministic implementation, industrial scalability	—	Integrates predictive control, quantum optimization, synchronization, realistic switching model, and distributed compensation

, a critical comparison with representative recent literature is depicted.

• Research Objectives

The primary objective of this research is to develop and validate a Distributed Quantum Multi-Shunt Active Power Filter (Quantum Multi-SAPF) capable of simultaneously achieving high-performance harmonic mitigation, near-unity power factor, adaptive converter coordination, and deterministic real-time implementation for modern industrial power systems. Unlike conventional centralized active power filters, the proposed architecture aims to combine distributed power electronic compensation with quantum-assisted supervisory optimization while preserving the deterministic behavior required for industrial-based control platforms.

A second objective is to establish a hierarchical multi-rate control architecture that separates fast electrical dynamics from slow supervisory optimization. The deterministic lower layer is responsible for signal acquisition, grid synchronization, current reference generation, current regulation, PWM modulation, and converter protection, whereas the upper supervisory layer optimizes converter participation factors, DC-link energy balancing, thermal loading, and Safe Operating Area utilization using QUBO, QAOA, and VQE algorithms. This separation ensures that computational latency associated with optimization does not interfere with the stability of the electrical control loops.

Another important objective is to demonstrate the feasibility of distributed coordinated operation of multiple SAPF units connected in parallel. This requires maintaining precise synchronization among the converters, balanced current sharing, stable DC-link voltages, and suppression of circulating currents without introducing additional differential current control loops. Furthermore, the architecture seeks to improve converter utilization through adaptive allocation of the compensation effort according to the instantaneous electrical, thermal, and operational conditions of each converter.

The research also aims to validate the proposed architecture through both switching-level numerical simulations and experimental implementation. Numerical validation is intended to demonstrate the intrinsic capability of the proposed control strategy under detailed switching conditions. Together, these complementary validation stages provide a comprehensive assessment of the proposed Distributed Quantum Multi-SAPF under both idealized and practical operating conditions.

• Main Scientific Contributions

The principal scientific contribution of this work is the development of a novel Distributed Quantum Multi-SAPF architecture that integrates deterministic-based current control with asynchronous quantum-assisted supervisory optimization into a unified cyber–physical framework. The proposed architecture extends the conventional concept of shunt active power filtering by introducing coordinated distributed compensation, allowing multiple converters to operate cooperatively while maintaining deterministic real-time performance and industrial implementation feasibility.

A second major contribution is the introduction of a hierarchical asynchronous control strategy in which fast electrical control and slow optimization are completely decoupled. The deterministic layer continuously executes all high-bandwidth electrical functions at the converter switching frequency, whereas the supervisory layer periodically performs multi-objective optimization using the QUBO, QAOA, and VQE algorithms. This architecture demonstrates that quantum-assisted optimization can be successfully integrated into industrial power electronic systems without compromising deterministic converter operation or introducing instability associated with uncertain computational latency.

The proposed work further contributes a distributed resource allocation methodology based on quantum-inspired optimization. Instead of enforcing equal current sharing among the parallel converters, the supervisory controller dynamically allocates the compensation effort according to converter loading, DC-link energy, synchronization quality, thermal conditions, and Safe Operating Area margins. This adaptive coordination improves converter utilization while maintaining balanced operation and avoiding unnecessary overload of individual units.

Another significant contribution is the development of an integrated circulating current suppression strategy that combines electrical topology, distributed synchronization, deterministic timing, interleaved PWM modulation, balanced DC-link regulation, and optimized current allocation. Unlike conventional parallel inverter systems, the proposed architecture suppresses circulating currents without requiring a dedicated differential current controller, thereby reducing implementation complexity while preserving stable parallel operation.

• Critical Positioning of the Proposed Work

References [30,31] establish that parallel converter systems require explicit coordination of current and power sharing. However, the reviewed architectures are generally developed for microgrid inverters or generic converter arrays and do not solve the combined harmonic allocation, reactive compensation, DC-link balancing, and thermal utilization problem formulated in the proposed Multi-SAPF.

References [32,33,34,35,36] show that circulating currents depend on topology, modulation, parameter differences, common mode voltage, and coordination quality. The proposed architecture addresses these factors through separate three-phase coupling inductors, deterministic tolerance-aware plant modeling, interleaved carriers, local high-speed current regulation, and supervisory participation factors.

References [37,38] demonstrate that synchronization quality is a stability requirement for converter-dominated systems.

Reference [49] supports hierarchical time scale separation, but its focus is microgrid secondary control. The proposed method applies the hierarchical principle specifically to active power filtering: deterministic local current controllers execute at $15 \mathrm{k}\mathrm{H}\mathrm{z}$, while a quantum-assisted supervisory layer updates allocation, energy balancing, and operating constraints at $20 \mathrm{H}\mathrm{z}$.

The distinctive contribution is, therefore, not parallel connection alone. It is the integration of distributed harmonic compensation, optimized non-equal current sharing, coherent PLL synchronization, interleaved switching, independent DC-link regulation, realistic converter non-idealities, SOA supervision, and quantum-assisted allocation within one validated four-node SAPF platform. In

Table 2. Thematic classification.

References	Main Topic	Relevance to the Proposed Multi-SAPF
[30,31]	Parallel converter control reviews	Centralized, decentralized, and coordinated current/power sharing
[32,33,34,35,36]	Current sharing and circulating current suppression	Converter decoupling, interleaving, modulation coordination, internal current limitation
[37,38]	Grid synchronization and PLL stability	Phase coherence, frequency spread, disturbance stability
[49]	Distributed hierarchical control	Separation of local high-bandwidth control from slower global coordination

, the thematic classification of the references [30,31,32,33,34,35,36,37,38,49] is centralized.

The literature represented by references [39,40,41,42,43,44,45,46,47,50] shows that variational quantum algorithms have progressed from theoretical formulations toward hybrid proof-of-concept optimization. QAOA is naturally suited to discrete combinatorial problems that admit QUBO/Ising representations, whereas a VQE/VQA treatment of bounded continuous supervisory variables requires an explicit finite resolution encoding, a finite dimensional Hermitian cost operator, deterministic measurement decoding, and physical feasibility projection. Accordingly, the present work does not treat VQE as a direct unrestricted continuous optimizer and does not claim practical quantum advantage.

Recent reviews indicate that quantum optimization is increasingly investigated for power system planning, scheduling, optimal power flow, resource allocation, and energy management, but applications to real-time power electronics control remain very limited.

The proposed Quantum Multi-SAPF Hybrid-Switching architecture differs from the current literature in three principal aspects:

• QAOA is employed for online converter participation and compensation current allocation, rather than for offline planning or scheduling.
• VQE is integrated into a predictive supervisory controller to optimize compensation references while simultaneously considering harmonic distortion, DC-link balancing, thermal loading, reactive power, and safe operating area constraints.
• The quantum optimization layer is embedded within a realistic distributed switching-level SAPF platform, including deterministic local current control, distributed PLL synchronization, semiconductor non-idealities, PWM dynamics, measurement uncertainty, and finite state operational management, thereby extending variational quantum optimization beyond high-level power system optimization into coordinated multi-converter control.

All time-critical functions, including synchronization, Clarke transformation, instantaneous power computation, current regulation, PWM generation, protection, and finite state machine management, are executed deterministically, supporting the architectural suitability for subsequent real-time and experimental assessment.

Finally, the paper provides a comprehensive validation framework for assessing the proposed QAOA-supervised multi-agent SAPF architecture under realistic operating conditions. The validated numerical results demonstrate a reduction in source current THD from 24.615% to 0.142%, corresponding to a 99.423% reduction in harmonic distortion. Simultaneously, the proposed control strategy achieves a source power factor of 0.99999 and limits the residual source reactive power to only 0.31 var. The compensation current tracking RMS error is restricted to 0.026 A, while the source current unbalance remains as low as 0.026%. Furthermore, the DC-link voltage is tightly regulated around its 750 V reference. The maximum modulation index remains limited to 0.763 pu, while the filter current RMS and peak values are 3.497 A and 7.664 A, respectively, ensuring substantial operating margins and full compliance with the specified safe operating area constraints. These results confirm the effectiveness of the proposed hierarchical control architecture in simultaneously achieving harmonic suppression, near-unity power factor, reactive power compensation, accurate current tracking, DC-link energy regulation, and balanced three-phase operation.

The close agreement between the mathematical formulation and numerical simulations confirms the robustness, scalability, and practical applicability of the proposed Distributed Quantum Multi-SAPF architecture for next-generation intelligent power quality conditioning systems.

2. Materials and Methods

2.1. Research Methodology

The proposed Quantum Multi-SAPF platform was developed using a hierarchical model-based methodology that combines physical power system modelling, switching-level converter simulation, distributed synchronization, deterministic local control, and quantum-assisted supervisory optimization. The complete workflow comprises system definition; derivation of the grid, load, coupling filter, converter, and DC-link models; generation of the aggregate compensation current reference; QAOA-based discrete resource allocation; VQE-assisted predictive optimization; synchronized local current regulation; finite state operational management; and quantitative validation using time-aligned measurements and coherent FFT analysis.

The physical compensation principle follows Kirchhoff’s current law at the Point of Common Coupling:

$${\mathbf{i}}_s(t)={\mathbf{i}}_L(t)-{\displaystyle \sum _{k=1}^4}{\mathbf{i}}_{f,k}(t),$$

(4)

where ${\mathbf{i}}_s$, ${\mathbf{i}}_L$, and ${\mathbf{i}}_{f,k}$ denote the source current, total load current, and compensation current injected by SAPF $k$, respectively. The control objective is to make ${\mathbf{i}}_s$ balanced, sinusoidal, and aligned with the positive-sequence PCC voltage.

The architecture operates at two distinct time scales. The four local converter controllers execute deterministic current regulation and PWM generation at $15 \mathrm{k}\mathrm{H}\mathrm{z}$, while the quantum supervisory optimizer updates resource allocation, DC-link balancing, and operating constraints at $20 \mathrm{H}\mathrm{z}$.

2.2. System Configuration

The investigated system consists of a balanced three-phase $400 \mathrm{V}$, $50 \mathrm{H}\mathrm{z}$ utility grid, a nonlinear six-pulse diode bridge RL load, and four parallel two-level SAPFs connected at the PCC. Each SAPF has an independent $750 \mathrm{V}$ DC link and is interfaced with the PCC through three dedicated coupling inductors.

Electrical port clarification: $R_L = 14 \mathsf{\Omega }$ and $L_L = 35 \mathrm{m}\mathrm{H}$ are physical parameters of the rectifier-fed load branch. At $V_{LL} = 400 \mathrm{V}$, the ideal average six-pulse rectified voltage is approximately $V_{d,avg} \approx 540 \mathrm{V}$. In contrast, $V_{dc,k} =750 \mathrm{V}$ is the independent DC-link reference of SAPF $k$. These voltages belong to different electrical ports and must not be combined when identifying the physical load resistance.

The grid and equivalent feeder dynamics are represented by

$${\mathbf{v}}_g(t)={\mathbf{v}}_{\mathrm{P}\mathrm{C}\mathrm{C}}(t)+R_g{\mathbf{i}}_s(t)+L_g{\displaystyle \frac{d{\mathbf{i}}_s(t)}{dt}},$$

(5)

where $R_g$ and $L_g$ denote the equivalent grid-side resistance and inductance.

The nonlinear load current is decomposed into fundamental positive-, negative-, and zero-sequence components and harmonic components:

$${\mathbf{i}}_L={\mathbf{i}}_1^{+}+{\mathbf{i}}_1^{-}+{\mathbf{i}}_1^0+{\displaystyle \sum _{h=2}^H}{\mathbf{i}}_h.$$

(6)

For the six-pulse rectifier, the dominant characteristic harmonics are of orders $6m\pm 1$, particularly the 5th, 7th, 11th, and 13th harmonics.

The desired source current and total compensation current references are generated as

$${\mathbf{i}}_s^{*}={\displaystyle \frac{P_s^{*}}{{\parallel {\mathbf{v}}_1^{+}\parallel }^2}}{\mathbf{v}}_1^{+},{\mathbf{i}}_f^{*}={\mathbf{i}}_L-{\mathbf{i}}_s^{*},$$

(7)

where $P_s^{*}$ includes the active load power and the small active-power demand required to cover converter losses and regulate the DC-links.

2.3. Mathematical Model of the Distributed SAPF

The aggregate compensation current is obtained by summing the currents injected by the four SAPFs:

$${\mathbf{i}}_f(t)={\displaystyle \sum _{k=1}^4}{\mathbf{i}}_{f,k}(t).$$

(8)

For SAPF $k$ and phase $p\in \{a,b,c\}$, the continuous-time coupling filter dynamics are

$$L_{f,kp}{\displaystyle \frac{d{i}_{f,kp}}{dt}}=v_{\mathrm{i}\mathrm{n}\mathrm{v},kp}-v_{\mathrm{P}\mathrm{C}\mathrm{C},p}-R_{f,kp}{i}_{f,kp}.$$

(9)

The discrete-time predictive model used by the digital controller is obtained through forward-Euler discretization:

$$i_{f,kp}[n+1]=\left(1−{\displaystyle \frac{R_{f,kp}{T}_s}{L_{f,kp}}}\right)i_{f,kp}[n]+{\displaystyle \frac{T_s}{L_{f,kp}}}\left[v_{\mathrm{i}\mathrm{n}\mathrm{v},kp}[n-d]-v_{\mathrm{P}\mathrm{C}\mathrm{C},p}[n]\right],$$

(10)

where $T_s=50 \mathsf{\mu }\mathrm{s}$ and $d=2$ samples represent one computation cycle delay plus one ADC pipeline delay.

The controller uses nominal coupling filter parameters, whereas the simulated physical plants use tolerance-shifted values. This deliberate mismatch evaluates robustness against realistic component dispersion.

2.4. Coupling Inductor Model

The nominal coupling filter parameters are

$$L_{f,\mathrm{n}\mathrm{o}\mathrm{m}}=3.00 \mathrm{m}\mathrm{H}/\mathrm{p}\mathrm{h}\mathrm{a}\mathrm{s}\mathrm{e},R_{f,\mathrm{n}\mathrm{o}\mathrm{m}}=0.030 \mathsf{\Omega }/\mathrm{p}\mathrm{h}\mathrm{a}\mathrm{s}\mathrm{e}.$$

The actual values assigned to SAPF $k$ are

$$\begin{array}{cccc}& L_{f,k}=L_{f,\mathrm{n}\mathrm{o}\mathrm{m}}\left(1+{\delta }_{L,k}\right),R_{f,k}=R_{f,\mathrm{n}\mathrm{o}\mathrm{m}}\left(1+{\delta }_{R,k}\right),& & \end{array}$$

(11)

with deterministic tolerances

$${\mathit{\delta }}_L=[0.035, -0.028, 0.047, -0.041],{\mathit{\delta }}_R=[0.060, -0.045, 0.035, -0.055].$$

The resulting inductances are

$$\begin{array}{cc}{L}_{f1a}=L_{f1b}=L_{f1c}& =3.105 \mathrm{m}\mathrm{H},\\ L_{f2a}=L_{f2b}=L_{f2c}& =2.916 \mathrm{m}\mathrm{H},\\ L_{f3a}=L_{f3b}=L_{f3c}& =3.141 \mathrm{m}\mathrm{H},\\ L_{f4a}=L_{f4b}=L_{f4c}& =2.877 \mathrm{m}\mathrm{H}.\end{array}$$

(12)

The corresponding winding resistances are $0.03180$, $0.02865$, $0.03105$, and $0.02835 \mathsf{\Omega }/\mathrm{p}\mathrm{h}\mathrm{a}\mathrm{s}\mathrm{e}$ for SAPFs 1–4, respectively.

The total magnetic energy stored in the three coupling inductors of SAPF $k$is

$$E_{L,k}={\displaystyle \frac{1}{2}}\sum _{p\in \{a,b,c\}}{L}_{f,kp}{i}_{f,kp}^2.$$

(13)

These inductors regulate injected-current dynamics, attenuate switching ripple, limit $di/dt$, suppress circulating currents, and electrically decouple the four parallel converters.

2.5. DC-Link Energy Model

Each SAPF contains an independent DC-link capacitor whose stored energy is

$$E_{dc,k}={\displaystyle \frac{1}{2}}{C}_{dc,k}{V}_{dc,k}^2.$$

(14)

The DC-link energy balance is expressed as

$$C_{dc,k}{V}_{dc,k}{\displaystyle \frac{d{V}_{dc,k}}{dt}}=P_{\mathrm{a}\mathrm{c},k}-P_{\mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s},k}-P_{\mathrm{a}\mathrm{u}\mathrm{x},k},$$

(15)

where $P_{\mathrm{a}\mathrm{c},k}$ is the active power exchanged with the AC side, $P_{\mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s},k}$ includes semiconductor and filter losses, and $P_{\mathrm{a}\mathrm{u}\mathrm{x},k}$ denotes auxiliary consumption.

The d-axis reference of SAPF $k$ includes both global participation and local DC-link regulation:

$$i_{d,k}^{*}={\lambda }_k{i}_{d,\mathsf{\Sigma }}^{*}+K_{pv}\left(V_{dc}^{*}−V_{dc,k}\right)+K_{iv}\int \left(V_{dc}^{*}−V_{dc,k}\right)dt.$$

(16)

This formulation maintains all four DC-link voltages close to the common reference while preserving the aggregate compensation objective.

2.6. Converter Model

Each SAPF is implemented as a three-phase, two-level IGBT voltage source inverter. For switching state $s_{kp}\in \left\{\mathrm{0,1}\right\}$, the ideal phase-to-midpoint voltage is

$$v_{\mathrm{i}\mathrm{n}\mathrm{v},kp}^{\mathrm{i}\mathrm{d}}=\left(s_{kp}−{\displaystyle \frac{1}{2}}\right)V_{dc,k}.$$

(17)

The IGBT and antiparallel diode conduction models are

$$v_{\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}=V_{\mathrm{C}\mathrm{E}0}+r_{\mathrm{C}\mathrm{E},\mathrm{o}\mathrm{n}}\mid i\mid ,v_D=V_{\mathrm{D}0}+r_{\mathrm{D},\mathrm{o}\mathrm{n}}\mid i\mid ,$$

(18)

with $V_{\mathrm{C}\mathrm{E}0}=1.65 \mathrm{V}$, $r_{\mathrm{C}\mathrm{E},\mathrm{o}\mathrm{n}}=0.012 \mathsf{\Omega }$, $V_{\mathrm{D}0}=1.25 \mathrm{V}$, and $r_{\mathrm{D},\mathrm{o}\mathrm{n}}=0.010 \mathsf{\Omega }$.

The actual converter phase voltage is, therefore,

$$v_{\mathrm{i}\mathrm{n}\mathrm{v},kp}=v_{\mathrm{i}\mathrm{n}\mathrm{v},kp}^{\mathrm{i}\mathrm{d}}-\Delta v_{\mathrm{c}\mathrm{o}\mathrm{n}\mathrm{d},kp}-\Delta v_{\mathrm{d}\mathrm{t},kp},$$

(19)

where $\Delta v_{\mathrm{c}\mathrm{o}\mathrm{n}\mathrm{d},kp}$ represents semiconductor conduction drops and $\Delta v_{\mathrm{d}\mathrm{t},kp }$ is the voltage error introduced by the $2.0 \mathsf{\mu }\mathrm{s}$ dead time.

2.7. PWM Modulation

The normalized modulation command and duty ratio are

$$m_{kp}^{*}={\displaystyle \frac{2v_{\mathrm{i}\mathrm{n}\mathrm{v},kp}^{*}}{V_{dc,k}}},d_{kp}={\displaystyle \frac{1+m_{kp}^{*}}{2}}.$$

(20)

The modulation command and voltage reference rate are constrained by

$$\mid m_{kp}^{*}\mid \le 0.995, \mid {\displaystyle \frac{\Delta v_{\mathrm{i}\mathrm{n}\mathrm{v},kp}^{*}}{T_s}}\mid \le 0.85{\displaystyle \frac{V_{dc}^{*}}{T_s}}.$$

(21)

The four PWM carriers are shifted by $0^{\circ }$, ${90}^{\circ }$, ${180}^{\circ }$, and ${270}^{\circ }$. Interleaving distributes switching transitions over one carrier period and reduces aggregate ripple at the PCC without increasing the switching frequency of any individual converter.

2.8. Proposed Distributed Synchronization and PLL Coordination Method

Each SAPF employs a SOGI-PLL to estimate the positive-sequence PCC angle and frequency. The local PLL equations are

$$e_{\mathrm{P}\mathrm{L}\mathrm{L},k}=v_{q,k}^{+}, {\widehat{\omega }}_k={\omega }_0+K_{p,\mathrm{P}\mathrm{L}\mathrm{L}}{e}_{\mathrm{P}\mathrm{L}\mathrm{L},k}+K_{i,\mathrm{P}\mathrm{L}\mathrm{L}}\int e_{\mathrm{P}\mathrm{L}\mathrm{L},k}dt, {\dot{\widehat{\theta }}}_k={\widehat{\omega }}_k.$$

(22)

Distributed phase agreement is reinforced through a consensus correction:

$${\dot{\widehat{\theta }}}_k={\widehat{\omega }}_k-k_{\theta }\sum _{j\in {\mathcal{N}}_k}{a}_{kj}\left({\widehat{\theta }}_k−{\widehat{\theta }}_j\right),$$

(23)

where ${\mathcal{N}}_k$ denotes the communication neighborhood of SAPF $k$, and $a_{kj}$ is the corresponding adjacency coefficient. The synchronization criteria are based on PLL frequency spread, detector residual, and maximum inter-node phase mismatch.

2.9. Hierarchical Control Strategy

The aggregate compensation reference is allocated among the four SAPFs according to

$$i_{f,k}^{*}={\lambda }_k i^{*}+\Delta i_{dc,k}^{*}+\Delta i_{bal,k}^{*}$$

(24)

where ${\lambda }_k$ is the supervisory participation factor, $V_{dc,k}$ regulates local DC-link energy, and $i_{bal,k,ref}$ corrects unequal electrical or thermal loading.

The allocation must satisfy

$${\displaystyle {\sum }_{k=1}^4}{\lambda }_k=1, 0 \le {\lambda }_k \le {\lambda }_{k,max}, I_{f,k} \le I_{k,max}, T_{j,k} \le T_{j,max}$$

(25)

The supervisory objective function is

$$J=w_{THD}{J}_{THD}+w_Q{J}_Q+w_I{J}_I+w_{Vdc}{J}_{Vdc}+w_T{J}_T+w_{sw}{J}_{sw}+w_{\Delta \lambda }{J}_{\Delta \lambda }$$

(26)

where the individual terms penalize source current distortion, residual reactive power, unequal converter loading, DC-link imbalance, thermal stress, switching effort, and abrupt allocation changes. Here, J_{TH D} measures normalized source-current harmonic distortion, J_Q penalizes residual source reactive power, J_I represents unequal or excessive converter-current loading, J_Vdc penalizes deviations among the individual DC-link voltages, J_T represents thermal stress, J_sw accounts for switching/modulation effort, and $J_{\Delta \lambda }$ penalizes abrupt changes in the participation vector. The positive weights define the relative supervisory priorities after normalization. Consequently, (26) is a slow multi-objective coordination criterion; it does not replace the 15 kHz deterministic current controller and does not directly generate PWM states.

The binary allocation problem is formulated as a quadratic unconstrained binary optimization (QUBO) problem, mapped to an equivalent Ising Hamiltonian, and addressed through variational optimization, as summarized in Equation (27).

$$\begin{array}{c}{x}^{*}=arg min x^{\mathrm{T}}Qx, x \in {\left\{\mathrm{0,1}\right\}}^{\mathrm{n}}\\ H_Q=c_{0}I+{\sum }_{\mathrm{i}}{h}_{\mathrm{i}}{Z}_{\mathrm{i}}+{\sum }_{\mathrm{i(j)}}{J}_{\mathrm{ij}}{Z}_{\mathrm{i}}{Z}_{\mathrm{j}}\\ {\vartheta }^{*}=arg min E_Q (\vartheta ), E_Q (\vartheta )=⟨\psi (\vartheta )\left|H_Q\right|\psi (\vartheta )⟩\end{array}$$

(27)

Here, x is the binary decision vector, Q is the QUBO coefficient matrix, Z_i is the Pauli-Z operator on qubit i, and h_i and J_ij are the Ising coefficients. The constant c₀I preserves the exact energy mapping but does not change the minimizing configuration. The variational parameters ϑ define the state |ψ(ϑ)⟩, and E_Q(ϑ) is the expected Hamiltonian energy.

Equation (27) defines the optimization problems; a finite-sample variational algorithm does not guarantee identification of the global QUBO optimum. The selected sampled binary candidate must therefore be decoded and checked against hard feasibility constraints before application.

The decoded solution supplies the optimal participation factors, activation states, current limits, DC-link priorities, and converter operating modes. The validated mean participation allocation was

$$\mathit{\lambda }=[0.2561, 0.2561, 0.2317, 0.2561].$$

(28)

Unlike conventional centralized active filters, the proposed Distributed Quantum Multi-Shunt Active Power Filter (Quantum Multi-SAPF) adopts a hierarchical cyber–physical architecture that separates deterministic converter control from computationally intensive supervisory optimization. The architecture is organized into nine functional layers, each operating at its own execution rate while exchanging only the information required for optimal operation.

2.9.1. Online Parameter Estimation for the SAPF Coupling Branch and Supply Frequency

To reduce sensitivity to component tolerances and slow parameter drift, the revised control description includes an online estimation layer. The coupling resistance and inductance of each SAPF are estimated from the measured PCC voltage, converter voltage, and filter current using recursive least squares (RLS). The estimated quantities are supervisory/model parameters; the fast current loop remains deterministic at 15 kHz.

$$y_k[n]=v_{PCC}[n]-v_{VSI,k}[n]=R_{f,k} i_{f,k}[n]+L_{f,k} {\displaystyle \frac{i_{f,k}[n]-i_{f,k}[n-1]}{T_s}}$$

(29)

$${\phi }_k[n]=\left[i_{f,k}[n] {\displaystyle \frac{i_{f,k}[n]-i_{f,k}[n-1]}{T_s}}\right], {\theta }_k^{est}[n]=\left[R_{f,k}^{est}[n] L_{f,k}^{est}[n]\right]$$

(30)

With forgetting factor λ_RLS, the RLS gain, innovation, parameter update, and covariance update are

$$K_k[n]={\displaystyle \frac{P_k[n-1] {\phi }_k[n]}{{\lambda }_{RLS}+{{\phi }_k}^T[n] P_k[n-1] {\phi }_k[n]}}$$

(31)

$${\epsilon }_k[n]=y_k[n]-{{\phi }_k}^T[n] {\theta }_k^{est}[n-1]$$

(32)

$${\theta }_k^{est}[n]={\theta }_k^{est}[n-1]+K_k[n] {\epsilon }_k[n]$$

(33)

$$P_k[n]={\displaystyle \frac{1}{{\lambda }_{RLS}}}\{P_k[n-1]-K_k[n] {{\phi }_k}^T[n] P_k[n-1]\}$$

(34)

For example, if $R_{f,k}^{est} = 0.031 \mathsf{\Omega }$, $L_{f,k}^{est} = 2.95 \mathrm{m}\mathrm{H}$, $i_{f,k} = 5.00 \mathrm{A}$, and ${\displaystyle \frac{d{i}_{f,k}}{dt}} \approx 1500 \mathrm{A}/\mathrm{s}$, the predicted coupling branch voltage is 0.031 × 5 + 0.00295 × 1500 ≈ 4.58 V. For a measured branch voltage of 4.60 V, the RLS innovation is approximately 0.02 V; the covariance matrix and regressor excitation determine how this residual updates resistance and inductance.

The equivalent DC-load resistance can be estimated from low-pass-filtered DC voltage and current (or power) quantities. A numerically robust power-based estimate is

$$v_d(t)=R_L i_d(t)+L_L {\displaystyle \frac{d{i}_d}{dt}}$$

(35)

For the physical nonlinear load, $R_L = 14 \mathsf{\Omega }$ is the dissipative resistance and $L_L = 35 \mathrm{m}\mathrm{H}$ is the series smoothing inductance. The inductive term stores and releases magnetic energy and shapes the rectified current ripple and diode conduction intervals; it does not represent an additional DC resistance. Thus, $R_L$ is a physical component value, whereas a resistance inferred from a voltage–power ratio would only be an operating-point equivalent and need not have the same numerical value.

The supply frequency is obtained from the SOGI-PLL estimated phase. In discrete form,

$$f_g^{est}[n]={\displaystyle \frac{{\theta }_g^{est}[n]-{\theta }_g^{est}[n-1]}{2\pi T_s}}$$

(36)

The raw derivative is low-pass filtered before supervisory use. Near the nominal operation, the estimator converges around the 50 Hz grid frequency, and the same estimated angle/frequency pair is used for synchronous transformations and coherent harmonic evaluation.

2.9.2. Core Supervisory Equations and Interface to Deterministic Local Control

To improve continuity between the main text and Appendix A, the equations required to understand the physical role of the supervisor are retained here, whereas derivations, extended notation, and implementation details remain in the Appendix. The PCC current balance is

$$i_{s,abc}=i_{L,abc}-{\displaystyle {\sum }_{k=1}^4}{i}_{F,k,abc}$$

(37)

The aggregate compensation demand is distributed by non-negative participation factors that sum to unity:

$$i_{F,k,ref} = {\lambda }_k i_{F,\Sigma ,ref}, {\lambda }_k \ge 0, {\displaystyle {\sum }_{k=1}^4}{\lambda }_k = 1$$

(38)

The supervisory layer updates every 50 ms, while the local controllers execute every 66.67 μs:

$$T_S = {\displaystyle \frac{1}{f_S}} = {\displaystyle \frac{1}{20}} = 50 \mathrm{m}\mathrm{s}, T_L = {\displaystyle \frac{1}{f_L}} = {\displaystyle \frac{1}{15000}} \approx 66.67 \mathsf{\mu }\mathrm{s}$$

(39)

$$N_{LS}={\displaystyle \frac{f_L}{f_S}}={\displaystyle \frac{15000}{20}}=750$$

(40)

Consequently, each accepted supervisory packet is held or rate-limited across approximately 750 deterministic local iterations. QAOA and the VQE-assisted branch modify only slow coordination variables; SOGI-PLL synchronization, compensation current generation, DC-link regulation, current tracking, modulation, and protection remain local deterministic functions.

$$r_{cmd}(k)={\Pi }_C\{F[z_{QAOA}(k), v_{VQE}(k), x_{sup}(k)]\}$$

(41)

Here, ${\Pi }_C$ denotes deterministic projection onto the instantaneous feasible set defined by current, DC-link, modulation, thermal, slew rate, availability, and FSM constraints. This equation is the explicit bridge between Section 2.9 and Section 2.10: the optimizer proposes, the feasibility layer validates, and the local controllers execute.

2.10. Finite State Machine

Safe commissioning and coordinated operation are implemented through the states OFF, PRECHARGE, GRID QUALIFY, PLL ACQUIRE, ARRAY SYNC, READY, SOFT START, RUN, DERATED, and FAULT. The transition logic is represented by

$$\mathcal{S}[n+1]=\left\{\begin{array}{cc}\mathrm{P}\mathrm{R}\mathrm{E}\mathrm{C}\mathrm{H}\mathrm{A}\mathrm{R}\mathrm{G}\mathrm{E},& \mathcal{S}=\mathrm{O}\mathrm{F}\mathrm{F}\wedge C_{\mathrm{e}\mathrm{n}\mathrm{a}\mathrm{b}\mathrm{l}\mathrm{e}},\\ \mathrm{G}\mathrm{R}\mathrm{I}\mathrm{D}\mathrm{Q}\mathrm{U}\mathrm{A}\mathrm{L}\mathrm{I}\mathrm{F}\mathrm{Y},& V_{dc,\mathrm{m}\mathrm{i}\mathrm{n}}\ge V_{\mathrm{p}\mathrm{r}\mathrm{e}},\\ \mathrm{P}\mathrm{L}\mathrm{L}\mathrm{A}\mathrm{C}\mathrm{Q}\mathrm{U}\mathrm{I}\mathrm{R}\mathrm{E},& C_{\mathrm{g}\mathrm{r}\mathrm{i}\mathrm{d}}=1,\\ \mathrm{A}\mathrm{R}\mathrm{R}\mathrm{A}\mathrm{Y}\mathrm{S}\mathrm{Y}\mathrm{N}\mathrm{C},& \mid \Delta \theta \mid \le {\theta }_{\mathrm{m}\mathrm{a}\mathrm{x}},\\ \mathrm{R}\mathrm{E}\mathrm{A}\mathrm{D}\mathrm{Y},& C_{\mathrm{s}\mathrm{y}\mathrm{n}\mathrm{c}}=1,\\ \mathrm{S}\mathrm{O}\mathrm{F}\mathrm{T}\mathrm{S}\mathrm{T}\mathrm{A}\mathrm{R}\mathrm{T},& C_{\mathrm{r}\mathrm{e}\mathrm{a}\mathrm{d}\mathrm{y}}=1,\\ \mathrm{R}\mathrm{U}\mathrm{N},& C_{\mathrm{t}\mathrm{r}\mathrm{a}\mathrm{c}\mathrm{k}}=1,\\ \mathrm{D}\mathrm{E}\mathrm{R}\mathrm{A}\mathrm{T}\mathrm{E}\mathrm{D},& T_j\ge T_{\mathrm{d}\mathrm{e}\mathrm{r}},\\ \mathrm{F}\mathrm{A}\mathrm{U}\mathrm{L}\mathrm{T},& C_{\mathrm{f}\mathrm{a}\mathrm{u}\mathrm{l}\mathrm{t}}=1,\\ \mathcal{S}[n],& \mathrm{otherwise}.\end{array}\right.$$

(42)

PWM is disabled during OFF and PRECHARGE and is progressively enabled during SOFT START. Transitions depend on grid qualification, minimum DC-link voltage, PLL convergence, array synchronization, reference tracking, current limits, temperature, and communication health.

2.11. Simulation Conditions

The complete platform was implemented in MATLAB R2026a and evaluated using a deterministic numerical model of power converters and control system that incorporates the non-idealities described below (

Table 3. Main simulation parameters.

Parameter	Value
Grid voltage	$400 \mathrm{V}$ line-to-line RMS
Nominal grid frequency	$50 \mathrm{H}\mathrm{z}$
Number of SAPFs	4
Converter topology	Two-level IGBT VSI
DC-link reference	$750 \mathrm{V}$
Local control/PWM frequency	$15 \mathrm{k}\mathrm{H}\mathrm{z}$
Supervisory frequency	$20 \mathrm{H}\mathrm{z}$
Nominal coupling inductance	$3.00 \mathrm{m}\mathrm{H}/\mathrm{p}\mathrm{h}\mathrm{a}\mathrm{s}\mathrm{e}$
Nominal coupling resistance	$0.030 \mathsf{\Omega }/\mathrm{p}\mathrm{h}\mathrm{a}\mathrm{s}\mathrm{e}$
Dead time	$2.0 \mathsf{\mu }\mathrm{s}$
Total digital delay	$100 \mathsf{\mu }\mathrm{s}$
Modulation limit/reached	0.90/0.763 p.u.
Carrier phase shifts	$0^{\circ },{90}^{\circ },{180}^{\circ },{270}^{\circ }$
Nominal active load power	≈9.80 kW

). The utility grid had a rated line-to-line voltage of 400 V and a nominal frequency of 50 Hz. The final measured frequency was approximately 50.2 Hz.

The nonlinear load consisted of a three-phase six-pulse diode bridge feeding an RL branch with $R_L=14 \mathsf{\Omega }$ and $L_L=35 \mathrm{m}\mathrm{H}$.

The nonlinear load consisted of a three-phase six-pulse diode bridge feeding a physical series $R_L-L_L$ branch with $R_L = 14 \mathsf{\Omega }$ and $L_L = 35 \mathrm{m}\mathrm{H}$. For an ideal six-pulse bridge supplied from $V_{LL} = 400 \mathrm{V}$, the average rectified voltage applied to the complete RL branch under continuous conduction is $V_{d,avg} = {\displaystyle \frac{3\surd 2}{\pi }}{V}_{LL} \approx 1.35 V_{LL} \approx 540 \mathrm{V}$. This load-side voltage is distinct from the 750 V DC-link reference of each SAPF.

Each SAPF used an independent $V_{dc,k} = 750 \mathrm{V}$ DC-link reference, 15 kHz PWM/local control frequency, and 20 Hz supervisory update rate. The $V_{dc,k}$ variable belongs to the SAPF energy storage subsystem and is not the rectified load voltage $V_d$. The controllers used nominal coupling filter values, while the physical model employed the tolerance-shifted values given in (9).

Current and voltage measurements were represented by 16-bit ADCs with ranges of $\pm 44 \mathrm{A}$ and $0$–$1000 \mathrm{V}$, respectively. The current quantization step was approximately $1.221 \mathrm{m}\mathrm{A}$, and the voltage step was approximately $15.259 \mathrm{m}\mathrm{V}$. Sensor noise levels were $5 \mathrm{m}\mathrm{A}\mathrm{R}\mathrm{M}\mathrm{S}$ for current and $20 \mathrm{m}\mathrm{V}\mathrm{R}\mathrm{M}\mathrm{S}$ for voltage measurement. Fixed current sensor offsets of +8 mA, −6 mA, +5 mA, and −7 mA were assigned to SAPFs 1–4, respectively.

2.12. Performance Evaluation

Performance evaluation was performed using synchronized current measurements satisfying the physical PCC balance in (1). Load, filter, and source current signals were temporally aligned before calculating current errors and harmonic indices.

THD was evaluated using a coherent FFT window containing an integer number of cycles at the PLL-estimated grid frequency. Ten cycles were used before compensation, and twenty cycles were used after the system reached the RUN state. The final acceptance criteria were satisfied.

2.13. Reproducibility and Data Availability

The simulations were deterministic. Component tolerances, sensor offsets, initial conditions, noise sequences, switching carrier phases, communication timing, controller delays, and optimization settings were fixed so that repeated simulations produced identical results.

The model was developed in MATLAB R2026a. Reproducibility requires the complete electrical parameter set, coupling filter tolerances, semiconductor model, controller gains, QUBO weights, variational circuit configuration, FSM thresholds, ADC models, and coherent FFT evaluation intervals reported in the manuscript and accompanying parameter files.

Figure 1 presents the complete architecture of the proposed Quantum Multi-SAPF Hybrid-Switching Power System, integrating the electrical power stage, distributed active power filters, measurement infrastructure, synchronization network, local controllers, quantum supervisory optimization, and protection functions into a unified cyber–physical control platform. The architecture has been designed to achieve simultaneous harmonic mitigation, reactive power compensation, optimal current sharing, DC-link energy balancing, and safe converter operation while satisfying IEEE 519 harmonic limits.

The proposed system consists of a three-phase utility grid supplying a nonlinear six-pulse diode bridge RL load through a realistic feeder impedance.

The Point of Common Coupling (PCC) is the central electrical node where the utility grid, the nonlinear load, and the four parallel SAPFs are interconnected. All electrical quantities required by the supervisory controller, including $v_{abc}$, $i_s$, $i_L$, $i_{f1}$−$i_{f4}$, and $V_{dc1}$−$V_{dc4}$, converter temperatures, and synchronization variables, are continuously measured at this location.

The nonlinear load is modeled as a three-phase six-pulse diode bridge rectifier supplying an RL load, consistent with the MATLAB R2026a simulation framework. Under the investigated operating condition, the nonlinear converter load produces a strongly distorted three-phase current waveform with a measured load current THD of 24.615%. This distorted current constitutes the uncompensated reference condition used to assess the performance of the proposed SAPF. After activation of the QAOA-supervised multi-agent compensation system, the source current THD is reduced from 24.615% to 0.142%, corresponding to a reduction in harmonic distortion. Simultaneously, the compensated grid-side operation achieves a source power factor of 0.99999, limits the residual source reactive power to 0.31 var, and maintains a balanced source RMS current of 14.262 A. These results confirm that the proposed controller effectively isolates the utility grid from the nonlinear current demand of the six-pulse rectifier while providing simultaneous harmonic and reactive current compensation. Because the nonlinear load current exhibits a THD of 24.615%, the total apparent power cannot be represented solely by the fundamental relation of apparent power. Under nearly sinusoidal supply voltage conditions, harmonic current introduces an additional distortion power component. The fundamental apparent power is approximately 13.08 kVA. Including harmonic-current RMS contribution increases total apparent power to approximately 13.47 kVA. The corresponding distortion power term is approximately 3.22 kVA.

The compensation system is composed of four identical shunt active power filters connected in parallel at the PCC. Each converter is coupled to the network through three dedicated inductors ($L_{f1a}$−$L_{f4c}$), having a nominal value of 3.0 mH per phase with 0.030 Ω winding resistance. These inductors attenuate switching harmonics, limit current gradients, suppress circulating currents, and ensure stable current regulation.

Each SAPF contains a two-level IGBT voltage source inverter supplied by an independent 750 V DC-link and controlled by a local real-time controller operating at 15 kHz. The local controllers perform current regulation, DC-link voltage control, PWM generation, and protection independently of the supervisory optimization layer.

The converters employ phase-interleaved PWM with carrier phase shifts of 0°, 90°, 180°, and 270°. Interleaving distributes switching events uniformly over the switching period, reducing the overall current ripple injected into the PCC without increasing the switching frequency of individual converters.

The global coordination is performed by the QAOA–VQE quantum supervisory controller, executed every 50 ms (20 Hz). The QAOA optimizer determines the optimal participation factors for the four SAPFs, balancing current sharing, converter utilization, harmonic compensation, and DC-link energy. The VQE optimizer subsequently computes optimal predictive current references while minimizing harmonic distortion, reactive power, thermal stress, and DC-link voltage deviations under the imposed operating constraints.

A distributed synchronization network based on SOGI-PLL maintains coherent operation of all converters by continuously aligning phase angles and tracking the grid frequency.

The protection layer continuously supervises converter current, DC-link voltage, current gradients, junction temperature, and fault conditions. The validated results confirm safe operation throughout the simulation.

The complete system satisfies the physical current balance at the PCC,

$$i_s=i_L-{\displaystyle \sum _{k=1}^4}{i}_{f,k},$$

where the distributed SAPFs collectively inject the compensating currents required to eliminate harmonic and reactive components from the source current.

The proposed architecture combines fast deterministic local control with quantum-assisted supervisory optimization. The validated results demonstrate a reduction in source current THD %, an improvement in the source power factor, reactive power compensation while maintaining balanced DC-link voltages, and safe operation of all converters.

Figure 2 illustrates the complete cascaded control architecture of the proposed three-phase Shunt Active Power Filter (SAPF), organized as a hierarchical multi-rate control system. The controller is divided into two coordinated layers operating at different sampling frequencies. The outer supervisory loops are executed at approximately 20 Hz and are responsible for determining the optimal compensation current references and regulating the DC-link energy. The inner current control loops operate at 15 kHz, ensuring high-bandwidth tracking of the reference currents through predictive current regulation and pulse-width modulation. This hierarchical organization separates slow energy management tasks from fast current dynamics, improving stability, robustness, and computational efficiency.

• Measurement System

The left-hand side of the architecture represents the measurement subsystem, which continuously acquires the electrical quantities required for feedback control.

The measured variables are:

• Three-phase PCC voltages $v_{sa},v_{sb},v_{sc}$;
• Filter currents $i_{fa},i_{fb},i_{fc}$, DC-link voltage $V_{dc,k}.$

These measurements constitute the physical interface between the converter and the electrical network and are updated every sampling interval.

2.

Grid Synchronization

The measured voltages are processed by a Second-Order Generalized Integrator Phase-Locked Loop (SOGI-PLL).

The PLL estimates $\widehat{\theta }$ and $\widehat{\omega },$which represent the instantaneous grid angle and frequency.

Accurate synchronization is essential because every transformation between the stationary and synchronous reference frames depends on the estimated electrical angle.

The SOGI-PLL provides excellent harmonic rejection while maintaining rapid synchronization under distorted grid conditions.

3.

Supervisory Commands

The optimization layer generates supervisory references that define the operating point of the SAPF.

These commands include:

• Participation factor ${\lambda }_k^{*}$, which determines the amount of compensation required (allocates aggregate compensation among converters);
• DC-link voltage reference $V_{dc}^{*}$
• Reactive power reference $Q_k^{*}$
• Maximum admissible filter current $I_{\mathrm{m}\mathrm{a}\mathrm{x},k}$
• Operating mode $m_k^{*}.$

These supervisory variables allow higher-level optimization algorithms, such as multi-agent coordination or QAOA-based optimization, to adapt the controller according to network conditions.

4.

abc–dq Transformations

The first block of the outer loop performs Clarke and Park transformations.

Using the estimated angle $\widehat{\theta },$ the measured three-phase quantities are converted into the synchronous rotating frame, $abc\to dq.$

The transformation produces $v_d,v_q,i_d,i_q,$ which simplifies the control problem because balanced sinusoidal variables become approximately constant in steady state.

This transformation decouples active and reactive power regulation.

5.

Compensation Current Generation

The second block implements the instantaneous p–q theory.

The instantaneous active and reactive powers are computed as

$$p=v_d{i}_d+v_q{i}_q,$$

$$q=v_q{i}_d-v_d{i}_q.$$

Using the supervisory participation factor ${\lambda }_k^{*}$ together with the reactive power reference $Q_k^{*},$ the controller determines the compensation current references $i_{cd}^{*}$ and $i_{cq}^{*}.$

These currents correspond to the harmonic and reactive components that must be injected by the SAPF to force the source current toward a sinusoidal waveform.

6.

DC-Link Voltage Regulation

The third outer loop regulates the DC-link capacitor voltage. The measured voltage $V_{dc,k}$ is continuously compared with its reference $V_{dc}^{*}.$ The voltage error $e_v=V_{dc}^{*}-V_{dc,k}$ is processed by a PI controller. Its output generates an additional active-current component $i_{d,\mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s}}^{*},$ which compensates converter conduction and switching losses while maintaining constant DC-link energy. The final reference currents become $i_d^{*}=i_{cd}^{*}+i_{d,\mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s}}^{*}$ and $i_q^{*}=i_{cq}^{*}.$ This summation ensures that harmonic compensation and DC-link energy regulation are performed simultaneously without interfering with each other.

7.

Current References

The outputs of the outer loops are combined to generate the final reference vector supplied to the inner controller.

The reference current vector ${\mathbf{i}}^{*}=[i_d^{*},i_q^{*}{]}^T$ contains all the information required for harmonic mitigation, reactive power compensation, and converter loss compensation.

8.

Inner Current Control Loops

The lower part of the figure represents the fast current control layer.

The measured currents $i_d,i_q$ are compared with their references $i_d^{*},i_q^{*}.$

The resulting errors $e_{id},e_{iq}$ are processed by independent PI regulators.

The regulators generate the voltage commands $u_d,u_q.$ Because the synchronous reference frame introduces cross-coupling terms, a feedforward decoupling network is employed.

The decoupling voltages $-\omega L_f{i}_q$ and $+\omega L_f{i}_d$ compensate the coupling between the two control axes, allowing both PI regulators to operate independently.

Consequently, the dynamic response becomes faster and overshoot is reduced.

9.

Current Limitation and Protection

Before modulation, the reference currents pass through a protection block. This subsystem performs current saturation, anti-windup, and converter protection. The objective is to guarantee that $\mid i_f\mid <I_{\mathrm{m}\mathrm{a}\mathrm{x}}$ under every operating condition. This prevents semiconductor overcurrent and preserves converter reliability.

10.

Inverse Transformations

The compensated voltage references $v_d^{*},v_q^{*}$ are transformed back into three-phase quantities through the inverse Park and Clarke transformations.

The controller, therefore, produces $v_a^{*},v_b^{*},v_c^{*},$ which constitute the voltage references required by the PWM modulator.

11.

PWM Modulation

The architecture employs interleaved Space Vector PWM (SVPWM) or Discontinuous PWM (DPWM) operating at $f_{sw}=15 \mathrm{kHz}.$ Carrier phase shifts of $0^{\circ }, {90}^{\circ }, {180}^{\circ }, {270}^{\circ }$ are used between parallel SAPF modules.

Interleaving significantly reduces output current ripple, DC-link current ripple, and electromagnetic interference, while increasing converter efficiency.

The PWM generates the duty cycles $d_a, d_b, d_c$ from which the gate signals $G_a^{\pm },G_b^{\pm },G_c^{\pm }$ are produced.

12.

Power Stage

The right-hand side illustrates the physical converter.

The SAPF consists of a two-level three-phase voltage source inverter, DC-link capacitor, and coupling inductors $L_f,$ which inject the compensation currents $i_{fa}, i_{fb}, i_{fc}$ into the Point of Common Coupling (PCC). The converter synthesizes the compensation voltages generated by the controller and produces the required harmonic compensation current.

13.

Signal Summary

The summaries of all controller inputs and outputs are as follows.

Inputs: three-phase voltages, three-phase currents, DC-link voltage, PLL angle, and supervisory references.

Outputs: converter voltage references, PWM duty cycles, gate signals, and injected compensation currents. This block clearly defines the interface between the digital controller and the physical converter.

Overall Control Principle

The complete control architecture follows a cascaded hierarchy. The slow outer loops estimate the instantaneous power components, regulate the DC-link energy, and generate optimal current references based on supervisory commands. The fast inner loops then ensure that these references are accurately tracked through decoupled PI current regulation, coordinate transformations, and high-frequency PWM modulation. Finally, the power converter injects the required compensation currents into the grid through the coupling inductors, forcing the source current to become sinusoidal and nearly in phase with the PCC voltage.

This hierarchical organization offers several advantages over conventional single-loop controllers. By separating energy regulation from current regulation, the controller achieves independent tuning of slow and fast dynamics, improving transient response and steady-state accuracy. The feedforward decoupling network minimizes cross-coupling between the $d$- and $q$-axes, enabling rapid current tracking and reducing overshoot. Furthermore, the modular supervisory interface allows advanced optimization methods—including multi-agent coordination, adaptive control, or QAOA-based supervisory optimization—to update the outer-loop references without modifying the proven inner current control structure. Consequently, the architecture provides a scalable and industrially robust framework capable of delivering high-quality harmonic compensation, nearly unity power factor, stable DC-link voltage regulation, and safe converter operation under widely varying operating conditions.

The control architecture of the proposed three-phase Shunt Active Power Filter (SAPF) is organized into two hierarchical control levels operating at different time scales (Figure 2). The architecture separates slow supervisory functions from high-speed current regulation, allowing independent optimization of energy management and converter dynamics. This hierarchical organization significantly improves stability, simplifies controller tuning, and enables the integration of advanced supervisory optimization algorithms without affecting the deterministic behaviour of the inner current controller.

The control process begins with the measurement subsystem, where the three-phase PCC voltages, filter currents, and DC-link voltage are continuously acquired. These signals provide the real-time electrical state of the converter and the power system. The measured voltages are processed by a Second-Order Generalized Integrator Phase-Locked Loop (SOGI-PLL), which accurately estimates the grid angle and frequency even under distorted operating conditions. The estimated electrical angle establishes the synchronous reference frame required by all subsequent control algorithms.

The supervisory optimization layer supplies high-level operating commands, including the participation factor, DC-link voltage reference, reactive power reference, converter current limit, and operating mode. These supervisory variables allow adaptive optimization algorithms to modify the operating point of the SAPF according to the instantaneous grid conditions, harmonic content, or converter operating constraints while maintaining complete compatibility with the lower-level deterministic controller.

Within the outer control loops, the measured three-phase voltages and currents are transformed into the synchronous $dq$ reference frame using the Clarke and Park transformations. In this rotating reference frame, the sinusoidal variables become nearly constant under steady-state conditions, allowing active and reactive power to be regulated independently. The transformed quantities form the basis for the instantaneous power calculations used throughout the supervisory control layer.

The compensation current generation block implements the instantaneous $p$-$q$ theory to determine the active and reactive current components required for harmonic mitigation and reactive power compensation. The instantaneous active and reactive powers are calculated from the $dq$-axis voltages and currents, while the supervisory participation factor and reactive power reference determine the desired compensation level. Consequently, the controller generates the reference compensation currents that eliminate harmonic distortion and force the source current to remain sinusoidal and nearly in phase with the supply voltage.

The second outer loop performs DC-link voltage regulation. The measured capacitor voltage is continuously compared with its reference, and the resulting voltage error is processed by a proportional–integral controller. Rather than modifying the harmonic compensation strategy, this controller produces an additional active-current component that compensates converter conduction and switching losses while maintaining constant DC-link energy. The active current generated by the voltage controller is added to the compensation current reference, producing the final current references supplied to the inner control loops.

The inner current control layer operates at the converter switching frequency and provides the fast dynamic response required for accurate current tracking. Independent PI controllers regulate the $d$- and $q$-axis currents using the errors between the measured and reference currents. To eliminate the dynamic coupling naturally introduced by the synchronous reference frame, feedforward decoupling terms proportional to the filter inductance and grid frequency are added to the controller outputs. This compensation significantly improves bandwidth, reduces overshoot, and enables independent regulation of the active and reactive current components.

Before modulation, the controller incorporates current limitation and anti-windup protection to guarantee that the commanded current remains within the converter Safe Operating Area (SOA). These protection mechanisms prevent excessive semiconductor stress while preserving the dynamic response of the current regulators. As a result, converter reliability is maintained even during severe load transients or abnormal operating conditions.

The compensated voltage references generated by the current controllers are transformed back into three-phase quantities through the inverse Park and inverse Clarke transformations. These three-phase voltage references are subsequently processed by an interleaved Space Vector Pulse-Width Modulation (SVPWM) or Discontinuous PWM (DPWM) strategy operating at a switching frequency of 15 kHz. The phase-shifted carrier arrangement reduces current ripple, distributes switching losses more uniformly among parallel converters, and improves overall converter efficiency.

The power stage consists of a conventional two-level three-phase voltage source inverter supplied by the regulated DC-link capacitor. Through the coupling inductors, the inverter injects the calculated compensation currents into the Point of Common Coupling (PCC), thereby cancelling the harmonic and reactive components drawn by the nonlinear load. Consequently, the utility supplies only the balanced fundamental active current required by the load, while the SAPF provides the remaining compensation currents.

The proposed cascaded architecture combines slow supervisory optimization with fast deterministic current regulation in a physically consistent and computationally efficient framework. The outer loops determine the optimal compensation objectives and maintain DC-link energy, whereas the inner loops guarantee precise current tracking through high-bandwidth decoupled control and PWM modulation. This modular organization facilitates the integration of advanced optimization techniques (QAOA-based supervisory optimization) while preserving the robustness, stability, and real-time performance required for industrial active power filtering applications.

Figure 3 (Appendix A) presents the complete hierarchical control architecture of the proposed Distributed Quantum Multi-SAPF system. The workflow is organized into two coordinated control layers operating at different time scales. The supervisory optimization layer executes asynchronously at 20 Hz and determines the optimal operating conditions for the distributed converters, whereas the local deterministic controllers execute at 15 kHz and perform real-time regulation of the compensation currents. This multi-rate organization separates computationally intensive optimization from fast electrical control, allowing advanced supervisory decision-making without compromising deterministic real-time operation.

The workflow begins with the measurement block, where all electrical variables required for control are acquired from the power system. These include the three-phase grid voltages, source currents, nonlinear load currents, SAPF currents, DC-link voltages, converter temperatures, active and reactive powers, power factor, current harmonic distortion, PLL angle, and grid frequency. These synchronized measurements provide a complete representation of the instantaneous operating condition of the distributed filtering system and form the input to the supervisory controller.

The measured signals are processed by the State Estimation and Signal Processing block. Anti-alias filtering removes measurement noise, Clarke and Park transformations convert the electrical variables into the synchronous reference frame, harmonic extraction isolates the distortion components, RMS estimation computes steady-state quantities, and the SOGI-PLL estimates the grid phase and frequency. The output is a compact estimated state vector that accurately describes the electrical state of the complete multi-SAPF system while reducing the dimensionality of the optimization problem.

The supervisory layer contains two complementary optimization stages. The QAOA branch addresses the discrete coordination problem by selecting a prevalidated operating profile from the encoded supervisory profile set. The four-bit representation determines discrete controller parameters such as the current loop time constant, DC-link energy loop gains, and current envelope. QAOA, therefore, answers the question of which admissible operating profile should be activated. The continuous participation vector is not decoded directly from these four QAOA bits; participation and current sharing belong to the subsequent continuous allocation/refinement and feasibility process.

After the discrete profile decision, the VQE/VQA-assisted predictive branch provides a bounded supervisory refinement. A continuous constrained problem is not passed directly to a finite-qubit VQE. Instead, bounded refinement variables are represented with finite resolution, their predictive costs define a finite dimensional Hermitian cost operator, and the selected candidate is deterministically decoded. In the present numerical study, this stage is implemented as a hybrid numerical supervisory refinement rather than execution on a physical quantum processor. Its output is advisory and is never applied directly as a PWM command.

The outputs of the two optimization branches are merged in the Fusion and Feasibility Projection block. Here, the discrete allocation decisions from the QAOA branch are combined with the continuous operating references generated by the VQE branch. The resulting solution is checked against converter current limits, Safe Operating Area constraints, DC-link voltage limits, and operating restrictions. Only physically feasible operating points are accepted, guaranteeing that every supervisory command can be safely implemented by the local controllers.

The validated supervisory solution is organized into a reference packet, which is updated every 50 ms (20 Hz). This packet contains the current references, DC-link voltage references, reactive power references, operating modes, current limits, and converter availability information for each SAPF module. The reference packet represents the interface between the supervisory optimization layer and the deterministic control layer.

The lower portion of the figure illustrates the local deterministic controller, which executes independently for every SAPF converter at 15 kHz. Each controller receives the supervisory reference packet together with locally measured voltages, currents, DC-link voltage, and grid variables. The controller first performs SOGI-PLL synchronization, estimating the grid angle required for synchronous reference frame control.

The synchronized variables are supplied to the current reference generation block, where the instantaneous $p$-$q$ theory computes the compensation current references assigned to the corresponding SAPF converter. The DC-link regulation block simultaneously maintains constant capacitor energy by adjusting the active-current component needed to compensate converter losses. These two outer loops generate the final current references for the inner current controller.

The current regulation block constitutes the high-bandwidth inner control loop. Operating in the synchronous reference frame, PI or PR regulators accurately track the reference currents and generate the converter voltage commands. Their outputs are supplied to the PWM generation block, which performs interleaved PWM modulation with dead time compensation to generate the IGBT gate signals.

Finally, the deterministic controller produces the converter voltages and compensation currents injected into the Point of Common Coupling. These currents cancel the harmonic and reactive components drawn by the nonlinear load, thereby restoring nearly sinusoidal source currents and a power factor close to unity.

The dashed feedback path highlights the closed-loop cyber–physical operation of the proposed architecture. The compensation currents continuously modify the electrical state of the network, new measurements are acquired, and the supervisory optimization is repeated every 20 Hz, while the deterministic controller continues regulating the converter every 15 kHz. Consequently, 750 deterministic control cycles are executed between two consecutive supervisory updates. This hierarchical arrangement enables computationally intensive quantum-assisted optimization to improve converter coordination while preserving the fast dynamic response, stability, and deterministic behaviour required for industrial active power filters.

2.14. Scope of Quantum-Assisted Validation and Real-Time Interface

The present manuscript demonstrates the quantum-assisted supervisory formulation within a numerical simulation workflow; it does not claim execution on physical quantum hardware. Accordingly, the reported electrical performance should be interpreted as numerical validation of the hierarchical control concept rather than as experimental or HIL validation. The local controllers do not wait for a quantum result: a validated reference packet is held or smoothly rate-limited between 20 Hz supervisory updates, while protection and current regulation continue independently at 15 kHz.

This separation also clarifies the distinct roles of QAOA and VQE/VQA. QAOA addresses discrete profile selection. The VQE/VQA-assisted branch addresses bounded predictive refinement after the discrete decision. The continuous participation vector is generated by the downstream allocation/refinement and feasibility stage rather than decoded from the four QAOA bits. All supervisory candidates are projected onto the feasible electrical, thermal, modulation, participation, and SOA constraint set before transmission to the local controllers. Therefore, neither quantum-assisted stage directly generates PWM switching states.

For the four-converter benchmark, the discrete search space is intentionally small, and a classical exhaustive or heuristic solver is entirely practical. The present contribution is, therefore, the architecture and formulation of a quantum-assisted supervisory layer, not a demonstrated quantum speed advantage. A rigorous claim of computational advantage would require identical instance benchmarks reporting objective value, feasibility rate, wall clock latency, iteration/shot count, and scaling with the number of converters and encoded decisions.

2.15. Stability Interpretation of the Multi-Rate Interface

The slow supervisor is treated as a bounded reference generator rather than as part of the fast-switching loop. For a decoupled local current channel with coupling inductance $L_f$ and resistance $R_f$, a PI-controlled first-order model can be written as

$$L_f {\displaystyle \frac{d{i}_e}{dt}}+R_f i_e=v_e, C_i(s)=K_p+{\displaystyle \frac{K_i}{s}}$$

(43)

$${\displaystyle \frac{K_i}{K_p}}={\displaystyle \frac{R_f}{L_f}}$$

(44)

In (43),$i_e = i_F^{*} - i_F$denotes the local current-tracking error (reference minus measured filter current) in the considered decoupled channel, while $v_e$ denotes the corresponding controller/equivalent error voltage applied to the first-order coupling-branch model. Thus, the symbols used in the stability model are explicitly linked to the physical SAPF current loop. With pole-zero cancellation, the nominal complementary sensitivity becomes first order, and the closed-loop pole is strictly in the left half-plane for positive gains. More generally, if the local closed-loop matrix $A_c$ is Hurwitz, a positive definite $P$ exists for any $Q > 0$ such that

$${A_c}^T P+P A_c=-Q$$

(45)

The corresponding quadratic Lyapunov function establishes local exponential stability for a fixed supervisory packet. Bounded packet changes enter as bounded exogenous reference perturbations, giving an input to state stability interpretation. This analysis does not replace a full impedance/Nyquist validation of a hardware implementation, but it explains why the 20 Hz layer is not allowed to modify the 15 kHz plant dynamics directly.

2.16. Hardware Non-Idealities and Validation Scope

The numerical model includes semiconductor conduction loss terms, dead time, quantization/noise, parameter tolerances, modulation saturation, and digital delay. For a representative dead time $t_d = 2 \mathsf{\mu }\mathrm{s}$ and local period $T_L =66.67 \mathsf{\mu }\mathrm{s}$, the normalized dead time fraction is

$${\delta }_{dt}={\displaystyle \frac{t_d}{T_L}}={\displaystyle \frac{2}{66.67}} \approx 0.030=3.0\%$$

(46)

At $V_{dc} = 750 \mathrm{V}$, this percentage illustrates why dead time compensation and experimental verification are important even when nominal current headroom is large. The numerical study is, therefore, classified as Level I/II model validation rather than HIL or experimental proof. Junction temperature dependence, processor execution jitter, gate driver behaviour, and device-specific switching energy maps remain targets for subsequent SIL/PIL/HIL and laboratory validation.

2.17. Practical Scalability and Real-Time Feasibility of the Quantum-Assisted Supervisor

For the present four-bit QAOA profile selector, the discrete search space contains only 16 states. Exact classical enumeration is, therefore, inexpensive and is the correct reference solver. In general, for $n$ binary decision variables, the state count grows as $N_{state} = 2^n$. The present contribution is, therefore, not a demonstrated quantum speed advantage.

$$N_{state}=2^n, N_{state}(4)=16, N_{state}(20)=\mathrm{1,048,576}$$

(47)

A future hardware implementation must satisfy an end-to-end supervisory deadline rather than a gate-level switching deadline. With supervisory period $T_S = 50 \mathrm{m}\mathrm{s}$, the admissible latency budget is

$$T_{tot}=T_{meas}+T_{encode}+T_{opt}+T_{decode}+T_{comm}+T_{safe} \le 50\mathrm{m}\mathrm{s}$$

(48)

The current study contains no physical QPU wall clock measurements. Actual NISQ latency must include circuit compilation, shot acquisition, readout, classical optimizer iterations, network/queue delay when applicable, and error mitigation overhead. A late or infeasible result is not applied; the last validated packet is retained while local current regulation and protection continue independently.

2.18. QUBO Weight Sensitivity and Communication Robustness Protocol

The QUBO/surrogate weights are engineering normalization and tuning coefficients rather than universal constants. Robustness should, therefore, be assessed overload and grid scenarios and over deliberate weight perturbations. For objective $J$ and weight $w_i$, a normalized sensitivity indicator is

$$S_{w\_i}={\displaystyle \frac{\Delta J\frac{1}{J}}{\Delta w_i\frac{1}{w_i}}}$$

(49)

Recommended tests include ±10%, ±20%, and ±30% perturbations of each normalized weight together with variations in load amplitude, load THD, grid short-circuit strength, X/R ratio, DC-link deviation, and thermal headroom. The complete factorial sweep is not part of the present validated dataset and is, therefore, stated as a required robustness study rather than as a completed result.

Communication robustness is treated similarly. Because the local controllers are autonomous, missing supervisory packets invoke hold last valid operation. With communication delay ${\tau }_c$, supervisory period $T_S$, number of lost packets $N_{lost}$, and number of transmitted packets $N_{sent}$, delay and packet loss should be quantified using

$$D_{norm}={\displaystyle \frac{{\tau }_c}{T_S}}, p_{loss}={\displaystyle \frac{N_{lost}}{N_{sent}}}$$

(50)

$${e_{share}}^2={\displaystyle \frac{1}{N}} {\displaystyle {\sum }_{k=1}^N}{[i_{F,k}-{\lambda }_k i_{F,\Sigma }]}^2$$

(51)

For example, delays of 5, 10, and 25 ms correspond to 0.10, 0.20, and 0.50 of one supervisory period $T_S$, respectively. These values are proposed test points, not measured communication results. Larger arrays should use hierarchical clustering so that high-bandwidth electrical states remain local and only aggregate capability, availability, thermal headroom, and participation requests are communicated upward.

3. Results

The reported validation corresponds to the SAPF QAOA Multi-Agent hierarchical control architecture operated with a 15 kHz switching/control frequency, a 50 Hz grid frequency, and a 750 V DC-link; reference current sensor offsets of +8 mA, −6 mA, +5 mA, and −7 mA were assigned to SAPFs 1–4, respectively. This is important because optimizing only one of these quantities can easily degrade another; the reported operating point instead represents a coordinated multi-objective solution.

3.1. Numerical Results

The principal power quality result is the reduction in source current THD from a load-side value of 24.615% to only 0.142%. This corresponds to approximately 99.423% harmonic reduction. The result demonstrates that the SAPF supplies almost the entire non-fundamental current demanded by the nonlinear load, leaving the grid to provide the fundamental active-current component predominantly.

A source THD of 0.142% is not merely below a conventional 5% current distortion reference; it is also comfortably below the project’s more demanding 1% performance objective. The large margin indicates that the selected profile does not operate close to the acceptance boundary. It, therefore, provides room for realistic degradations caused by measurement noise, dead time, parameter uncertainty, or digital delay in a subsequent implementation.

The reduction is especially significant because it is achieved at 15 kHz rather than the 20 kHz case. The result shows that the control architecture retains essentially the same harmonic performance after the switching frequency is reduced, which is relevant for switching loss reduction and embedded implementation.

The final source power factor is 0.99999, while the residual source reactive power is only 0.31 var. These values show that the controller has practically eliminated the fundamental reactive current component while preserving the active component required by the load and converter losses. From the grid perspective, the compensated load, therefore, behaves almost as an ideal active load.

This result confirms that harmonic compensation and reactive power compensation are not competing destructively in the final tuning. The QAOA-supervised profile and the underlying dq/p-q control structure provide sufficient coordination to maintain both extremely low distortion and nearly unity power factor.

The current tracking RMS error is 0.026 A. Relative to the 14.262 A source RMS current; this represents only about 0.182% of the grid current magnitude. Such a small error indicates that the fast inner current loop accurately follows the compensation references generated by the outer supervisory and energy control layers.

The aggregate filter current requirement is 3.497 A RMS with a peak value of 7.664 A. As the Profile 16 peak current limit is 44 A, the observed peak represents only 17.42% of the specified current envelope, leaving approximately 82.58% peak current headroom. Therefore, the reported harmonic suppression is not obtained through persistent current saturation or operation close to the imposed current constraint. This substantial reserve is beneficial for transient disturbances, load changes, parameter uncertainty, and temporary redistribution of compensation effort among the four SAPFs.

The mean DC-link voltage is 748.84 V for a 750 V reference, corresponding to a mean offset of approximately −1.16 V, which, when normalized with respect to the reference voltage, gives −0.155%.

The DC-link result demonstrates effective energy balancing. The outer energy regulator supplies the small active-current component required to compensate converter losses without materially disturbing the source current waveform. This decoupling between the slower energy loop and the faster current loop is essential: aggressive voltage regulation could otherwise inject low-frequency current distortion and degrade THD or power factor. The small negative offset indicates that the energy control loop establishes an operating equilibrium slightly below the nominal reference rather than exhibiting a significant loss of DC-link regulation. The resulting active-current correction must evolve sufficiently slowly relative to the inner current controller. This bandwidth separation is important because excessively aggressive DC-link regulation can modulate the fundamental active-current reference and introduce additional low-frequency spectral components, thereby degrading source current THD and potentially the power factor. The reported combination of very low source THD, near-unity PF, and tightly regulated DC-link voltage, therefore, supports effective dynamic separation between the energy regulation and current tracking functions.

The ripple value is far below the 1% objective, providing substantial design margin. At the same time, the nonzero ripple is physically more credible than an artificially clamped or numerically constant DC-link voltage.

The final source current unbalance is only 0.026%, indicating nearly identical RMS currents in the three phases. This confirms that the compensation mechanism does not introduce significant negative sequence current and that the multi-agent structure preserves phase symmetry.

The maximum modulation index is 0.763 pu. Relative to a normalized upper boundary of 1 pu, approximately 23.7% normalized modulation reserve remains. This voltage headroom is important for rejecting disturbances and tracking rapidly changing compensation references without entering overmodulation. Taken together, the DC-link regulation, 0.026% source current unbalance, 0.763 pu maximum modulation index, low current utilization, and reported SOA PASS indicate that the high harmonic compensation performance is obtained with substantial electrical operating margin rather than through operation close to the converter voltage or current boundaries.

Profile 16 is the final selected and nominally dominant QAOA profile in the complete time-domain supervisory simulation. Its parameters—τ_I = 40 microseconds, K_pE = 12.00, K_iE = 90.0, and I_max = 44 A—define the final nominal operating personality. Temporary profile changes during startup or disturbances represent supervisory adaptation. Importantly, Profile 16 is not claimed to be the unique minimizer of a representative frozen QUBO snapshot; the measured state and the 16 candidate costs evolve with time, so the effective supervisory cost landscape is time dependent.

The final profile is physically feasible with substantial reserve. The reported 7.664 A peak filter current uses approximately 17.42% of the 44 A profile envelope, leaving 82.58% peak current headroom. The mean DC-link value of 748.84 V relative to the 750 V reference corresponds to an offset of −1.16 V (−0.155%). A maximum modulation index of 0.763 pu leaves 23.7% normalized modulation reserve. Together with 0.026% source current unbalance and SOA PASS, these margins show that the reported power quality performance is not obtained through persistent current or modulation saturation.

3.1.1. +50% Load Step Transient Validation

To address dynamic viability explicitly, the nonlinear load current amplitude was increased by 50% at $t = 0.80 \mathrm{s}$. The measured load RMS current increased from approximately 14.57 A to 21.85 A. In the validated transient run, source current THD remained below 1% throughout the event; the reported 0 s THD recovery, therefore, means that the threshold was never violated, not that the physical transient was instantaneous. The DC-link voltage remained within the ±1% settling band, with approximately 0.563% undershot and 0.332% overshoot. Source PF recovered above 0.995 in 90 ms, while the one-cycle tracking RMS error recovered below 0.10 A in approximately 1.3 ms. Relative to $T_S = 50 \mathrm{m}\mathrm{s}$, this is

$${\displaystyle \frac{t_{track}}{T_S}}={\displaystyle \frac{1.3 \mathrm{m}\mathrm{s}}{50 \mathrm{m}\mathrm{s}}} \approx 0.026=2.6\%$$

(52)

This time scale comparison confirms that fast disturbance rejection is produced by the deterministic local current loop, whereas the 20 Hz supervisor changes slower allocation and operating point decisions. The transient modulation index reached 1.000 pu briefly, and the overall SOA test remained PASS.

3.1.2. Five-Case Attribution and Classical Benchmark

An identical condition ablation compared DET_ONLY, CLASSICAL_SUP, QAOA_ONLY, VQE_ONLY, and FULL_QAOA_VQE. Steady-state source current THD values were 0.12031%, 0.11948%, 0.12031%, 0.12031%, and 0.12031%, respectively. Thus, exact classical supervision changed THD relative to DET_ONLY by only 0.00083 percentage points, quantified as

$$\Delta {THD}_{CLASS-DET}=0.11948-0.12031=-0.00083 percentage points$$

(53)

The ablation, therefore, confirms that the extremely low steady-state THD is primarily attributable to deterministic compensation reference generation, high-bandwidth current tracking, converter headroom, and the common modulation architecture. The quantum-assisted layer should be interpreted as a supervisory coordination mechanism rather than the direct source of harmonic cancellation.

Under the +50% load step, peak THD was 0.16798% for DET_ONLY, 0.16709% for CLASSICAL_SUP, 0.16113% for QAOA_ONLY, 0.16586% for VQE_ONLY, and 0.15868% for FULL_QAOA_VQE. The relative reduction in the peak THD for FULL_QAOA_VQE with respect to DET_ONLY is

$$G_{THD,FULL}={\displaystyle \frac{0.16798-0.15868}{0.16798}}\times 100\% \approx 5.54\%$$

(54)

The full case, therefore, gave the lowest peak THD in this tested disturbance, but it was not uniformly superior: the QAOA-based cases exhibited a larger DC-link undershoot and smaller overshoot than DET_ONLY. PF recovery remained approximately 90 ms in all cases. These results demonstrate supervisory trade-off shaping, not a universal quantum advantage.

3.1.3. Technological Interpretation of the Ablation Results

A five-case ablation study was performed under identical electrical and control conditions to separate the deterministic compensation chain from the supervisory optimization. DET_ONLY, CLASSICAL_SUP, QAOA_ONLY, VQE_ONLY, and FULL_QAOA_VQE produced steady-state source current THD values of 0.12031%, 0.11948%, 0.12031%, 0.12031%, and 0.12031%, respectively. Hence, the ultra-low steady-state THD is primarily attributable to the deterministic p-q reference generator, high-bandwidth local current controller, converter headroom, and common modulation architecture. Under the +50% nonlinear load current amplitude disturbance, the corresponding peak THD values were 0.16798%, 0.16709%, 0.16113%, 0.16586%, and 0.15868%. The full supervisor, therefore, reduced peak transient THD by approximately 5.54% relative to DET_ONLY, while not dominating every transient metric. The approximately 1.1–1.3 ms tracking recovery is generated by the 15 kHz deterministic local controller rather than the 20 Hz supervisor.

3.2. Figures and Tables

The numerical dashboard of the SAPF QAOA Multi-Agent controller at 15 kHz is presented in Figure 4.

The dashboard (Figure 4) demonstrates a clear separation between fast deterministic compensation and slower supervisory adaptation. The local current control layer is responsible for the instantaneous waveform tracking and harmonic cancellation, whereas the QAOA supervisory layer selects among predefined controller profiles according to the observed operating condition. This hierarchical organization is important because the high-frequency current control task does not depend on a quantum optimization result at every switching sample. Instead, the supervisory decision modifies the operating envelope and tuning on a slower time scale, while the local loop continuously enforces the compensation current reference, DC-link regulation, modulation constraints, and current limits. The figure, therefore, supports the contribution of a multi-rate architecture in which supervisory optimization and deterministic converter control have distinct and complementary roles.

Figure 4a compares the nonlinear load current with the compensated source current. The visibly distorted load waveform becomes nearly sinusoidal at the source, providing direct time-domain evidence that the SAPF prevents most load-generated harmonic current from propagating upstream. Figure 4b shows phase A compensation current reference and the actual filter current. Their close overlap, together with the 0.026 A RMS tracking error, confirms accurate high-bandwidth local current regulation and shows that fast harmonic tracking is performed by the deterministic control layer. Figure 4c presents the DC-link voltage. Following the controlled startup, the voltage converges smoothly to the 750 V reference (dash line) and remains tightly regulated, with a mean value of 749.83 V and only 0.059% ripple, demonstrating stable converter energy regulation during compensation. Figure 4d illustrates the startup state machine. The ordered PRECHARGE–COUPLING–NOMINAL sequence provides a controlled transition from DC-link energization to full compensation and highlights the implementation-oriented supervisory structure of the proposed SAPF. Figure 4e shows the online source current THD. After the startup and estimator window transient, THD falls below the 1% criterion (dash line) and remains very low, reaching 0.142% in the final evaluation. Relative to the 24.615% load THD, this represents a 99.422% reduction. Figure 4f depicts the source power factor. It rapidly approaches unity and remains above the 0.995 requirement (dash line) during nominal operation, with a final value of 1.00, confirming that harmonic compensation is accompanied by effective fundamental reactive current compensation. Figure 4g presents the source of reactive power. After the initial transient, reactive power converges close to zero (dash line) and reaches approximately 0.30 var in the final operating condition, consistently supporting the near-unity power factor reported in Figure 4f. Figure 4h illustrates the QAOA supervisory action through the selected profile index. The profile changes as the operating condition evolves, while Profile 16 becomes dominant in the final interval. This behavior highlights QAOA as a slower discrete supervisory selector rather than a switching frequency current controller. Figure 4i summarizes the harmonic compensation result by directly comparing load and source THD. The reduction from 24.615% to 0.142% makes the source-side distortion almost negligible on the same graphical scale and emphasizes the effectiveness of the deterministic compensation mechanism. Figure 4j shows PWM utilization. The modulation index remains within the normalized limit (dash line) and reaches a maximum of 0.764 pu over the final reporting interval, leaving approximately 23.6% of the normalized modulation range unused under the reported steady-state condition. Figure 4k compares the RMS source currents of phases A, B, and C. Their nearly identical values produce only 0.026% current unbalance, indicating that the compensation strategy preserves excellent three-phase symmetry while suppressing harmonic distortion. Figure 4l consolidates the principal performance indicators. The system achieves 0.142% source current THD, unity power factor, 0.059% DC-link ripple, 0.026 A RMS tracking error, and SOA PASS. With a 7.658 A peak filter current compared with the 44 A Profile 16 controller envelope, only about 17.4% of that envelope is utilized, corresponding to approximately 82.6% simulated current envelope reserve.

The complete Figure 4 demonstrates the complementary operation of two control time scales. The deterministic local layer provides fast current tracking, harmonic cancellation, DC-link regulation, and converter constraint enforcement responsible for the ultra-low steady-state distortion, whereas the QAOA layer performs slower discrete operating profile adaptation. The combined results, therefore, support the proposed hierarchical multi-rate architecture: supervisory optimization can modify operating decisions without placing quantum-assisted computation directly in the switching frequency control path. In

Table 4. Fulfilment of the principal control objectives.

Objective	Target	Result	Status	Assessment
Source current harmonic distortion	THD < 1%	0.142%	ACHIEVED	Large margin. Very low residual harmonic distortion.
Power factor	PF > 0.995	0.99999	ACHIEVED	Practically unity power factor.
Reactive power compensation	Qs approximately 0	0.31 var	ACHIEVED	Residual reactive exchange is negligible.
Current reference tracking	RMS error < 0.5 A	0.026 A	ACHIEVED	Only 5% of the 0.5 A limit. High-fidelity reference tracking.
DC-link ripple	<1%	0.059%	ACHIEVED	More than one order of magnitude below the limit.
Source current balance	Very low unbalance	0.026%	ACHIEVED	Near-perfect phase symmetry.
Current SOA	If,peak < Imax	7.66 A < 40 A	ACHIEVED	Large current reserve.
Modulation feasibility	mmax < 1 pu	0.763 pu	ACHIEVED	Approximately 23.7% modulation reserve.
Final QAOA profile	16	PASS	Selected	Active discrete supervisory selection.
Overall electrical SOA	No limit violation	PASS	ACHIEVED	Validated for the reported simulation.

fulfilment of the principal control objectives are depicted.

4. Discussion

Figure 4 supports a hierarchical control interpretation in which the fastest dynamics remain deterministic, while QAOA operates at the supervisory level. This is an appropriate division of responsibilities for an industrial SAPF: the quantum layer can explore discrete controller configurations or allocation policies without being placed in the safety-critical semiconductor switching path.

The figure also demonstrates near-unity PF, negligible reactive power, stable DC-link voltage, low tracking error, balanced phase currents, adequate PWM reserve, successful state machine progression, and an explicit final supervisory profile. This multi-criterion evidence makes the claimed system-level improvement considerably stronger than a single harmonic spectrum or THD value.

The QAOA profile trajectory further demonstrates supervisory adaptability. Rather than presenting the optimizer only as an offline tuning mechanism, the figure depicts profile selection during system operation. The local controller then executes the selected configuration while maintaining continuous current tracking and DC-link regulation.

The principal power quality objective is fulfilled: the source current THD is reduced to 0.142%, corresponding to approximately 99.4% harmonic reduction. The displacement/reactive current objective is also fulfilled because the source power factor reaches 1.00000 and the reactive power converges close to zero. The DC-link objective is fulfilled by maintaining a mean voltage of 749.83 V with only 0.059% ripple.

The dynamic control objective is supported by 0.026 A current tracking error and by the close overlap of reference and actual SAPF current. The hardware utilization objective is supported by PWM operation below sustained saturation, while the symmetry objective is confirmed by only 0.026% current unbalance. Finally, the supervisory objective is fulfilled by the successful PRECHARGE → COUPLING → NOMINAL transition and the active selection of QAOA Profile 16. Taken together, the dashboard provides an integrated PASS-level demonstration of the QAOA-supervised SAPF architecture.

The dashboard also indicates a robust operating power system. The modulation index remains below 0.8 pu, and the peak filter current is far below the 44 A limit. Consequently, the final SOA PASS is consistent with the plotted operating variables. For experimental validation, the same dashboard should be extended with semiconductor junction temperature, dead time distortion, measurement noise, computation/PWM delay, and grid voltage distortion so that the numerical margins can be verified under hardware-realistic conditions.

4.1. Scalability and Evidence Interpretation

The numerical results should be interpreted within the scope of the proposed hierarchical architecture and the validation conditions considered in this study. The ablation analysis demonstrates that the ultra-low steady-state source current THD is primarily achieved by the deterministic compensation layer, including the instantaneous $p$-$q$-based reference generation, high-bandwidth local current regulation, and interleaved PWM. The QAOA and VQE/VQA-assisted supervisory stages, therefore, complement rather than replace the deterministic control layer, providing discrete operating profile selection, bounded predictive refinement, coordinated resource allocation, and transient multi-objective adaptation.

The present QAOA formulation employs a four-bit encoding corresponding to 16 candidate operating profiles. At this problem size, exhaustive classical evaluation remains computationally straightforward; consequently, the reported results should not be interpreted as evidence of computational quantum advantage. Instead, the quantum-assisted formulation establishes a supervisory optimization framework that can be extended to larger distributed converter systems. Practical scaling should rely on hierarchical decomposition, converter clustering, reduced supervisory decision spaces, warm start strategies, and event-triggered optimization rather than direct monolithic expansion of the binary search space.

The multi-rate architecture provides an additional basis for scalability by separating the 15 kHz deterministic local control dynamics from the 20 Hz supervisory optimization. Approximately 750 local control updates are, therefore, executed during each 50 ms supervisory intervals. Harmonic current tracking, DC-link regulation, PWM generation, current limiting, and protection remain local and deterministic and do not depend on completion of the supervisory optimization at every local sampling instant. This separation allows the supervisory layer to address slower coordination, thermal, allocation, and operating profile objectives without directly determining converter switching actions.

Nevertheless, the present validation does not establish real-time execution on physical NISQ hardware or hardware-level scalability. Practical implementation must additionally account for quantum-processing latency, circuit execution and measurement overhead, classical optimizer iterations, communication delay and packet loss, and sensitivity to QUBO weighting coefficients. These aspects require dedicated larger-scale numerical studies followed by HIL and experimental validation. Accordingly, the scalability demonstrated here should be interpreted primarily as architectural and control-level scalability, rather than as experimentally demonstrated quantum computational scalability. This hierarchical interpretation is consistent with recent developments in hierarchical optimization [52] and multi-rate distributed inverter control and stability [53]. Accordingly, novelty is the physically structured integration of discrete supervisory optimization, bounded continuous variational refinement, deterministic feasibility filtering, and fast local converter control. The architecture creates a reproducible framework in which future quantum hardware or improved classical/quantum solvers can be compared without placing non-deterministic computation in the safety critical switching loop.

4.2. Practical Scalability, Real-Time Feasibility, and Communication Robustness

Practical real-time feasibility is governed by the $T_S = 50 \mathrm{m}\mathrm{s}$ supervisory deadline, not by the $T_L = 66.67 \mathsf{\mu }\mathrm{s}$ PWM/current control period. The complete supervisory latency is decomposed as

$$T_{tot}=T_{meas}+T_{enc}+T_{opt}+T_{dec}+T_{comm}+T_{safe}$$

(55)

$$T_{tot} \le T_S=50 \mathrm{m}\mathrm{s}$$

(56)

The present study does not provide measured end-to-end latency from physical NISQ hardware. Actual latency would include circuit compilation, queueing, repeated shots, readout, classical optimizer iterations, error mitigation, decoding, feasibility projection, and communication. Therefore, execution of the complete QAOA/VQE supervisory cycle within the 50 ms deadline is not demonstrated. If a new supervisory result is late, invalid, or infeasible, it is rejected, and the last validated packet is retained while the 15 kHz local current regulation, protection, and SOA enforcement continue independently.

The current four-bit selector contains only 16 candidate states; exhaustive classical evaluation is, therefore, computationally trivial. No quantum speedup is claimed at this problem size. Scaling to larger converter arrays should use hierarchical decomposition, clustering, reduced supervisory variables, warm starts, and event-triggered optimization rather than naive monolithic growth of the binary search space. Representative state space sizes are

$$N_{state}(20)=2^{20}=\mathrm{1,048,576}, N_{state}(40)=2^{40} \approx 1.10\times {10}^{12}$$

(57)

For identical condition benchmarking, the steady-state classical supervisor achieved 0.11948% THD versus 0.12031% for deterministic-only control, while the full QAOA–VQE case also remained approximately 0.12031%. Under the +50% nonlinear load current amplitude step, the full case reduced peak THD from 0.16798% to 0.15868%. Defining $G_{THD}$ as the relative peak THD reduction with respect to DET_ONLY gives

$$G_{THD}={\displaystyle \frac{0.16798-0.15868}{0.16798}}\times 100\% \approx 5.54\%$$

(58)

The value $G_{THD} \approx 5.54\%$ quantifies the transient peak THD improvement for this controlled disturbance. It is not a universal dominance result because the FULL QAOA–VQE case exhibits a larger DC-link undershoot than DET_ONLY. The quantum-assisted supervisor is, therefore, interpreted as a mechanism for coordinated transient trade-offs and constraint-aware allocation rather than as demonstrated computational-speed superiority.

The QUBO weights are engineering normalization and tuning parameters and must be tested overload and grid scenarios. For objective $J$ and a generic weight $w$, the normalized finite perturbation sensitivity indicator is

$$S_w={\displaystyle \frac{\frac{\Delta J}{J}}{\frac{\Delta w}{w}}}$$

(59)

The QUBO coefficients are engineering normalization and tuning parameters rather than a unique optimum. A systematic sensitivity protocol should perturb each normalized weight while varying nonlinear load level, harmonic content, reactive loading, grid short-circuit strength, X/R ratio, DC-link deviation, parameter uncertainty, and thermal headroom. The complete multidimensional sweep has not yet been executed; consequently, this protocol is identified as required validation rather than reported numerical evidence.

Communication robustness should be quantified by normalized delay, packet loss rate, synchronization error, and current-sharing error. With $T_S = 50\mathrm{m}\mathrm{s}$, delays of 5, 10, and 25 ms correspond to 0.10, 0.20, and 0.50 supervisory periods, respectively. For communication delay ${\tau }_c$, the normalized delay is

$$D_{norm}={\displaystyle \frac{{\tau }_c}{T_S}}$$

(60)

$$E_{share,RMS}=\sqrt{{\displaystyle \frac{1}{N}} {\displaystyle {\sum }_{k=1}^N}{(i_{F,k}-{\lambda }_k i_{F,\Sigma })}^2}$$

(61)

In (61), the current-sharing error quantifies the RMS mismatch over the observation interval between the measured filter current of each converter and its supervisory allocation of the aggregate filter current demand. Communication robustness should additionally be evaluated under fixed delays, random jitter, isolated packet drops, burst losses, and temporary supervisory disconnection. A practical implementation retains the last feasible command after an invalid or missing packet and transitions to deterministic LOCAL SAFE MODE after a stale data threshold, while local current limiting, DC-link protection, modulation limiting, thermal protection, and SOA enforcement remain active. Numerical packet loss or delay tolerance limits are not claimed until these tests are executed. For larger arrays, hierarchical clustering is recommended so that fast converter states remain local and only aggregate capability, thermal headroom, availability, and requested participation are communicated to the upper supervisor.

5. Conclusions

The provided 15 kHz dashboard (Figure 4) provides strong numerical evidence that the SAPF QAOA Multi-Agent meets its principal control objectives. The nonlinear load THD of 24.615% is reduced to a source THD of 0.142%, the source PF reaches 0.99999, the reactive power falls to 0.31 var, the current tracking error is only 0.025 A, and the DC-link ripple is limited to 0.059%. Three-phase unbalance is 0.026%, the maximum modulation index is 0.763 pu, and the peak filter current remains far below the 44 A limit. The final SOA PASS, therefore, reflects both high power quality performance and substantial converter operating margin. The figure supports the use of the 15 kHz configuration as a high-performance implementation point for the proposed QAOA-supervised hierarchical SAPF controller.

The harmonic objective is fulfilled with very large margin, demonstrating that the fast current loop and compensation-reference generator are properly coordinated. The power factor and reactive power objectives are also fulfilled, showing that the controller accurately separates active and non-active current components. The DC-link objective is fulfilled without degrading source current quality, confirming appropriate bandwidth separation between the energy and current loops.

The tracking and SOA objectives are simultaneously fulfilled. This is particularly important because extremely low THD can sometimes be obtained numerically by imposing unrealistically large compensation currents or converter voltages. Here, the current and modulation margins indicate that the reported operating point remains inside the modeled converter capability.

The four-SAPF solution is selected because it converts a conventional shunt compensation problem into a modular multi-agent power electronic platform. It distributes current and losses, permits thermal-aware and SOA-aware participation, supports interleaved switching, offers redundancy, preserves modulation and current reserve, and creates the degrees of freedom required for QAOA-based supervisory allocation. The defensible contribution of the four-unit topology is its modularity, scalable rating, distributed thermal loading, redundancy, interleaving capability, and optimization-enabled redistribution of compensation effort.

For the investigated system, these properties are especially relevant because harmonic mitigation and reactive power compensation must be achieved simultaneously while four DC-link voltages, current tracking performance, converter temperature, modulation headroom, and safe operating limits remain controlled. The reported reduction from 24.615% load current THD to 0.142% source current THD, together with PF = 0.99999 and residual Q = 0.31 var, demonstrates the effectiveness of the aggregate compensation objective.

For the investigated numerical operating conditions, the overall objective of a high-performance adaptive hierarchical SAPF controller is achieved. The five-case ablation nevertheless shows that the very low steady-state THD is mainly produced by the deterministic compensation and current control layer. The quantum-assisted supervisor contributes to discrete profile coordination, bounded supervisory refinement, allocation and feasibility management, and transient multi-objective trade-off shaping. The present four-bit problem does not demonstrate computational quantum advantage, and physical NISQ timing, HIL/experimental validation, systematic QUBO weight robustness, and communication delay/packet loss testing remain necessary before hardware-level industrial scalability can be claimed.

The first contribution is the hierarchical separation of supervisory optimization from deterministic fast control. QAOA is used to select among prevalidated control profiles, while the inner current and DC-link loops retain explicit deterministic dynamics. This avoids the unrealistic assumption that a quantum optimizer must directly generate PWM switching states at the converter switching frequency.

The second contribution is the multi-objective profile concept. Instead of tuning a single fixed controller for one operating point, the architecture provides profiles for nominal hyper-performance, soft coupling, DC-link recovery, harmonic rejection, reactive power priority, unbalance mitigation, transient damping, and SOA derating. The QAOA layer can, therefore, change control priorities according to the physical operating condition.

The third contribution is the simultaneous achievement of power quality and energy regulation objectives. The reported result combines 0.142% source THD, 0.99999 PF, 0.31 var reactive power, 0.026 A tracking error, and 0.059% DC-link ripple. Achieving these quantities simultaneously is more significant than optimizing any one of them independently.

The fourth contribution is operation with substantial converter reserve. The filter current peak is only 7.664 A against a 44 A profile limit, and the maximum modulation index is 0.763 pu. The high-power quality performance is, therefore, achieved without exhausting the modeled current or voltage capability of the VSI.

The fifth contribution is the explicit integration of SOA constraints into supervisory interpretation. Current and modulation margins are not treated as secondary diagnostics but as constraints that can alter the selected profile. This makes the architecture more suitable for subsequent industrial and hardware-in-the-loop validation.

The central contribution is not any single metric but the simultaneous fulfillment of harmonic, reactive power, energy regulation, tracking, balancing, and hardware margin objectives within hierarchical multi-agent architecture. Profile 16 is the final and nominally dominant profile observed in the complete time-domain simulation; it is not presented as the unique optimum of every frozen QUBO snapshot. The broader profile library provides a reproducible mechanism for adaptive supervisory operation during startup, disturbances, and protection-related conditions.

On the basis of the reported simulation, all principal electrical control objectives are achieved. The architecture, therefore, provides a strong foundation for the next development stage: switched device simulation, robustness analysis, real-time implementation, and SIL/PIL/HIL or experimental validation.