An 8-Bit Four-Channel Time-Interleaved SAR-Flash Hybrid ADC with Time-Domain Interpolation

Abstract

An 8-bit 3.2 GS/s four-channel time-interleaved (TI) successive-approximation-register (SAR)-flash analog-to-digital converter (ADC) employing complementary dynamic amplifier (CDA)-based two-step sub-ADCs is presented for high-speed wired and wireless communication systems. Each sub-ADC uses four CDAs to perform a 4-bit asynchronous loop-unrolled (LU) SAR conversion followed by a 4.5-bit reference-embedded interpolating flash (I-Flash) conversion, achieving 8-bit resolution with reduced comparator count and input capacitance. A four-channel TI architecture with a multi-phase clock generator and an on-chip voltage-controlled delay line (VCDL) enables 3.2 GS/s operation while performing foreground offset calibration under full TI loading to accurately track inter-channel reference variations. Fabricated in a 28 nm CMOS process, the prototype ADC shows differential non-linearity (DNL) and integral non-linearity (INL) ranges of −0.78 to +0.74 LSB and −0.84 to +1.03 LSB, respectively, and achieves a signal-to-noise and distortion ratio (SNDR) and a spurious-free dynamic range (SFDR) of 41.74 dB and 58.03 dB at 3.2 GS/s with a Nyquist-rate input. Operating from a 1 V supply, the ADC core consumes 8.63 mW at 3.2 GS/s, corresponding to a Walden figure-of-merit (FoM) of approximately 27 fJ/conversion step.

1. Introduction

In high-speed wired and wireless communication systems, as well as in applications requiring large-volume data transfer, analog-to-digital converters (ADCs) capable of multi-GS/s sampling rates and medium-to-high resolution have become indispensable. The widespread adoption of multi-level modulation schemes such as PAM-4 and PAM-8 further increases the demand for high-speed and high-accuracy data conversion at both the transmitter and receiver, continuously driving the need for high-speed ADCs [1,2,3,4,5,6]. To meet these requirements, time-interleaved (TI) architectures, in which multiple sub-ADCs operate in parallel to scale the overall sampling rate in proportion to the number of channels, have been widely adopted, making TI ADCs a key solution for high-speed systems [7,8,9,10,11,12,13,14]. However, adopting the TI architecture does not simply increase the conversion speed.

Channel mismatches including offset, gain, timing skew, and bandwidth variation are inevitable in TI systems [15,16,17], and the circuits and digital algorithms required to suppress these errors significantly increase power consumption and architectural complexity. In particular, in high-speed and high-resolution TI ADCs, calibration-related circuits often occupy a substantial portion of the total power budget [18,19,20,21], posing a critical limitation to power efficiency and system-level integration. Therefore, designing an efficient high-speed TI ADC requires not only increasing the interleaving factor but also employing power-efficient sub-ADCs and choosing an appropriate number of channels to alleviate calibration and clock-distribution burdens. From this perspective, this work adopts a previously reported complementary dynamic amplifier (CDA)-based low-power sub-ADC architecture [22] to achieve improved power and area efficiency in TI operation. With a dual-edge operating scheme, a CDA-based sub-ADC can realize 8-bit resolution using only four CDAs, offering significant energy and area advantages over conventional medium-resolution high-speed ADCs. By employing this CDA-based low-power sub-ADC as the fundamental building block of the TI architecture, the proposed design achieves the target sampling rate without relying on excessively high interleaving factors while simultaneously reducing the calibration and clock-distribution burdens. This work implements a four-channel TI ADC using a CDA-based two-step sub-ADC, achieving an overall sampling rate of 3.2 GS/s. Each sub-ADC operates at a relatively low clock frequency, ensuring sufficient timing margin, while the TI architecture collectively provides the required high-speed sampling. Furthermore, clock generation optimized for channel-to-channel matching, together with offset calibration performed under realistic TI operating conditions, validates the suitability of the proposed architecture for high-speed and low-power TI ADCs. Accordingly, the main contribution of this work lies in the practical extension of a previously demonstrated single-channel CDA-based ADC to a four-channel TI implementation, rather than in proposing a fundamentally new ADC architecture. The work addresses the additional design challenges that arise from multi-channel implementation and provides the associated circuit-level design considerations and verification results. The remainder of this paper is organized as follows. Section 2 describes the overall TI ADC architecture and the CDA-based sub-ADC. Section 3 presents the circuit implementation in the TI environment, and Section 4 discusses the measurement results, followed by conclusions.

2. Proposed TI ADC Architecture

2.1. Overall Architecture of the Four-Channel TI ADC

In the proposed ADC, each sub-ADC employs a CDA-based two-step architecture and operates reliably under low-power conditions. Four identical sub-ADCs are driven in a time-interleaved manner using evenly spaced sampling clock phases, resulting in an overall sampling rate of 3.2 GS/s. Since each sub-ADC operates at a relatively low internal clock frequency, the proposed architecture effectively mitigates comparator delay, capacitive digital-to-analog converter (CDAC) settling requirements, and high-frequency clocking demands that would arise if a single ADC were directly operated at multi-GS/s rates. The TI configuration thus preserves the simplicity and power efficiency of the sub-ADCs while multiplying the overall conversion rate, and a block diagram of the proposed system is shown in Figure 1. An external differential clock is first converted into an internal pulse signal by a low-voltage differential signaling (LVDS) receiver, and then four sampling clock phases are generated by a multi-phase clock generator, followed by a voltage-controlled delay line (VCDL)-based architecture that provides fine time-skew correction between channels with high resolution under the same area constraint. Using these generated sampling clocks (Φ_1:4), each sub-ADC independently performs coarse-fine conversion. The conversion results from the four channels are then multiplexed sequentially, forming a continuous output data stream. The proposed TI scheme achieves a high overall sampling rate while minimizing the clock frequency and circuit burden of each sub-ADC. In particular, it alleviates CDAC switching stress, comparator delay, and clock-distribution burden, enabling robust high-speed operation.

2.2. Sub-ADC Overview

Figure 2 shows the block diagram of the proposed TI sub-ADC. It is composed of four CDAs and performs an 8-bit conversion. The MSB is resolved sequentially using a loop-unrolled (LU) successive approximation register (SAR) operation, while the lower bits are obtained through a fast-interpolating flash (I-Flash) conversion. Each CDA incorporates both PMOS and NMOS input pairs and operates as a dual-edge amplifier by selecting the charging and discharging paths at the rising and falling clock edges, respectively. This enables the realization of 8-bit resolution (4-bit LU-SAR + 4.5-bit I-Flash) using only four CDAs. During the sampling phase, the input signal is stored on the top plate of the CDAC through dedicated bootstrapped switches (BTS), while the CDAC control nodes are held at their initial reference levels. Figure 3a illustrates the schematic of the CDA with the foreground offset-calibration circuitry based on the offset-calibration approach in [23], while Figure 3b shows the timing diagram of the asynchronous clocks and the waveform at the CDA output node V_DP/M. In this offset-calibration scheme, the effective offset of the coarse ADC is adjusted by tuning auxiliary PMOS current sources, whereas the offset of the fine ADC is compensated by using NMOS-based auxiliary current sources and tail-current control. After sampling, when the Φ_C<4> clock transitions low, the P-side of CDA<4> is activated to initiate the comparison. The MSB is then determined and latched by the SR-latch (SRL) according to the discharge-rate difference between the CDA output nodes. All CDA clocks, including CLKC and CLKF, are generated by the asynchronous logic. After the MSB capacitor of the CDAC is switched, the P-side of the next CDA is sequentially activated in accordance with the CDAC settling time. In this manner, the upper four bits are resolved in a conventional LU-SAR sequence, starting from CDA<4> and ending with CDA<1>. To prevent shoot-through current in the PIs during the LU-SAR operation, shoot-through-prevention (STP) blocks are inserted between the CDAs and PIs. The STP blocks disable signal transfer to the PIs during the LU-SAR operation and enable the signal path only during the I-Flash operation.

Once the LU-SAR conversion is completed, the CDA outputs are reset to the reference level through a complementary path using the NMOS input pairs, and the same four CDAs used in the coarse stage are reused for the I-Flash conversion. In the I-Flash conversion, the N-sides of the four CDAs are activated simultaneously, generating 25 zero-crossings through a reference-embedded 8× interpolation architecture. The time-domain interpolator (TDI) array receives the timing information generated by adjacent CDA outputs and produces additional intermediate timing points between them, thereby realizing the 8× interpolation without requiring additional CDAs. The interpolated timing signals are then applied to the SRL array, where the relative arrival order of the interpolated signals is sensed and latched. Accordingly, each SRL provides a digital decision corresponding to an interpolated zero-crossing point, and the resulting 25 decisions form T<25:1>, which is subsequently processed by the digital encoder to determine the lower-bit output. This provides sufficient resolution for determining the lower 4.5 bits and reduces the total number of required conversions for an 8-bit decision from eight conversions to approximately five. By combining the LU-SAR and reference-embedded I-Flash operations, the sub-ADC achieves full 8-bit conversion with a compact area and low power consumption.

3. Circuit Implementation

3.1. Multi-Phase Clock Generation

Figure 4 illustrates the block diagram of the proposed multi-phase clock generator and its associated timing diagram. Non-overlapping sampling clocks are required to prevent simultaneous sampling between adjacent TI channels and to ensure stable channel-to-channel sampling operation in the presence of clock skew and delay variations. Without any additional logic, generating non-overlapping clocks using only a single ring counter requires an input clock running at twice the target sampling frequency, which significantly increases the design burden. To avoid this, the architecture shown in Figure 4a is adopted to generate multi-phase clocks from an input clock operating at the desired sampling frequency. The proposed multi-phase clock generator consists of two ring counters, each composed of three set-mode D Flip Flops (DFFs) and one reset-mode DFF, and four AND gates. Φ_LVDS and Φ_LVDSB drive each ring counter, and four-phase clocks with a 25% duty cycle are generated on the rising edge of Φ_LVDS. Similarly, another set of four 25% duty clocks is generated on the falling edge of Φ_LVDS. Thus, after generating a total of eight 25% duty clocks, the clocks derived from the rising and falling edges are combined through AND gates to finally produce four non-overlapping clocks. This operation is illustrated in the timing diagram shown in Figure 4b. The timing stability of the generated sampling clocks was also verified through transient-noise simulations. With a noise bandwidth of up to 100 GHz, the RMS jitter of the four sampling clocks, evaluated over 1000 samples, ranges from approximately 92.9 fs to 97.5 fs. At an input frequency of 1.599 GHz, these values correspond to a jitter-limited SNR of approximately 60.2–60.6 dB, or an equivalent resolution of approximately 9.7 bits. Since this resolution is higher than the nominal 8-bit resolution of the proposed ADC, the contribution of sampling-clock jitter to the measured ADC performance is negligible.

Although the random jitter of the generated clocks is sufficiently small, the four sampling clocks (Φ_L<1:4>) for the proposed four-channel TI SAR ADC inherently exhibit phase deviations caused by device variation and routing asymmetry. These phase differences translate directly into sampling-time skew among the channels, which becomes increasingly critical at multi-GS/s operation.

To mitigate this issue, the proposed design employs an on-chip VCDL-based phase-alignment scheme to finely adjust the sampling phase of each channel. Figure 5 illustrates the overall digital timing-skew detection and correction procedure. During post-silicon characterization, a single-tone sinusoidal signal is applied to the ADC, and the digitized output sequences of the interleaved channels are processed to estimate the timing-skew error using the method described in [24]. To further verify the effectiveness of the timing-skew calibration engine applied in this work, Figure 6 presents MATLAB R2025b-based behavioral simulation results using a timing-skew distribution derived from circuit-level Monte Carlo simulations. The Monte Carlo simulation of the sampling-clock paths was performed with 100 samples, resulting in a 1σ timing-skew variation of approximately 3.75 ps. Based on this result, channel timing errors following the same statistical distribution were applied to the MATLAB model to evaluate the calibration performance. Figure 6a shows the timing-skew calibration results for channels 2–4, with channel 1 used as the reference channel. The x-axis represents the signed individual timing skew applied to channels 2–4, while the y-axis represents the corresponding timing skew relative to channel 1. Before calibration, the relative timing errors are distributed over approximately −14 to +14 ps. After calibration, the timing-skew errors converge to within approximately ±350 fs around channel 1. Figure 6b shows the SNDR before and after calibration for each of the 100 Monte Carlo samples. Although the SNDR before calibration varies considerably depending on the randomly generated channel timing skews, the calibrated results consistently maintain an SNDR higher than 48 dB. These results confirm that the timing-skew calibration engine applied to the ADC effectively reduces inter-channel timing mismatch and restores ADC performance under the timing-skew variations obtained from the circuit-level Monte Carlo simulations. In the current implementation, the polarity of the timing-skew error is continuously detected in real time in a background manner during normal ADC operation. The estimated timing-error polarity or error metric is then used to determine the update direction of the VCDL control code for each channel. This procedure is repeated until the sampling-time mismatch among the channels is sufficiently reduced.

Figure 7 shows the detailed VCDL circuit and its corresponding timing diagram. Each VCDL receives one of the four uncorrected sampling clocks, Φ_L<1:4>, and generates the corresponding phase-adjusted clock, Φ_S<1:4>. When a channel is detected to sample earlier or later than the desired phase, its VCDL control code is updated to increase or decrease the delay in the compensating direction. Consequently, the sampling edges of Φ_S<1:4> are more closely aligned, thereby reducing the sampling-phase mismatch among the four TI channels.

3.2. Offset Calibration and Gain Matching in TI

Figure 8 summarizes the foreground offset-calibration sequence, and Figure 9 illustrates the block-level implementation and control flow of the foreground calibration scheme. When the foreground calibration is initiated by asserting CAL ON, the input is sampled at ${\mathrm{V}}_{\mathrm{I}\mathrm{N},\mathrm{D}\mathrm{I}\mathrm{F}\mathrm{F}}=0$, and the required offset voltages are sequentially generated by the CDAC in the calibration mode. First, the offset of the coarse ADC is calibrated by tuning the additional PMOS current sources to adjust the effective offset. Once the coarse offset calibration is completed, the coarse calibration completion flag signal is asserted, which triggers the fine ADC offset calibration. The fine ADC is then calibrated in a similar manner, using the offset voltages generated by the CDAC while adjusting NMOS-based auxiliary current sources and the tail current to compensate for its offset. After the fine calibration of each channel is completed, the channel-level calibration-done signals are merged to generate the final CAL DONE signal. As shown in Figure 8, the entire foreground calibration process is completed before normal ADC conversion starts.

In this way, the internal offset-calibration scheme of each sub-ADC can, in principle, be applied in the same manner as in a single-channel architecture. However, in a TI environment, multiple channels operate simultaneously, and accurate offset values are difficult to obtain unless the calibration is carried out under the same conditions as during normal operation. In particular, when the ADC is extended to a TI architecture, the overall circuit loading increases, and the CDAC reference-voltage distribution changes. Consequently, calibration performed with only a single active channel may not accurately reflect the actual TI operating conditions, resulting in offset errors. In other words, even slight differences in the CDAC reference levels experienced by individual channels may cause the offset values obtained through conventional calibration to deviate from those under actual TI operation. To address this issue, the foreground offset calibration is performed with all channels activated, while preserving the same operation sequence as in full TI operation. As shown in Figure 9, each channel performs coarse and fine offset calibration using the CDAC-generated calibration references, and the calibration-done signals from all channels are combined to determine the completion of the overall foreground calibration. That is, by calibrating the offset of each channel under the same loading conditions, reference-voltage variations, and switching activity as in TI operation, calibration errors caused by channel-to-channel reference deviations and operating-condition differences introduced by TI expansion can be reduced. Through this approach, more accurate offset values can be obtained under conditions that closely match the actual operating environment.

In addition, the calibration range was designed to sufficiently cover the offset variation caused by process, supply-voltage, and temperature variations. Figure 10 shows the simulated offset variation of CDA<4> under different PVT conditions. The calibration range was determined based on the worst-case PVT condition of SS, 0.95 V, and 0 °C and was designed to provide sufficient margin to cover the ±3σ offset variation under this condition. Therefore, the expected PVT-induced offset variation remains within the available calibration range.

Inter-channel gain mismatch was also considered in the four-channel TI implementation. Variations in the reference voltage supplied to each sub-ADC can result in gain differences among the channels. Therefore, the resistance of each reference-voltage path was designed such that the resulting channel-to-channel reference-voltage difference remains below 0.1 LSB based on the ADC input range. For the 8-bit ADC with a 0.8 V differential input range, 0.1 LSB corresponds to 0.3125 mV, or approximately 0.031% of the 1 V CDAC reference.

3.3. CDA Gain–Conversion Speed Trade-Off

In the adopted 8× time-domain interpolation architecture, the offset of each CDA and the 2× interpolated zero-crossing generated between adjacent CDAs are directly calibrated. The zero-crossing points generated by the subsequent 4× and 8× interpolation stages are not directly calibrated; instead, the effect of offsets introduced in these back-end interpolation stages is mitigated by providing sufficient time-domain gain in the front-end CDA. Therefore, sufficient CDA time-domain gain is important for maintaining the accuracy of the overall 8× time-domain interpolation. In this work, the differential input range is reduced from 1.2 V in [22] to 0.8 V, decreasing the LSB size from approximately 4.69 mV to 3.125 mV. Accordingly, sufficient CDA time-domain gain is required to convert the smaller input-voltage difference into an adequate timing difference for the subsequent interpolation stages. As reported in [23], the output slopes of a DA are expressed as

$${\mathrm{S}\mathrm{l}\mathrm{o}\mathrm{p}\mathrm{e}}_{{\mathrm{S}}_{\mathrm{k}}^{+}}={\displaystyle \frac{{\mathrm{I}}_{\mathrm{k}}^{+}}{{\mathrm{C}}_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}}}={\displaystyle \frac{{\mathrm{V}}_{\mathrm{D}\mathrm{T}}}{{\mathrm{t}}_2}},{\mathrm{S}\mathrm{l}\mathrm{o}\mathrm{p}\mathrm{e}}_{{\mathrm{S}}_{\mathrm{k}}^{-}}={\displaystyle \frac{{\mathrm{I}}_{\mathrm{k}}^{-}}{{\mathrm{C}}_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}}}={\displaystyle \frac{{\mathrm{V}}_{\mathrm{D}\mathrm{T}}}{{\mathrm{t}}_1}}$$

(1)

Based on the output–slope relationship, the voltage-to-time gain of the DA is defined as

$${\mathrm{G}}_{\mathrm{D}\mathrm{A},\mathrm{t}\mathrm{i}\mathrm{m}\mathrm{e}}={\displaystyle \frac{∆\mathrm{t}}{{\mathrm{V}}_{\mathrm{i}\mathrm{n},\mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}}}}={\displaystyle \frac{4{\mathrm{C}}_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}{\mathrm{V}}_{\mathrm{D}\mathrm{T}}{\mathrm{g}}_{\mathrm{m}}}{{\mathrm{I}}_{\mathrm{t}\mathrm{a}\mathrm{i}\mathrm{l}}^2}}$$

(2)

Here, ${\mathbf{I}}_{\mathbf{k}}^{+}$ and ${\mathbf{I}}_{\mathbf{k}}^{-}$ are the discharge currents of the DA output nodes determined by the input voltage, ${\mathbf{C}}_{\mathbf{l}\mathbf{o}\mathbf{a}\mathbf{d}}$ is the load capacitance at the DA output nodes, and ${\mathbf{V}}_{\mathbf{D}\mathbf{T}}$ is the voltage difference between VDD and the inverter logic threshold. ${\mathbf{t}}_{\mathbf{1}}$ and ${\mathbf{t}}_{\mathbf{2}}$ are the corresponding discharge times from VDD to the inverter logic threshold, ${\mathbf{g}}_{\mathbf{m}}$ is the transconductance of the input transistors, and ${\mathbf{I}}_{\mathbf{t}\mathbf{a}\mathbf{i}\mathbf{l}}$ is the total tail current of the DA. These definitions and the voltage-to-time gain expression follow [23]. Although these relationships were originally derived for the DA, the active amplification phase of the CDA employed in this work is also based on a dynamic differential-pair charging or discharging operation. Therefore, the relationships in (1) and (2) are used as design guidelines for analyzing the CDA time-domain gain. Since the output transition time and the time-domain gain depend on common circuit parameters, the gain–latching-time characteristic of the CDA was evaluated through post-layout simulations. As shown in Figure 11, the latching time increases with the CDA time-domain gain. In this work, the CDA was designed to provide a time-domain gain of approximately 464 fs/mV, with a corresponding latching time of approximately 69 ps.

4. Measurement Results

The proposed 3.2 GS/s 8-bit four-channel TI SAR-Flash ADC was fabricated in a 28 nm CMOS process. Figure 12 shows the die photograph and enlarged layout views of the ADC core and a single sub-ADC. Each sub-ADC occupies 80 μm × 25 μm and consists of a CDAC with switch logic, asynchronous logic, four CDAs and SRLs, a TDI array, and encoder blocks. The four-channel ADC core, including power routing, occupies 232 μm × 97 μm, corresponding to an area of approximately $0.023 {\mathrm{mm}}^2$.

The measurement environment for the 3.2 GS/s TI ADC is illustrated in Figure 13. The clock and analog input signals are generated by Keysight Technologies E8257D-540 (Keysight Technologies, Santa Rosa, CA, USA) and RIGOL DSG5204 (RIGOL Technologies, Suzhou, China) signal generators, respectively. These signals are converted to differential inputs via Marki BAL0026 (Marki Microwave LLC, Morgan Hill, CA, USA) baluns and fed into the chip through Mini-Circuits ZX85-12G bias-tees (Mini-Circuits, Brooklyn, NY, USA). Phase-matched cables are used to maintain 100 $\mathsf{\Omega }$ differential impedance matching. Additionally, a Keysight Technologies N9010B (Keysight Technologies, Santa Rosa, CA, USA) signal analyzer is utilized to monitor the input signal spectrum. On the output side, the decimated digital outputs are captured by an NI PXIe-6547 digital waveform analyzer (National Instruments Corporation, Austin, TX, USA), enabling real-time performance evaluation and detection of inter-channel mismatches, including offset and timing skew.

The measured differential non-linearity (DNL) and integral non-linearity (INL) at 3.2 GS/s are shown in Figure 14. After offset calibration, the measured DNL and INL range from −0.78 to +0.74 LSB and from −0.84 to +1.03 LSB, respectively. Since the measured DNL remains within ±1 LSB, the ADC achieves no missing codes after calibration. The measured INL also remains close to 1 LSB, confirming that the proposed ADC maintains sufficient static linearity at the target sampling rate.

Figure 15 shows the fast Fourier transform (FFT) spectra with and without offset calibration for a 1.8245 MHz input at a 3.2 GS/s conversion rate. With calibration, the spurious-free dynamic range (SFDR) improves from 40.34 dB to 58.49 dB, and the signal-to-noise and distortion ratio (SNDR) improves from 30.78 dB to 44.28 dB.

Figure 16 shows the FFT spectra for a Nyquist-rate input before and after timing-skew calibration. Before calibration, the SFDR and SNDR are 35.84 dB and 34.02 dB, respectively. The timing-skew error is estimated to be approximately 1.61 ps based on the worst-case spur [25]. After calibration, these spurs are significantly suppressed, and the SFDR and SNDR improve to 58.03 dB and 41.74 dB, respectively. These results demonstrate that the proposed timing-skew calibration effectively reduces channel-to-channel sampling-time mismatch and enables the ADC to maintain stable conversion performance even for high-frequency input signals close to the Nyquist frequency.

Figure 17 shows the performance as a function of input frequency at a 3.2 GS/s conversion rate. As the input frequency increases from 1.8245 MHz to the Nyquist frequency, the SNDR remains above 41 dB. It is noted that the relatively higher SNDR observed at the lowest input frequency and at the Nyquist frequency is mainly due to differences in the measurement equipment and external filters, which reduce the second-harmonic component and thereby improve the measured performance.

Figure 18 shows the performance for a 1.8245 MHz input as the sampling rate is varied from 2.2 to 3.2 GS/s. In this case, the SNDR remains above 44 dB over the entire sampling-rate range. The ADC core operates from a 1 V supply.

Figure 19 shows the measured input-frequency response of the four-channel TI ADC. The hold capacitance is 64 fF, as determined from the KT/C noise requirement, and approximately 23 fF of additional parasitic capacitance is associated with the input routing to the four TI channels. The measured input response also reflects the effects of the I/O pad capacitance and impedance-matching resistance. The measured −3 dB input bandwidth is approximately 3.4 GHz, which is sufficiently higher than the 1.6-GHz Nyquist frequency at the target sampling rate of 3.2 GS/s.

At 3.2 GS/s, the total power consumption is 8.63 mW, and the power breakdown is shown in Figure 20. The ADC array occupies the largest portion, consuming 6.73 mW, which corresponds to 78% of the total power. Within the ADC array, the CDAs consume 1.81 mW, followed by the TDIs and SR latches with 1.64 mW, the asynchronous logic and encoder with 1.04 mW each, and the remaining circuits with 1.20 mW. The VCDL, clock generator, and MUX consume 0.43 mW, 0.69 mW, and 0.78 mW, respectively.

Table 1. Performance comparison.

	This Work	Ref. [26]	Ref. [27]	Ref. [28]	Ref. [29]	Ref. [30]	Ref. [31]	Ref [32]
Technology (nm)	28	55	65	28	28	28	28	28
Architecture	TI SAR-Flash	TI ADC	TI ADC	TI ADC	TI ADC	TI SAR	TI SAR	TI ADC
# of channels	4	8	8	5	4	4	4	2
Supply (V)	1	1.2	1.2	0.9	1	1.2/0.9	1	1
Resolution (bit)	8	8	8	7	6	7	8	7
FS (GS/s)	3.2	2.6	2.6	2.5	3.6	2	1.6	3.8
DNL/INLMAX (LSB)	0.78/1.03	0.93/0.91	0.75/1.07	0.45/0.35	0.67/0.66	0.98/1.5	1.34/1.53	0.55/0.73
SNDR@Nyq. (dB)	41.74	31.8	41.29	40	33.9	36.4	42.6	39.9
SFDR@Nyq. (dB)	58.03	40.3	50.01	52.3	49.8	47.8	52.9	50.8
ENOB@Nyq. (bit)	6.64	5	6.57	6.3	5.3	5.75	6.78	6.34
Power (mW)	8.63	60	28.88	7.6	6.1	7.62	3.22	7.5
Active area (mm2)	0.023 2	0.220	0.400	0.030	0.019	0.008	0.019	0.008 2
Walden FOM 1 (fJ/conv.-step)	27	726	117.2	37.2	41.8	70.8	18.3	24.4

¹ Walden FoM = Power/(2^ENOB $\times$ Sampling frequency), ² w/o calibration.

compares the proposed ADC with recently reported TI ADCs having 6- to 8-bit resolution and sampling rates ranging from 2 to 3.6 GS/s. These criteria were selected to compare ADCs operating in a similar resolution and sampling-rate range. The proposed ADC achieves 3.2 GS/s operation with an 8-bit resolution using a four-channel TI architecture. Although the number of interleaved channels is relatively small, the proposed ADC maintains high Nyquist performance, achieving an SNDR of 41.74 dB, an SFDR of 58.03 dB, and an effective number of bits (ENOB) of 6.64 bits. Furthermore, the measured Walden figure-of-merit (FoM) is 27 fJ/conv.-step, which is the lowest value among the compared ADCs. This shows that the proposed architecture provides an efficient resolution–speed–power trade-off while maintaining a compact active area.

5. Conclusions

This paper has presented a 28 nm CMOS 8-bit 3.2 GS/s four-channel TI SAR-Flash hybrid ADC employing CDA-based two-step sub-ADCs with LU-SAR and reference-embedded I-Flash operation. By reusing only four CDAs over a 4-bit LU-SAR and 4.5-bit I-Flash conversion and operating them on both clock edges, the sub-ADC achieves full 8-bit resolution with reduced comparator count and input capacitance, improving energy and area efficiency. A four-channel TI architecture with a multi-phase clock generator and VCDL-based phase alignment enables 3.2 GS/s operation while relaxing the per-channel clock frequency and supporting foreground offset calibration under realistic TI loading conditions. The prototype ADC achieves DNL/INL within −0.78/+0.74 LSB and −0.84/+1.03 LSB and delivers SNDR/SFDR of approximately 44.28/58.49 dB at a low-frequency input and 41.74/58.03 dB at a Nyquist-rate input, corresponding to ENOB of about 7.1 and 6.6 bits. Operating from a 1 V supply, the ADC core consumes 8.63 mW at 3.2 GS/s, resulting in a Walden FoM of about 27 fJ/conversion step. These results demonstrate that the proposed CDA-based SAR-Flash hybrid ADC provides a compact and power-efficient solution for multi-GS/s medium-resolution data conversion in high-speed communication systems.