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Volume 15
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10.3390/electronics15184232
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Article

An 8-Bit Four-Channel Time-Interleaved SAR-Flash Hybrid ADC with Time-Domain Interpolation

by
Sang-Won Oh
1,
Da-Yeon Kim
1,
Hyeon-Gi Hwang
1,
Ye-Won Yoon
1,
Woo-Suk Shin
1,
Ji-Min Kim
1,
Yoon-Seo Jang
1,
Dong-Jin Chang
2,* and
Dong-Ryeol Oh
1,*
1
Department of Electronic Engineering, Faculty of Applied Energy System, Jeju National University, Jeju 63543, Republic of Korea
2
Department of Electronics Engineering, Chungnam National University, Daejeon 34134, Republic of Korea
*
Authors to whom correspondence should be addressed.
Electronics 2026, 15(18), 4232; https://doi.org/10.3390/electronics15184232
Submission received: 3 August 2026 / Revised: 5 September 2026 / Accepted: 16 September 2026 / Published: 17 September 2026
(This article belongs to the Section Circuit and Signal Processing)
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Abstract

An 8-bit 3.2 GS/s four-channel time-interleaved (TI) successive-approximation-register (SAR)-flash analog-to-digital converter (ADC) employing complementary dynamic amplifier (CDA)-based two-step sub-ADCs is presented for high-speed wired and wireless communication systems. Each sub-ADC uses four CDAs to perform a 4-bit asynchronous loop-unrolled (LU) SAR conversion followed by a 4.5-bit reference-embedded interpolating flash (I-Flash) conversion, achieving 8-bit resolution with reduced comparator count and input capacitance. A four-channel TI architecture with a multi-phase clock generator and an on-chip voltage-controlled delay line (VCDL) enables 3.2 GS/s operation while performing foreground offset calibration under full TI loading to accurately track inter-channel reference variations. Fabricated in a 28 nm CMOS process, the prototype ADC shows differential non-linearity (DNL) and integral non-linearity (INL) ranges of −0.78 to +0.74 LSB and −0.84 to +1.03 LSB, respectively, and achieves a signal-to-noise and distortion ratio (SNDR) and a spurious-free dynamic range (SFDR) of 41.74 dB and 58.03 dB at 3.2 GS/s with a Nyquist-rate input. Operating from a 1 V supply, the ADC core consumes 8.63 mW at 3.2 GS/s, corresponding to a Walden figure-of-merit (FoM) of approximately 27 fJ/conversion step.
Keywords: analog-to-digital converter (ADC); time-interleaving (TI); successive approximation register (SAR); time-domain; interpolation; flash; reference embedding; clock generation analog-to-digital converter (ADC); time-interleaving (TI); successive approximation register (SAR); time-domain; interpolation; flash; reference embedding; clock generation

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MDPI and ACS Style

Oh, S.-W.; Kim, D.-Y.; Hwang, H.-G.; Yoon, Y.-W.; Shin, W.-S.; Kim, J.-M.; Jang, Y.-S.; Chang, D.-J.; Oh, D.-R. An 8-Bit Four-Channel Time-Interleaved SAR-Flash Hybrid ADC with Time-Domain Interpolation. Electronics 2026, 15, 4232. https://doi.org/10.3390/electronics15184232

AMA Style

Oh S-W, Kim D-Y, Hwang H-G, Yoon Y-W, Shin W-S, Kim J-M, Jang Y-S, Chang D-J, Oh D-R. An 8-Bit Four-Channel Time-Interleaved SAR-Flash Hybrid ADC with Time-Domain Interpolation. Electronics. 2026; 15(18):4232. https://doi.org/10.3390/electronics15184232

Chicago/Turabian Style

Oh, Sang-Won, Da-Yeon Kim, Hyeon-Gi Hwang, Ye-Won Yoon, Woo-Suk Shin, Ji-Min Kim, Yoon-Seo Jang, Dong-Jin Chang, and Dong-Ryeol Oh. 2026. "An 8-Bit Four-Channel Time-Interleaved SAR-Flash Hybrid ADC with Time-Domain Interpolation" Electronics 15, no. 18: 4232. https://doi.org/10.3390/electronics15184232

APA Style

Oh, S.-W., Kim, D.-Y., Hwang, H.-G., Yoon, Y.-W., Shin, W.-S., Kim, J.-M., Jang, Y.-S., Chang, D.-J., & Oh, D.-R. (2026). An 8-Bit Four-Channel Time-Interleaved SAR-Flash Hybrid ADC with Time-Domain Interpolation. Electronics, 15(18), 4232. https://doi.org/10.3390/electronics15184232

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