Harmonic Suppression in Active-Clamped High-Frequency Link Inverters Under Non-Unity Power Factor Loads

Abstract

High-frequency link inverters (HFLI) inherently suffer from voltage ringing, and the issue becomes more severe under non-unity power factor loads. Although active clamping circuits can effectively suppress the voltage ringing, they cause severe distortion in the output voltage and current waveforms under such loads. To address this problem, this paper proposes an improved modulation strategy with leakage energy feedback for active-clamped high-frequency link inverters (ACHFLI). In the proposed strategy, two secondary-side MOSFETs achieve zero-current switching (ZCS) turn-off, while the other two MOSFETs operate at low frequency throughout the entire line cycle. By feeding the leakage inductance energy back to the primary side, the voltage balance of the clamping capacitor can be better maintained under non-unity power factor loads, thereby mitigating the waveform distortion in the output voltage and current during the intervals when their polarities are opposite. A prototype with 48 V_in input, 110 V_o output, and 300 W rated power was built to verify the proposed strategy. Experimental results show that the modulation strategy alleviates the waveform distortion when the voltage and current have opposite polarities, and the total harmonic distortion (THD) of the output voltage is reduced by a maximum of 2.74%.

1. Introduction

Isolated DC-AC converters have been widely used in various fields, including AC grid-fed UPS systems, battery chargers for electric vehicles, and distributed renewable energy systems [1,2,3,4,5,6,7]. Among them, the high-frequency-link inverter (HFLI) has become one of the most extensively studied topologies in related applications due to its significant advantages, such as high power density, bidirectional power flow capability, and fast dynamic response [8,9]. The modulation strategies for this type of converter are mainly classified into primary-side modulation [10,11] and secondary-side modulation [12]. Compared with primary-side modulation, secondary-side modulation offers greater practical advantages, as it eliminates circulating current, enables zero-voltage switching (ZVS) for the primary-side switches, and also allows ZVS or zero-current switching (ZCS) for the secondary-side devices. However, regardless of the modulation strategy employed, high-magnitude voltage ringing inevitably appears across the secondary-side switches due to the resonance between the transformer leakage inductance and the parasitic capacitance of the secondary-side switches. The peak value of this voltage ringing can reach two to three times the steady-state voltage, posing a serious threat to the safe operation of the secondary-side switches [13,14]. Moreover, the voltage ringing issue becomes even more severe under non-unity power factor loads.

To suppress voltage ringing, various suppression circuits have been proposed. Among them, the resistor-capacitor snubber circuit [15] features a relatively simple structure; however, the resistor dissipates energy, leading to a reduction in overall system efficiency. At higher switching frequencies, this approach becomes less feasible and may even require an additional cooling system. The flyback-type regenerative snubber circuit [16] introduces magnetic components, diodes, and switching devices, thereby increasing system cost and complexity. The regenerative passive snubber circuit requires [17] no active devices, and the voltage ringing amplitude can be limited to 1.55 times the steady-state voltage. The primary-side three-leg circuit [18] mitigates voltage spikes by generating a second-order voltage waveform; nevertheless, due to errors in online calculation, a low-power resistor-capacitor-diode snubber circuit is still required for the cycloconverter switches.

Although the aforementioned suppression circuits can mitigate voltage ringing to some extent, their effectiveness is limited, and none of them can suppress it to a level close to the steady-state voltage. The full-bridge active clamp circuit [19] can effectively suppress voltage ringing to the steady-state voltage, and its control strategy is simple and easy to implement; however, it requires a relatively large number of switching devices. To reduce the number of switching devices, a half-bridge active clamp circuit [20] has been proposed in the literature. Although this circuit reduces the number of switching devices, the newly added switching devices must withstand twice the steady-state voltage. On this basis, ref. [21] integrates and simplifies the full-bridge clamp circuit with the cycloconverter, resulting in a novel active clamp circuit, as shown in Figure 1. This circuit consists of two switching devices (Q₁ and Q₂) and one clamp capacitor (C_c), and can clamp the secondary-side voltage to the steady-state level. Compared with a cycloconverter-type inverter, this circuit increases the number of switching devices and enlarges the overall converter volume. However, its conventional modulation strategy for suppressing voltage ringing under non-unity power factor loads has not been sufficiently investigated.

To address this issue, this paper proposes a modulation strategy that not only effectively suppresses voltage ringing but also improves the waveform distortion in the output voltage and current when their polarities are opposite. Compared with the conventional modulation strategy, the advantages of the proposed modulation strategy are as follows:

(1) Two MOSFETs on the secondary side achieve ZCS turn-off, and two MOSFETs operate entirely at low frequency within one line cycle, effectively reducing switching losses.

(2) The resonance between the secondary-side equivalent parasitic capacitance (C_eq) and the leakage inductance (L_k) is utilized to feed energy back to the primary side, thereby maintaining the stability of the clamp capacitor voltage, effectively suppressing voltage ringing, and improving the waveform distortion in the output voltage and current when their polarities are opposite.

The paper is organized as follows: Section 2 presents the principles of the proposed modulation strategy. Section 3 designs the clamp capacitor capacitance parameters. Section 4 validates the advantages of the proposed modulation strategy through experimental and simulation results. Finally, Section 5 concludes this paper.

2. Principle of Operation

2.1. Proposed Modulation Methods

The proposed modulation strategy is shown in Figure 2. In this strategy, u_s represents the modulating wave, and u_r represents the carrier wave. The primary-side MOSFETs operate at a fixed 50% duty cycle at the switching frequency f_k. Within one switching cycle, two modulated pulses labeled v_xy are generated (including v_xy1 and v_xy2), which increase the harmonic frequency without increasing switching losses, thereby reducing the filter requirement.

The specific switching sequence is as follows: M₁, M₂, M₃ and M₄ operate with a constant 50% duty cycle, where M₁ and M₄ turn on simultaneously, and M₂ and M₃ turn on simultaneously. During the positive half-cycle of the line frequency, M₆ and M₇ operate at low frequency, with M₆ remaining on and M₇ remaining off; M₈ turns on with a delay relative to M₁ and M₄, and its turn off is synchronized with that of M₁ and M₄; Q₁ turns on with a delay relative to M₂ and M₃, and its turn-off is synchronized with that of M₂ and M₃; M₅ and Q₂ turn-on early during the dead time and turn-off with a delay, creating a resonant interval. To avoid short-circuiting the clamp capacitor, the switching sequence must satisfy the following conditions: when M₅ turns on, Q₁ is completely off; when M₅ turns off, Q₁ has not yet turned on; when Q₂ turns on, M₈ is completely off; when Q₂ turns off, M₈ has not yet turned on. The turn-on instant of M₉ coincides with that of v_xy2, and the turn-off instant of M₉ coincides with that of v_xy1; the turn on instant of M₁₀ coincides with that of v_xy2, and the turn-off instant of M₁₀ is synchronized with that of M₁ and M₄; the turn-on instant of M₁₁ coincides with that of v_xy1, and the turn-off instant of M₁₁ is synchronized with that of M₁ and M₄; M₁₂ turns on with a delay relative to M₁ and M₄, and its turn-off instant coincides with that of v_xy2.

During the negative half-cycle of the line frequency, M₆ and M₇ operate at low frequency, with M₇ remaining on and M₆ remaining off. M₅ turns on with a delay relative to M₁ and M₄, and its turn-off is synchronized with that of M₁ and M₄. Q₂ turns on with a delay relative to M₂ and M₃, and its turn-off is synchronized with that of M₂ and M₃. M₈ and Q₁ turn on early during the dead time and turn off with a delay, creating a resonant interval. To avoid short-circuiting the clamp capacitor, the switching sequence must satisfy the following conditions: when M₈ turns on, Q₂ is completely off; when M₈ turns off, Q₂ has not yet turned on; when Q₁ turns on, M₅ is completely off; when Q₁ turns off, M₅ has not yet turned on. The turn-on instant of M₉ coincides with that of v_xy1, and the turn-off instant of M₉ is synchronized with that of M₁ and M₄. M₁₀ turns on with a delay relative to M₁ and M₄, and its turn-off instant coincides with that of v_xy2. The turn-on instant of M₁₁ coincides with that of v_xy2, and its turn-off instant coincides with that of v_xy1. The turn-on instant of M₁₂ coincides with that of v_xy2, and its turn-off instant is synchronized with that of M₁ and M₄.

The simplified operating modes of the proposed modulation strategy in the region where the voltage and current have the same polarity (V_o > 0, i_o > 0) are shown in Figure 3.

Mode 1: The circuit operates in a freewheeling state. The output current i_o flows through the loop formed by M₅, M₆, M₉ and M₁₀. C_c absorbs leakage inductance energy through M₅ and M₈.

Mode 2: Energy is transferred from the primary-side to the secondary-side load. The i_o flows through the loop formed by M₅, M₆, M₁₁ and M₁₂. C_c releases energy to the load through the path formed by M₆, M₈, M₁₁ and M₁₂.

Mode 3: The circuit enters the freewheeling state again. The i_o flows through the loop formed by M₆, M₁₁, M₁₂, and Q₂. C_c absorbs leakage inductance energy through Q₁ and Q₂. During this period, M₁₀ is turned off. Since there is no current flowing through its branch, M₁₀ achieves ZCS turn-off.

Mode 4: Energy is transferred from the primary-side to the secondary-side load again. The i_o flows through the loop formed by M₆, M₉, M₁₀, and Q₂. C_c absorbs leakage inductance energy through Q₁ and Q₂. M₁₁ is turned off during Mode 1. Since there is no current flowing through its branch at turn-off, M₁₁ achieves ZCS turn-off.

From the above analysis, it can be seen that the clamp capacitor absorbs leakage inductance energy during the freewheeling mode and then releases this energy to the load during the energy transfer mode, thereby ensuring that the clamp capacitor voltage remains in a charge-balanced state.

2.2. Operating Mode

In practical applications, non-unity power factor loads (mainly resistive–inductive and resistive–capacitive loads) introduce a phase shift between the output voltage and current of the inverter, resulting in intervals where the voltage and current have opposite polarities (V_o > 0, i_o < 0 and V_o < 0, i_o > 0). In this paper, the interval where the output voltage and current are in opposite polarities (V_o > 0, i_o < 0) is taken as an example to analyze in detail the operating modes within one switching cycle. Figure 4 shows the key waveforms of the active-clamped high-frequency-link inverter during a single switching cycle, and Figure 5 shows the corresponding circuit states of the operating modes. To simplify the analysis, the following assumptions are made:

(1) The transformer and all MOSFETs are assumed to be ideal devices.

(2) The output capacitances of the primary-side MOSFETs are denoted as C_PN (N = 1–4), and those of the secondary-side MOSFETs are denoted as C_SM (M = 5–12) and C_QX (X = 1, 2).

(3) The output capacitances of the primary-side MOSFETs are assumed to be equal, denoted as C_P; similarly, the output capacitances of the secondary-side MOSFETs are assumed to be equal, denoted as C_S.

Mode 1 (t₀–t₂): The circuit operates in a freewheeling state. The i_o flows through the loop formed by M₅, M₆, M₉, and M₁₀. During the interval t₀–t₁, C_c absorbs leakage inductance energy through M₅ and M₈. During t₁–t₂, since the clamp voltage is higher than the steady-state voltage nV_in, the C_c releases energy to the primary side.

Mode 2 (t₂–t₃): M₉ turns off, and i_o transfers from the loop formed by M₅, M₆, C_S9, and M₁₀ to the loop formed by M₅, M₆, C_S11, and C_S12. During this process, i_o charges C_S9 and discharges C_S11. At the end of this mode, C_S11 is discharged to zero.

Mode 3 (t₃–t₅): M₁₁ achieves ZVS turn-on, and i_o releases energy to the primary side through the loop formed by M₅, M₆, M₁₁, and M₁₂. During the interval t₃–t₄, the C_c absorbs secondary-side energy through M₆ and M₈, and the clamp capacitor voltage rises. During t₄–t₅, the C_c releases energy to the primary side through M₅ and M₈, and the clamp capacitor voltage falls.

Mode 4 (t₅–t₆): Primary-side switches M₁ and M₄ turn-off. M₁₀ turns off; since there is no current flowing through its branch, M₁₀ achieves ZCS turn-off. i_o releases energy to the primary side through the loop formed by M₅, M₆, M₁₁, and M₁₂.

Mode 5 (t₆–t₇): Q₂ turns on early. L_k and C_eq resonate, feeding energy back to the primary side. i_o transfers from the loop formed by M₅, M₆, M₁₁, and M₁₂ to the loop formed by Q₂, M₆, M₁₁, and M₁₂.

Mode 6 (t₇–t₈): i_o flows through the loop formed by Q₂, M₆, M₁₁, and M₁₂. When C_Q1 is discharged to zero, the leakage inductance energy is absorbed by C_c through the body diode of Q₁ and Q₂, and the clamp capacitor voltage rises.

The operating modes in the second half of the high-frequency switching cycle are symmetric to those analyzed above and are not described here for brevity. Under non-unity power factor load conditions, voltage ringing becomes more severe. By introducing a resonant path formed by L_k and C_eq to feed energy back to the primary side, the clamp capacitor voltage can be effectively maintained stable, thereby improving the distortion in the output voltage waveform. During the positive half-cycle of the line frequency, M₁₀ and M₁₁ are not in the current path when they turn off, thus achieving ZCS turn-off. Similarly, during the negative half-cycle of the line frequency, M₉ and M₁₂ can also achieve ZCS turn-off.

3. Design of the Clamp Capacitor

Based on the analysis of the charging and discharging states of the clamp capacitor, the corresponding equivalent circuit model is shown in Figure 6.

According to the circuit model of the CC charging state, the equation can be formulated as follows.

$$\left\{\begin{array}{l}n{V}_{\mathrm{in}}-V_{\mathrm{Cc}}(t)-L_{\mathrm{k}}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{s}}(t)}{\mathrm{d}t}}=0\\ C_{\mathrm{c}}{\displaystyle \frac{\mathrm{d}{V}_{\mathrm{Cc}}(t)}{\mathrm{d}t}}=i_{\mathrm{s}}(t)\end{array}\right.$$

(1)

Assuming i_s(0) = I_s and V_Cc(0) = V_C, solving the above equations yields

$$\left\{\begin{array}{l}{i}_{\mathrm{s}}(t)=I_{\mathrm{s}}\cos ({\displaystyle \frac{t}{\sqrt{L_{\mathrm{k}}{C}_{\mathrm{c}}}}})+{\displaystyle \frac{(n{V}_{\mathrm{in}}\hspace{0.17em}-\hspace{0.17em}{V}_{\mathrm{C}})\sqrt{C_{\mathrm{c}}}}{\sqrt{L_{\mathrm{k}}}}}\sin \left({\displaystyle \frac{t}{\sqrt{L_{\mathrm{k}}{C}_{\mathrm{c}}}}}\right)\\ V_{\mathrm{Cc}}(t)=n{V}_{\mathrm{in}}-(n{V}_{\mathrm{in}}\hspace{0.17em}-\hspace{0.17em}{V}_{\mathrm{C}})\cos ({\displaystyle \frac{t}{\sqrt{L_{\mathrm{k}}{C}_{\mathrm{c}}}}})+{\displaystyle \frac{I_{\mathrm{s}}\sqrt{L_{\mathrm{k}}}}{\sqrt{C_{\mathrm{c}}}}}\sin \left({\displaystyle \frac{t}{\sqrt{L_{\mathrm{k}}{C}_{\mathrm{c}}}}}\right)\end{array}\right.$$

(2)

To simplify the calculation, it is assumed that i_o remains constant at I_o within one switching cycle. Then, according to the circuit model of the C_c-discharging state, the equation can be formulated as follows.

$$\left\{\begin{array}{l}n{V}_{\mathrm{in}}-V_{\mathrm{Cc}}(t)-L_{\mathrm{k}}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{s}}(t)}{\mathrm{d}t}}=0\\ C_{\mathrm{c}}{\displaystyle \frac{\mathrm{d}{V}_{\mathrm{Cc}}(t)}{\mathrm{d}t}}+I_{\mathrm{o}}=i_{\mathrm{s}}(t)\end{array}\right.$$

(3)

The initial state of the circuit is

$$\left\{\begin{array}{l}{I}_{\mathrm{s}1}=I_{\mathrm{s}}\cos ({\displaystyle \frac{T-\frac{D}{T}}{\sqrt{L_{\mathrm{k}}{C}_{\mathrm{c}}}}})+{\displaystyle \frac{(n{V}_{\mathrm{in}}-\hspace{0.17em}{V}_{\mathrm{C}})\sqrt{C_{\mathrm{c}}}}{\sqrt{L_{\mathrm{k}}}}}\sin ({\displaystyle \frac{T-\frac{D}{T}}{\sqrt{L_{\mathrm{k}}{C}_{\mathrm{c}}}}})\\ V_{\mathrm{C}1}=n{V}_{\mathrm{in}}-(n{V}_{\mathrm{in}}\hspace{0.17em}-\hspace{0.17em}{V}_{\mathrm{C}})\cos ({\displaystyle \frac{T-\frac{D}{T}}{\sqrt{L_{\mathrm{k}}{C}_{\mathrm{c}}}}})+{\displaystyle \frac{I_{\mathrm{s}}\sqrt{L_{\mathrm{k}}}}{\sqrt{C_{\mathrm{c}}}}}\sin ({\displaystyle \frac{T-\frac{D}{T}}{\sqrt{L_{\mathrm{k}}{C}_{\mathrm{c}}}}})\end{array}\right.$$

(4)

Let D be the duty cycle, I_s1 the initial condition of the secondary current, and V_C1 the initial condition of the clamp capacitor voltage. Substituting these into Equation (3) and solving yields

$$V_{\mathrm{Cc}}(t)=n{V}_{\mathrm{in}}-(n{V}_{\mathrm{in}}\hspace{0.17em}-\hspace{0.17em}{V}_{\mathrm{C}1})\cos ({\displaystyle \frac{t}{\sqrt{L_{\mathrm{k}}{C}_{\mathrm{c}}}}})+{\displaystyle \frac{(I_{\mathrm{o}}+I_{\mathrm{s}1})\sqrt{L_{\mathrm{k}}}}{\sqrt{C_{\mathrm{c}}}}}\sin \left({\displaystyle \frac{t}{\sqrt{L_{\mathrm{k}}{C}_{\mathrm{c}}}}}\right)$$

(5)

To ensure the stability of the clamp capacitor voltage, its voltage ripple amplitude must not exceed 5% of the steady-state voltage nV_in.

$$C_{\mathrm{c}}\ge {\displaystyle \frac{L_{\mathrm{k}}{(I_{\mathrm{s}1}+I_{\mathrm{o}})}^2}{{0.05}^2\times n^2{V}_{\mathrm{in}}^2}}$$

(6)

Using the relevant experimental parameters (specific parameters are given in Section 4), substituting L_k = 12.9 μH, I_o = 2.73 A, n = 5, I_s1 = 2.73 A and V_in = 40 V into Equation (6) yields a minimum clamp capacitance of 3.8 μF. To ensure the stability of the clamp capacitor voltage, a clamp capacitance of 15 μF is selected in this paper.

4. Simulation and Experimental Results

To verify the proposed modulation strategy, a 300 W prototype with 48 V_in input and 110 V_o output is built (see Figure 7). The key parameters and components are listed in

Table 1. Specifications of the inverter prototype.

Parameter	Symbol	Value
Input voltage	Vin	40 V–54 V
Output voltage	Vo	110 V
Transformer turn ratio	n	5
Leakage inductance (secondary-side)	Lk	12.9 μH
Magnetizing inductance (primary-side)	Lm	159 μH
Camp capacitor	Cc	15 μF
Rated power	Po	300 W
Filter inductances	Lf	3 mH
Filter capacitor	Cf	680 nF
primary-side transistors	M1–M4	NCEP033N10
secondary-side transistors	M4–M12 Q1–Q2	GC2M0080120D1
Microcontroller	-	TMS320F280049

. Although a 300 W prototype is demonstrated here, the proposed modulation strategy can be readily scaled to higher power levels (well beyond 300 W, e.g., several kilowatts) by resizing the power devices and magnetic components accordingly. Moreover, the strategy does not rely on a specific transformer turns ratio; it can be easily adapted to other input/output voltage specifications by adjusting the control parameters.

To avoid excessive inrush current on the primary side when charging the C_c, the primary-side MOSFETs operate with a small duty cycle to pre-charge the C_c, as shown in Figure 8. Once the clamp capacitor voltage reaches nV_in, the secondary side initiates a soft start and eventually transitions to normal operation. With pre-charging, the maximum inrush current is only 32.6 A.

Figure 9 shows the experimental waveforms of the primary-side current i_p, secondary-side voltage V_ab, output voltage V_o, and output current i_o without the proposed improved modulation strategy (without introducing the L_k and C_eq resonant region) under three different resistive–inductive load conditions: (1) P = 165 W, Q_L = 77.8 var; (2) P = 148 W, Q_L = 89.1 var; (3) P = 163.5 W, Q_L = 131.5 var (P: active power; Q_L: inductive reactive power). During the intervals when the output voltage and output current have opposite polarities, severe waveform distortion is observed, with the output voltage THD reaching 3.74%, 3.8%, and 4.1%, respectively. Meanwhile, the i_p increases significantly during these intervals.

Figure 10 shows the experimental waveforms of the i_p, V_ab, V_o, and i_o under the same resistive–inductive load conditions (identical to the three load cases in Figure 9) with the proposed improved modulation strategy (by introducing the L_k and C_eq resonant region). During the intervals when the output voltage and output current have opposite polarities, the waveform distortion is significantly mitigated, and the output voltage THD is reduced to 1.27%, 1.39%, and 1.66%, respectively. Moreover, i_p does not exhibit a significant increase during these intervals, and its variation trend remains consistent with that of i_o. In addition, it can be observed from the figure that the secondary-side voltage approaches the steady-state value and the voltage ringing is effectively suppressed.

Figure 11 shows the experimental waveforms of i_p, V_ab, V_o, and i_o without the proposed improved modulation strategy (without introducing the L_k and C_eq resonant region) under different resistive–capacitive load conditions. The three load cases are: (1) P = 231 W, Q_C = −105.7 var; (2) P = 130.7 W, Q_C = −105.7 var; (3) P = 110.5 W, Q_C = −105.7 var (Q_C: capacitive reactive power.). During the intervals when the output voltage and output current have opposite polarities, severe waveform distortion is observed, with the output voltage THD reaching 3.78%, 4.01%, and 4.11%, respectively. Meanwhile, the i_p increases significantly during these intervals.

Figure 12 presents the experimental waveforms of the i_p, V_ab, V_o, and i_o under the same resistive–inductive load conditions (identical to the three load cases in Figure 11) with the proposed improved modulation strategy (by introducing the L_k and C_eq resonant region). During intervals when the output voltage and output current have opposite polarities, the waveform distortion is significantly mitigated, and the output voltage THD is reduced to 1.69%, 1.71%, and 1.81%, respectively. Moreover, i_p does not exhibit a significant increase during these intervals, and its variation trend remains consistent with that of i_o. In addition, it can be observed from the figure that the secondary-side voltage approaches the steady-state value and the voltage ringing is effectively suppressed.

Figure 13 compares the output voltage THD of the two modulation strategies under resistive–capacitive and resistive–inductive loads. By introducing the resonant region, the proposed modulation strategy can feed energy back to the primary side, thereby better maintaining the voltage stability of the clamp capacitor under non-unity-power-factor loads (mainly including resistive–capacitive and resistive–inductive loads). Consequently, this strategy effectively mitigates the waveform distortion during intervals when the output voltage and output current have opposite polarities, reducing the output voltage THD by up to 2.74%.

Figure 14 shows the experimental waveforms of the gate drive voltages V_GSM6 (M6), V_GSM7 (M₇), and the output voltage V_o. It can be observed that the switching frequencies of M₆ and M₇ are identical to the output voltage frequency, indicating that both switches operate in a low-frequency regime.

Figure 15 shows the gate-source drive voltage V_GS and drain-source voltage V_ds of the secondary-side switches. It can be observed that V_GS starts to rise only when V_ds is zero, with no overlap between them, indicating that M₁₀ and M₁₁ achieve ZVS turn-on.

Figure 16 shows the simulated waveforms of the gate-source drive voltage V_GS of M₁₀ and M₁₁ and the drain-source current i_ds. It can be observed that i_ds is zero when M₁₀ and M₁₁ are turned off, indicating that both switches achieve ZCS turn-off. Under the same experimental conditions, the conduction losses and transformer losses of the proposed modulation strategy and the modulation strategy in [21] are essentially equivalent, and both can achieve soft switching of the primary-side MOSFETs. Therefore, the comparison focuses on the switching losses caused by the secondary-side MOSFETs, which can be expressed as:

$$P_{\mathrm{on}/\mathrm{off}}={\displaystyle \frac{1}{2}}{V}_{\mathrm{ds}}{I}_{\mathrm{ds}\_\mathrm{on}/\mathrm{off}}{t}_{\mathrm{on}/\mathrm{off}}{f}_{\mathrm{k}}$$

(7)

Substituting V_ds = 240 V, I_ds-on = 4.925 A, I_ds-off = 3.325 A, t_on = 88 ns, t_off = 57 ns, and f_k = 40 kHz/50 Hz into Equation (7) yields that the switching loss of the proposed modulation strategy is reduced by approximately 5.7 W compared with that of the modulation strategy in [21].

5. Conclusions

This paper addresses aggravated voltage ringing and severe distortion in the output voltage and current waveforms of ACHFLI under non-unity power factor loads, and proposes an improved modulation strategy with leakage energy feedback. In this strategy, two secondary-side MOSFETs achieve ZCS turn-off, while the other two MOSFETs operate at low frequency throughout the entire line cycle. By feeding the leakage inductance energy back to the primary side, the voltage balance of the clamping capacitor is effectively maintained, thereby significantly mitigating the waveform distortion in the output voltage and current during intervals when their polarities are opposite. Experimental results demonstrate that the proposed modulation strategy effectively alleviates the waveform distortion when the voltage and current have opposite polarities, and the THD of the output voltage is reduced by a maximum of 2.74%, confirming the feasibility and effectiveness of the approach.