Flores, F.; Portela Queimaño, J.; Costa Pazo, J.M.; Valdés-Peña, M.D.; Quintáns Graña, C.; Villapún Sánchez, J.M.
An Optimized Floating-Point Unit Set for FPGA-Based DSP: Improving Area, Energy, and Throughput Trade-Offs. Electronics 2026, 15, 2850.
https://doi.org/10.3390/electronics15132850
AMA Style
Flores F, Portela Queimaño J, Costa Pazo JM, Valdés-Peña MD, Quintáns Graña C, Villapún Sánchez JM.
An Optimized Floating-Point Unit Set for FPGA-Based DSP: Improving Area, Energy, and Throughput Trade-Offs. Electronics. 2026; 15(13):2850.
https://doi.org/10.3390/electronics15132850
Chicago/Turabian Style
Flores, Fernando, Juan Portela Queimaño, Jesús Manuel Costa Pazo, MarÃa Dolores Valdés-Peña, Camilo Quintáns Graña, and José Manuel Villapún Sánchez.
2026. "An Optimized Floating-Point Unit Set for FPGA-Based DSP: Improving Area, Energy, and Throughput Trade-Offs" Electronics 15, no. 13: 2850.
https://doi.org/10.3390/electronics15132850
APA Style
Flores, F., Portela Queimaño, J., Costa Pazo, J. M., Valdés-Peña, M. D., Quintáns Graña, C., & Villapún Sánchez, J. M.
(2026). An Optimized Floating-Point Unit Set for FPGA-Based DSP: Improving Area, Energy, and Throughput Trade-Offs. Electronics, 15(13), 2850.
https://doi.org/10.3390/electronics15132850
