A Novel Low-Power True Random Number Generator Using LOMOS Topology with Entropy-Based Adaptive Windowing

Abstract

An important module that must be present in any communication system is a random number generator (RNG). One of the RNGs is the True RNG (TRNG), which is completely random. The output of the TRNG is unpredictable as it extracts its randomness from physical phenomena such as temperature, noise, power supply fluctuations, timing jitter in oscillators, and metastability in digital circuits. It is used in many applications such as cryptography, IoT sensors, and mobile equipment. In this paper, a novel low-power TRNG architecture is proposed: its core novelty is that all the system modules are adaptive to be more efficient and cooperate with system variations. It consists of a morphing gated ring oscillator, a lightweight real-time entropy monitoring, and a dynamic sampling window. Each module is verified before system integration. Our system strikes a favorable trade-off between randomness and power consumption as all the modules are implemented using LOMOS standard cells—a power-efficient topology for CMOS logic gate design. It consumes 0.226 μW from a 0.4 V supply at 1 MHz. The proposed architecture is evaluated using the NIST SP 800-22 statistical test suite, and successfully passes 10 randomness tests.

1. Introduction

Randomness is often treated as a mathematical abstraction, yet in physical systems, it emerges as a subtle fingerprint of the inherent unpredictability of nature. Generally, two classifications of random number generators (RNGs) exist: Pseudo RNGs (PRNGs) and True RNGs (TRNGs) [1]. A PRNG is predictable as it uses a seed to generate output; when the seed is repeated, the output will be the same [2]. On the contrary, a TRNG is unpredictable. While deterministic machines excel at precision and repeatability, they fundamentally lack the ability to generate true entropy. This limitation has transformed the design of TRNGs from a peripheral concern into a foundational challenge.

The unpredictability of the output numbers is extracted from a common entropy source which is the jitter on clock signals. Jitter can be viewed as timing deviation from the theoretically correct position due to electronic noise, it typically follows a Gaussian distribution characterized by a certain standard deviation [3]. Usually, jitter is an unwanted property in a system, but this behavior is useful when generating random signals in a TRNG. Randomness originates from the fact that transistors are noisy and they suffer from thermal noise, flicker noise, supply noise, and substrate coupling [4]. These phenomena are random, time-varying, and uncorrelated across devices. Oscillator-based TRNGs benefit from the jitter: the ideal period of a ring oscillator (RO) equals $2\times N\times T_{inv}$, where N is the number of stages and $T_{inv}$ is the inverter delay. Each inverter delay fluctuates and changes every cycle [5]. This creates phase noise (jitter).

Several TRNG architectures have been proposed. Fully synthesized and all-digital TRNGs have attracted significant attention due to their portability and ease of integration. In [6], a three-edge multi-mode RO-based TRNG was implemented entirely using a standard-cell digital flow. It uses a single RO, thereby improving robustness against external noise. Similarly, ref. [7] proposed a collapsing RO-based TRNG that eliminates the need for custom analog structures. In addition, ref. [8] introduced an all-digital metastability-based TRNG using arbiter circuits, where randomness is generated by comparing two nearly identical signal paths and the output depends on which signal arrives first. Multiple arbiters operate in parallel to achieve high throughput. Moreover, for high throughput, ref. [9] proposed an oscillator-based TRNG that exploits jitter in multi-ring oscillators combined with noise amplification. It provides an advantage in terms of speed and implementation simplicity. For stronger physical entropy sources, ref. [10] introduced a TRNG based on random telegraph noise (RTN), where entropy is extracted directly from charge trapping and de-trapping events in a single transistor. As a result, it offers inherently unpredictable random behavior with minimal reliance on digital architectural complexity. To further improve robustness, ref. [11] proposed a differential RO-based TRNG with feedback resistors. This approach has better noise immunity and is robust compared to single-ended oscillator designs.

To sum up, multi-oscillator TRNGs achieve relatively simple implementation and high-speed operation, but they suffer from power overhead and coupling effects, which can degrade entropy. In contrast, metastability and RTN-based designs shift entropy generation to physical phenomena, improving randomness and theoretical robustness; however, they are constrained by low throughput, the need for analog sensing circuitry, and sensitivity to process, voltage, and temperature (PVT) variations. Finally, high-speed all-digital TRNGs significantly increase data rates through parallel sampling and calibration techniques, but this comes at the cost of high power consumption, large area, and architectural complexity.

The proposed TRNG architecture is based on four key innovations: a Morphing Gated Ring Oscillator (GRO), a Lightweight Entropy Monitor, an Adaptive Controller, and all of them are implemented using LOMOS topology. The primary objective of this work is to develop a fully digital energy-efficient TRNG capable of maintaining high-quality randomness under varying operating conditions while minimizing power consumption.

To achieve this goal, the proposed design employs a morphing GRO whose oscillation structure is dynamically reconfigured according to the measured entropy level. When entropy degrades, additional oscillation stages are activated to enhance randomness generation; conversely, when sufficient entropy is available, oscillator activity is reduced to lower power consumption. Furthermore, the use of a gated oscillator, rather than a continuously operating ring oscillator, significantly decreases dynamic power dissipation by restricting oscillation to predefined time intervals. In addition, a lightweight entropy monitoring and adaptive control mechanism is introduced to continuously evaluate the entropy and adjust system operation accordingly. This includes an adaptive windowing strategy that dynamically modifies sampling and halting intervals based on real-time entropy estimates, as well as a controlled operational sequence that separates oscillation, accumulation, evaluation, and sampling phases. Together, these mechanisms improve statistical randomness, reduce temporal correlation between successive samples, and enhance the robustness of entropy extraction. Finally, all system modules are implemented using LOMOS topology [12], enabling substantial reduction in overall power consumption.

The paper is organized as follows: Section 2 presents the proposed TRNG architecture and its operating principle, followed by the design and verification of the LOMOS-based building sub-blocks and the system modules that are constructed from them. Section 3 describes the integration of these modules into the complete TRNG system and presents the overall system verification. Section 4 discusses the simulation results, including evaluation using the NIST randomness test suite, and compares its performance with state-of-the-art TRNG designs. Finally, Section 5 presents the conclusion.

2. Proposed TRNG Architecture

The fundamental functional blocks of a TRNG consist of an oscillator, a counter, a sampler, and a post-processing unit that extracts and conditions entropy to produce robust, unbiased, and standards-compliant output. The general concept is that an RO does not oscillate at a perfectly constant period. The instantaneous phase of the RO contains unpredictable timing variations (jitter) caused by thermal noise and device noise. Then, sampling creates random bits; the RO output is sampled using a reference clock [13], if the RO edge arrives near the D flipflop aperture window, the D flipflop may become metastable. Thus, the final resolved value is unpredictable; this is typically followed by post-processing to improve statistical randomness quality. This is the core TRNG mechanism.

To design the full architecture (shown in Figure 1) of such a system, the functions that need to be performed are divided across several modules. The interface of each module must be designed accurately so that the output ports match the input ports of the next module in the chain. To make sure that the system performs as expected, each module is implemented separately and verified, then all modules are integrated together. After that, the whole system is verified. In this section, the functionality of each module, its internal design, and its input/output interface signals will be explained.

2.1. LOMOS Sub-Blocks and Their Verification

Before discussing the individual system modules, it is essential to introduce the underlying circuit topology used to implement them. The proposed TRNG is built using a novel logic topology known as LOMOS. As demonstrated by the figure of merit (FOM) reported in [12], LOMOS has a good balance between power consumption and area. Moreover, it is robust to temperature variations across a large range. It is designed to work in the subthreshold region by scaling down the supply voltage ($V_{dd}$) to 400 mV. The proposed TRNG system is implemented using LOMOS standard cells [12]. These standard cells are utilized to implement key building blocks such as comparators, multiplexers, and flipflops, which are subsequently integrated into the system modules. The functionality of these building blocks is verified prior to their integration into the overall system.

2.1.1. Flipflop

This sub-block is a fundamental element utilized throughout all modules. In Figure 2, the design of a synchronous D flipflop is realized using LOMOS topology and is constructed from NAND and inverter gates [14], ensuring edge-triggered operation. The input is precisely sampled only at the rising edge of the clock (CLK), while all intermediate fluctuations are effectively rejected.

The simulation in Figure 3 shows the operation of a positive edge-triggered D flipflop, clearly demonstrating its sampling, storage, and edge-sensitive behavior. Output Q only updates at the rising edges of the clock. At each rising edge, Q takes the instantaneous value of D. Around 4 µs, a rising clock edge samples a high value at D, resulting in Q transitioning from logic low to high. While around 6 µs, the next rising edge captures a low value at D, causing Q to switch from high to low. Between clock edges, even though D continues to toggle, Q remains constant, confirming proper isolation of input variations and reliable storage of the last sampled state. The complementary output Q′ consistently remains the inverse of Q, validating correct internal operation.

2.1.2. Multiplexer

The circuit design shown in Figure 4 implements a 2 × 1 multiplexer with inputs $\mathrm{A}$ and $\mathrm{B}$, where the selector signal determines which input is propagated to the output. The circuit is realized using NAND, NOR, and inverter gates. When the selector equals 0, the output follows $\mathrm{A}$; when the selector equals 1, the output follows $\mathrm{B}$.

Figure 5 presents the transient simulation of the 2 × 1 multiplexer, clearly demonstrating its correct switching behavior under a time-varying select signal. The select signal alternates between logic high and logic low, directly controlling the input to output path of the circuit. When the selector signal is high (duration: 0–1.5 μs and 3–4.5 μs), the multiplexer routes input B to the output. Conversely, when the selector signal is low (duration: 1.5–3 μs and after 4.5 μs), the circuit switches to input A, and the output accurately tracks A. The close alignment between output and the selected input in each interval confirms correct operation, stable switching, and proper response to selector transitions without observable glitches.

2.1.3. Comparator

The comparator architecture shown in Figure 6 is constructed from NAND, XNOR, and inverter-based logic stages. It is designed to perform an equality comparison between two multi-bit inputs, A and B, by evaluating each corresponding bit pair and propagating the match condition through the logic network. The output is asserted as high only when all bits of A and B are identical, indicating a full match condition. For a 4-bit comparator, each input is composed of 4 bits.

Figure 7 verifies the functionality of this sub-block through simulation, having two inputs A [3:0] and B [3:0]. Input A is fixed to 5 (in binary representation: 0101), thus the output transitions to a logic-high state only when input B equals 5, confirming correct equality detection around 5.5 μs and demonstrating the reliability of the proposed design. The four waveforms (B [0] till B [3]) represent the analog voltage signals corresponding to the individual bits of input B, while the bus waveform shown below provides their equivalent decimal representation. As shown in the waveform, when input B equals 5, the output signal is not asserted instantaneously. Instead, a small delay is observed before the output transitions to logic high. This delay results from the propagation delay of the combinational comparator circuit.

2.2. Morphing GRO

The Morphing GRO is the first key contribution of the proposed TRNG. It is a ring oscillator whose number of delay elements, feedback path, and effective loop delay changes during the operation, not just at reset. Thus, the entropy source itself is non-stationary. The frequency of oscillation is characterized by the number of inverters, known as stages, and the delay of each inverter, which is determined by the topology used and the sizing of the gates. To avoid deterministic glitches, the change in the number of stages must occur when the oscillator is disabled. Thus, the behavior of the system is regulated by a control signal resulting in two states: when the enable signal is low, the topology can be reconfigured, whereas when the enable signal is high, the oscillator is held in continuous operation and maintains oscillation.

Most papers use either a fixed RO topology [15] or select one topology once at startup [16]. However, in this paper, a dynamic reconfiguration for the entropy source at runtime is based on entropy feedback. This increases entropy as each configuration has a different oscillation frequency, different phase noise power spectral density, and different sensitivity to voltage and temperature variations. When topology is switched: phase continuity is broken, frequency jumps, and jitter statistics change. We opted to implement a GRO instead of a basic RO to save power as the GRO only oscillates when enable is asserted [17]. The proposed GRO physically gates the oscillation loop using an enable-controlled AND gate. When enable is low, oscillation ceases entirely.

As illustrated in Figure 8, the module accepts three inputs: a reset signal for deterministic initialization, an enable signal to activate the oscillation process, and a 2-bit GRO_mode control that governs the effective number of delay stages within the ring. This programmable topology allows the oscillator to morph its internal structure in real time, thereby modulating the oscillation frequency with fine granularity. The output of the module is a tunable oscillation signal whose frequency is directly influenced by the selected GRO mode, making the design particularly suitable for applications requiring adaptive timing generation. The simplicity of the interface combined with its structural flexibility enables seamless integration into larger digital architectures while maintaining precise control over performance and power trade-offs. Figure 9 shows the internal gate level of this module—the three control signals are controlled by the GRO mode signal. The number of stages is defined by the GRO mode signal, which is composed of 2 bits. When GRO mode = 0, seven-stage GRO configuration is enabled. When GRO mode = 1, five-stage GRO is enabled, while three-stage GRO is activated when GRO mode = 2 or 3. The green blocks can be considered as switches; thus, two control signals should be low and only one must be high. When the GRO mode is set to 0, seven-stage GRO configuration is enabled; thus, Ctrl 3 must close its corresponding switch while Ctrl 1 and Ctrl 2 remain open. The Ctrl 3 signal is generated by NORing the two GRO mode bits, ensuring that it becomes active only for that specific mode selection. While Ctrl 2 is generated by NORing bit [1] with complementary bit [0], lastly, Ctrl 1 equals bit [1] of the GRO mode. All gates are implemented using LOMOS topology.

Figure 10 verifies the correct operation and configurability of the Morphing GRO. When the enable signal is asserted, the oscillator immediately begins generating a periodic output, confirming proper activation of the oscillation mechanism.

Two distinct operating modes are demonstrated through the GRO_mode [1:0] control. When GRO_mode = 0, the oscillator is configured with seven stages, resulting in a longer propagation delay. Consequently, the oscillation frequency is lower, as evidenced by the wider spacing between successive waveform peaks. In contrast, when GRO_mode = 1 (after 8 μs), the structure is reduced to five stages, shortening the total delay path. This reduction directly increases the oscillation frequency, which is clearly observed in the denser waveform cycles within the same time interval. These results confirm the fundamental relationship between the number of delay stages and oscillation frequency: increasing the number of stages increases the total delay and reduces the oscillation frequency. The simulation thus demonstrates the effectiveness of the proposed Morphing GRO in achieving dynamic and controllable frequency tuning through simple digital control.

2.3. Lightweight Entropy Monitor

This is the second key contribution of the proposed TRNG. It is a real-time statistical quality control block that evaluates whether the raw bitstream has sufficient randomness before it is released or post-processed. The correlation is detected, if there is strong correlation then the entropy is bad. The last two bits are used for this calculation. For each bit, the last two samples are XORed, for i = 0 and 1: $d_i\left[n\right]=b_i\left[n\right]\oplus b_i\left[n-1\right]$. This detects whether a transition occurred between consecutive samples or not. We chose the least significant 2 bits and not the most significant bits (MSBs) as the MSB toggles slower than the least significant bit (LSB), so the entropy estimation will be misleading. Moreover, 2 bits and not just one bit are chosen to increase robustness and to improve reliability.

In an RO (jitter-based) TRNG, entropy is carried by timing jitter (phase noise); thus, useful randomness manifests as variability in successive samples: frequent transitions indicate that the sampling edge is moving relative to the RO phase, while long runs of identical bits suggest low jitter, locking, or over-slow sampling. Thus, the XOR output serves as a fast proxy for temporal correlation by estimating the transition probability $P\left(b\right[n]\ne b[n-1\left]\right)$. The approach is extremely low-cost and provides immediate feedback for adaptive control (adjusting the sampling window when transitions are scarce).

The inputs consist of the current and previously sampled values of two-bit streams (bit [0] and bit [1]) along with control signals including clock, reset, and sample_en, as shown in Figure 11. Figure 12 illustrates its internal design: for each bit stream, the current value is XORed with its corresponding previous value, effectively detecting transitions between successive samples. These operations generate two intermediate signals, $d_0$ and $d_1$, indicating whether a change has occurred in bit [0] and bit [1], respectively. The results are then combined using a logical OR operation, producing a single decision metric that reflects the presence of activity in either stream. The sample_en signal is asserted for one clock cycle to latch and validate the output, ensuring that the entropy decision is synchronized with system timing. The final output, entropy_ok, is asserted as high whenever at least one transition is detected ($d_0=1$ or $d_1=1$), indicating acceptable entropy. Conversely, if no transitions are observed, the output remains low, signaling insufficient randomness. This behavior confirms that the entropy monitor effectively captures temporal variations in the input streams and provides a simple yet reliable mechanism for real-time entropy validation.

Two test case scenarios are shown in Figure 13, where bits [0] and [1] are observed over a period of time. In case (a), previous bits [0] and [1] are sampled at V1, and then at the next clock edge, V2 current bits [0] and [1] are detected. These two samples are then processed using XOR and OR operations. At the next clock edge, which is V3 (when sample_en is asserted), the entropy_ok control signal is generated. In this scenario, bit [1] did not change during two consecutive clk periods, while bit [0] did change, indicating the presence of good entropy. In case (b), both bits [0] and [1] did not change across the sampling intervals, V4 and V5, so at V6 when the sample_en is high, entropy_ok is de-asserted, indicating bad entropy. Overall, these calculations require three clk periods; two of them to capture samples at distinct time instances and the third to compute the entropy and accordingly regulate the rest of the system.

2.4. Adaptive Controller

This is the third key contribution of the proposed TRNG. After the entropy is evaluated, the output flag from the entropy monitor module controls the adaptive controller module. Based on this flag, the controller dynamically adjusts the observation window size. When the entropy is deemed sufficient, the controller reduces the window length by a predefined step. Conversely, when the entropy is insufficient, the window size increases. The window is constrained within predefined minimum and maximum bounds to ensure stable operation. If the window size reaches its maximum limit while the entropy remains inadequate, the controller modifies the GRO configuration by reducing the number of stages. This structural adjustment decreases the overall propagation delay, resulting in a higher oscillation frequency that can improve entropy generation in subsequent cycles. The GRO topology is controlled by the GRO_mode signal. The input and output signals are shown in Figure 14, and to achieve the specified functionality, the module can be structurally designed as in Figure 15, Figure 16 and Figure 17. In Figure 15, the smaller than block compares the window size with its initialized minimum value so that when the window length decreases, it cannot be smaller than the lower bound. The same goes for the bigger than block, the window size cannot increase above the maximum bound. In Figure 17, the “x2” means that this path is repeated two times, as our window is 6 bits, so the gate level of window [3] is the same as window [5], and that of window [2] is the same as window [4].

This approach establishes a two-dimensional adaptation mechanism that operates across both time (window size) and structure (GRO topology). Unlike many conventional TRNG designs that rely on offline entropy evaluation and manual parameter tuning, the proposed system performs continuous, real-time adaptation. In summary, the adaptive controller implements three possible actions: increasing the window size, decreasing the window size, or reconfiguring the GRO topology. This dynamic decision-making process makes our proposed design adaptive, non-stationary, and robust.

The simulation results in Figure 18 demonstrate the dynamic behavior of the adaptive controller in response to real-time entropy evaluation. The system is initialized with a window size of 30, a step size (Δ) of 5, and bounded limits of 20 (minimum) and 60 (maximum).

At each assertion of the sample_en signal, the entropy is evaluated through the entropy_ok flag, and the window size is updated accordingly for the subsequent cycle. At t = 40 µs, the entropy is identified as insufficient (entropy_ok = 0), prompting the controller to increase the window size from 30 to 35. This increase reflects the need for a longer observation period to improve entropy estimation. Later, at t = 120 µs, the entropy is classified as sufficient (entropy_ok = 1), leading to a reduction in the window size, thereby optimizing efficiency by avoiding unnecessary sampling overhead. This adaptive behavior continues throughout the simulation, where the window size incrementally increases or decreases in discrete steps of Δ based on the entropy condition observed at each sampling instant. Additionally, it is observed that the GRO_mode remains unchanged during this period, indicating that structural adaptation is not triggered. The GRO topology is only reconfigured when the window size reaches its maximum bound (60) and the entropy remains inadequate. This confirms that the controller prioritizes temporal adaptation (window scaling) before resorting to structural modification (GRO reconfiguration).

Overall, the simulation validates the effectiveness of the proposed adaptive strategy, where real-time feedback enables continuous tuning of the system parameters to maintain optimal entropy generation while balancing performance and resource utilization.

The next two simulations show two corner cases to verify that the module works correctly in all scenarios. Figure 19 confirms that when the window size reaches its maximum (60) and the entropy is still bad, the other varying dimension will change. The GRO topology will change, and this appears through the GRO_mode signal. As the mode increases, the number of stages of the GRO will decrease, thus generating faster oscillation which may lead to better entropy. On the contrary, Figure 20 shows the opposite scenario: when the minimum window size (20) is reached and the entropy is good, it keeps functioning with the same window size. Around 63 μs, when sample_en is asserted, the entropy is evaluated as good, so the window size did not change.

2.5. Enable Window

This module specifies the temporal window during which the system remains enabled and operational. Its design is composed of a counter and a finite state machine (FSM), and the interface is shown in Figure 21. This FSM plays a key role in coordinating the system’s operational timing. After the window length is configured from the previous module, the enable signal activates the counter so it advances until it matches the predefined window size. At this point, the “equal to window size” flag is asserted, indicating completion of the measurement interval. This event immediately forces a transition that de-asserts the enable signal, stopping the oscillation and isolating the system in a Quiet state to allow stable evaluation of the generated data. Once internal computations are settled, the sample_en signal is asserted to capture the output. The FSM cycles through four well-defined states: S0 (counting phase under active enable), S1 (window match detected and flag asserted), S2 (oscillation disabled, quiet evaluation phase), and S3 (output sampling phase). Reasserting the enable signal, the flow is repeated with a new window configuration. These state transitions are realized through the gate-level implementation depicted in Figure 22 and Figure 23.

Fundamentally, the module is designed to enforce strict temporal separation between its key operational stages—oscillation, accumulation, evaluation, and sampling. Each phase is executed in isolation, ensuring that no overlap occurs between entropy generation and subsequent digital processing. This disciplined sequencing preserves timing integrity by minimizing race conditions and metastability while also guaranteeing consistent and reliable entropy extraction under well-controlled conditions.

Figure 24 clearly demonstrates the deterministic timing behavior of the module for a window length of 10. The four light blue waveforms represent the analog voltage signals corresponding to the individual bits of the counter, while the bus waveform shown below them provides their equivalent decimal representation. Upon assertion of the enable signal, the counter begins incrementing synchronously with the clock, progressing from 0 up to 10 while the GRO remains active. Once the counter reaches the programmed limit, the equal_to_window_size flag is asserted, marking the precise termination of the observation window and triggering a state transition to S1. Immediately thereafter, the enable signal is de-asserted, halting the GRO and resetting the counter to zero, while the quiet signal is asserted to isolate the system for stable evaluation in state S2. Following this controlled pause, the sample_en signal is asserted for a single clock cycle in state S3, capturing the final output without interference from ongoing oscillation. Finally, the enable signal is reasserted and a new measurement cycle begins. This waveform sequence validates that the module enforces strict temporal ordering—counting, stopping, evaluating, and sampling—ensuring precise timing control.

2.6. GRO Sampler

The GRO Sampler’s basic idea is that a jittered clock signal samples an oscillatory signal generated by the GRO [14]. Although both signals run at nearly identical frequencies, unavoidable device-level mismatches and timing noise introduce small phase deviations between them. These deviations are critical, since they ensure that sampling events occur at slightly different points of the oscillation cycle, producing inherently uncertain logic outcomes. The D flipflop at the output resolves these asynchronous interactions into discrete digital bits, where the randomness emerges from the timing uncertainty.

At a deeper level, the oscillator is continuously perturbed by both correlated low-frequency flicker noise and uncorrelated thermal noise. These noise components subtly modulate gate delays and propagation paths inside the ring, leading to random variations in the oscillation period over time. As a result, even though the GRO is structurally periodic, its temporal behavior becomes effectively random when observed over time due to these microscopic fluctuations, which are essential for entropy generation.

This module’s interface shown in Figure 25 exposes three control/data inputs and one output. The GRO Oscillation input carries the continuous-time waveform generated by the GRO, representing the entropy source. The CLK input provides the sampling reference, whose edge timing determines when the oscillator state is captured; any jitter or phase noise on this clock directly perturbs the sampling instant. The Reset input enforces deterministic initialization by forcing the internal state of the sampler to a known condition prior to a new acquisition window. The Sampled Oscillation output is the discretized representation of the oscillator at the sampling instants, effectively encoding the instantaneous phase (or voltage level) of the oscillation into a digital waveform suitable for downstream processing. This can be internally designed as shown in Figure 26.

Figure 27 illustrates the interaction between a non-ideal sampling clock and an oscillating signal. The top trace represents a jitter-affected clock, while the middle trace shows the GRO oscillation with a relatively stable amplitude and period. The bottom trace is the sampled output, which changes state only at clock edges. Due to the mismatch between the oscillator period and the jittered sampling instants, each clock edge captures a slightly different phase of the oscillation. When the sampling edge occurs near a transition of the oscillator, small timing perturbations are amplified into different logic decisions, producing irregular pulse widths and non-uniform transitions in the output. Over time, this phase uncertainty accumulates, breaking any fixed phase relationship between the clock and the oscillator. The variability in edge placement and pulse duration of the output directly reflects the underlying timing noise, demonstrating how deterministic oscillation is transformed into entropy through time-domain sampling uncertainty.

2.7. Edge Counter

The Edge Counter counts how many rising transitions occurred during the specified window. In an ideal scenario, the count would be constant. However, in practice it can vary due to timing uncertainty, making this counter useful for observing real signal behavior.

As shown in Figure 28, the sampled oscillation is this module’s input, the signal whose edges are being counted, along with two control signals: enable and reset. When Enable is asserted, the counter begins incrementing on each rising edge of the sampled oscillation. Whenever the enable signal is de-asserted, the counter should stop counting and reset to its initial state so that when the enable signal is high again, the counter begins counting normally. The reset signal provides an explicit way to force the counter back to zero. The output is a multi-bit bus (Counter [9:0]) that holds the current count value, allowing up to 1024 edges to be represented. The gate-level implementation of the counter is identical to that of the enable window module; the differences lie in the clock signal driving the flipflops (illustrated in Figure 29) and the counter width.

The behavior of the module can be observed clearly in Figure 30. At the start, the Enable signal is low, thus the counter remains at zero. Once Enable goes high, the counter begins incrementing on each rising edge of the sampled oscillator signal (shown in blue). By visually counting these rising edges during the enabled period, we find that there are eight transitions, which matches the value produced by the counter. When Enable is de-asserted again, the counter stops and resets, preparing for the next measurement window. The individual counter bits (red waveforms) illustrate the expected binary counting pattern along with its decimal representation, confirming correct operation. Overall, the simulation demonstrates that the module accurately tracks edge events and properly responds to control signals.

2.8. Output Sampling Register

The Output Sampling Register serves as a synchronization and data capture boundary between the asynchronous entropy generation domain (GRO-driven counter) and the synchronous system clock domain. Since the counter is driven by an asynchronous oscillator, its output can change at any time relative to the system clock, leading to metastability if sampled directly. The sampling register solves this by freezing a stable snapshot of the counter value during a controlled enable window [18]. When sample_en is high, the register captures its value on a clock edge, ensuring that all bits correspond to the same instant in time. This guarantees safe transfer into the synchronous domain. Additionally, by capturing the value only once per enable window, the register prevents multiple reads of the same entropy source instance, enforcing proper decimation and avoiding correlation between successive outputs. Its primary role is to provide a clean, single-cycle, metastability-contained representation of the asynchronous counter suitable for digital processing. This module’s interface and internal structure are shown in Figure 31 and Figure 32, respectively.

Figure 33 verifies the functionality of this module. The green bus is the TRNG output, while the pink one is for the counter. At the beginning, the TRNG output holds a previously captured value (0). This highlights an important characteristic: the output is not a live reflection of the counter but a registered value that only updates at specific sampling instants. At the first sampling event (V1), when the sample_en signal goes high, the current counter value (11) is captured and transferred into the synchronous domain. Immediately after this event, the TRNG output updates to 11. Even though the counter continues to run and increments afterward, the output remains fixed at 11. This demonstrates that the design takes a single snapshot of the counter rather than continuously tracking it, ensuring a stable and well-defined value. Between V1 and V2, the counter progresses through multiple values (0, 1, 2, …, 8), but none of these intermediate states affect the output. At the second sampling event (V2), the process repeats: the counter value at that instant (8) is captured, and the output updates accordingly. Overall, the waveform demonstrates a robust mechanism for synchronizing an asynchronous signal, producing stable and discrete outputs that are safe for further digital processing.

3. Proposed TRNG System Integration

The system integration stage brings together all previously developed modules into a unified TRNG architecture and verifies their correct interaction as a whole. The entropy source generates a jittery oscillator signal that feeds the Edge Counter, which accumulates transitions during defined enable windows. The sampling and control logic periodically asserts the enable signal, allowing the counter value to be captured and transferred safely from the asynchronous domain into the synchronous domain through a register stage. This registered output is then held constant until the next sampling event, ensuring a stable and well-defined interface for downstream processing. System-level simulation shown in Figure 34 confirms that the modules operate cohesively: the counter increments only during active windows, resets appropriately between cycles, and the output updates strictly at the intended sampling instants. The observed output values vary from one window to another (8, 10, 13, 11, 15, etc.), indicating the presence of entropy. Additionally, based on the entropy evaluated at each cycle, the window length varies (25, 30, 35, 40, 45 cycles), showing that the system correctly adapts to capture sufficient randomness in each sampling cycle. The blue, pink, and green buses are the decimal representations for the window size, system output, and GRO mode, respectively. The GRO mode remains at zero in this simulation as it will not change unless the window size reaches its maximum bound (6o in this test case). Also, we wanted to test that the system will function correctly whenever the reset signal is asserted, so here the reset is high, around 600 μs, which is why the window size instantly becomes 30 as this is its initial value. Overall, the system exhibits consistent and reliable behavior, validating its readiness for further evaluation and potential hardware implementation.

To sum up, this system architecture features not only a dynamically reconfigurable gated ring oscillator, but also an entropy-aware adaptive sampling window. Unlike prior GRO-TRNGs with fixed oscillator topology and static window lengths, the proposed design actively adapts both the entropy source structure and the entropy extraction during runtime, improving robustness across temperature variations. Figure 35 shows the performance of the proposed TRNG across a wide temperature range (−10 °C to 125 °C). The analog waveforms are the sample_en signal at each temperature; whenever it is asserted, an output is released.

4. Simulation Results

All results reported in this work were obtained through transistor-level simulations using the Cadence Virtuoso/Spectre environment with a 65 nm CMOS process design kit (PDK). The proposed TRNG was evaluated under typical process conditions with a supply voltage of 400 mV and an operating temperature of 27 °C. Transient simulations were conducted to evaluate the functionality and performance of the proposed TRNG, including power consumption, operating frequency, entropy generation, and randomness characteristics.

To validate the effectiveness of the proposed TRNG, the generated bitstream is first subjected to the NIST SP 800-22 statistical test suite. Subsequently, the proposed design is benchmarked against state-of-the-art TRNGs.

4.1. NIST Randomness Test

The NIST SP800-22 statistical test suite is a widely accepted benchmark for evaluating the statistical randomness of binary sequences generated by random number generators. The suite consists of multiple tests, specifically 15, designed to detect different types of non-random behavior, such as bias in the proportion of zeros and ones, repetitive patterns, long runs, periodic structures, and correlations between adjacent bits. Passing these tests provides strong statistical evidence that the generated sequence exhibits the characteristics expected from a random source.

As per the standard, the p-value is defined as the probability (under the null hypothesis of randomness) that the chosen test statistic will assume values that are equal to or worse than the observed test statistic value when considering the null hypothesis. The p-value is frequently called the “tail probability” [19].

The threshold of 0.01 is the standard value specified by NIST. Consequently, all tests with p-values greater than 0.01 are considered successful; a p-value below 0.01 indicates sufficient statistical evidence to reject the null hypothesis of randomness [19].

Table 1. NIST SP800-22A Test Results.

	p-Value	Pass
Frequency (Monobit)	0.73	✓
Frequency Test within a Block	0.51	✓
Runs	0.66	✓
Longest Run of Ones in a Block	0.39	✓
Binary Matrix Rank	0.35	✓
DFT	0.2	✓
Non-overlapping Template Matching	0.03	✓
Serial	0.61	✓
Approximate Entropy	0.55	✓
Cumulative Sums	0.69/0.72	✓

All calculations were performed using the algorithms and formulas documented in [19].

summarizes the results of the NIST SP800-22A statistical test suite performed on the generated random bitstream to evaluate the randomness quality of our proposed TRNG. All evaluated NIST SP800-22 tests were successfully passed, indicating that the generated bitstream exhibits the statistical properties expected from a random source. The successful completion of the Frequency (Monobit) Test confirms that the proportions of zeros and ones are well balanced, while the Frequency Test within a Block demonstrates that this balance is maintained throughout different portions of the sequence. The Runs Test and the Longest Run of Ones in a Block Test indicate that the occurrence and lengths of consecutive zeros and ones are consistent with random behavior, with no evidence of excessively rapid or slow oscillations between bit values.

Furthermore, the Binary Matrix Rank Test results suggest the absence of significant linear dependencies within the generated sequence, whereas the Discrete Fourier Transform Test results confirm that no dominant periodic or repetitive structures are present. The successful result of the Non-overlapping Template Matching Test indicates that specific predefined patterns do not occur more frequently than expected in a random sequence. Similarly, the Serial Test verifies that overlapping bit patterns appear with frequencies close to their theoretical random expectations.

The Approximate Entropy Test results demonstrate a high degree of unpredictability and complexity in the generated bitstream by confirming that the frequencies of adjacent pattern lengths are statistically consistent with randomness. Finally, the Cumulative Sums Test, evaluated in both forward and backward directions, indicates that the cumulative deviations from the expected mean remain within acceptable bounds and do not exhibit systematic bias.

Overall, the combined success of all ten NIST tests provides strong statistical evidence that the proposed TRNG generates unbiased, pattern-free, non-periodic, and statistically independent random sequences.

4.2. Comparative Analysis with State-of-the-Art TRNGs

One of the main contributions of this work is power consumption reduction. At a frequency of 1 MHz, the dynamic power consumption of this proposed system design using LOMOS topology is 0.226 μW, while the static power is 0.211 μW. This power consumption is the lowest compared to previously implemented TRNGs, as shown in

Table 2. Summary of measurement results and a comparison with state-of-the-art 65 nm TRNG designs.

	[6]	[7]	[11]	[20]	[21]	This Work
Technology	65 nm	65 nm	65 nm	65 nm	65 nm	65 nm
Supply (V)	0.9	1.08	1.08	Not reported	0.8	0.4
Entropy Source	Jitter in 3-edge RO	RO (jitter)	Jitter accumulation	Oxide breakdown	SAR residue	GRO (jitter) + metastability
Power (μW)	159	158	289	2000	0.27	0.226
Efficiency (nJ/bit)	0.057	0.0244	0.0355	181.82	0.00022	0.0014
Post Processing	No	Not reported	Not reported	No	No	Yes
NIST Pass	All	2 LSBs pass all tests	3 LSBs pass all tests	All	All	10
Bit Rate (Mb/s)	2.8	6.5	8.2	0.011	1.25	0.165
Area (μm2)	960	702	920	1200	90,000	10,500
Normalized FOM	3.79	1.19	2.25	15,171	1.35	1

. To observe the effectiveness of LOMOS topology, the proposed architecture is tested using CMOS topology. Its dynamic power consumption is 0.8 μW.

Table 2 confirms that our proposed architecture achieves a very low power consumption of only 0.226 μW, which is significantly lower than the referenced designs, where the power ranges from tens of microwatts to several milliwatts. In addition, the proposed architecture demonstrates an outstanding energy efficiency of 0.0014 nJ/bit, outperforming all compared works, which highlights the effectiveness of our architecture. Although the achieved bit rate of 0.165 Mb/s is lower than some high-throughput implementations, the design prioritizes ultra-low-power operation and energy efficiency, making it highly suitable for resource-constrained and battery-powered applications. In terms of silicon area, the proposed design occupies approximately 10,500 μm² (this is an estimated calculation; the gates occupy 5250 μm² and the routing channels occupy the same area as the gates in the worst case), which is moderate compared with other reported implementations and represents a reasonable trade-off considering the achieved low-power operation and strong randomness performance. Overall, the proposed TRNG provides a balanced design with superior energy efficiency, extremely low power consumption, and reliable statistical performance. For fair comparison, FOM is calculated for better evaluation of the trade-offs. FOM = Area × Power/Bit Rate, where Area is in μm², Power is in μW, and the Bit Rate is in Mb/s. Lower FOM means better performance, where the aim is to have less power consumption, less area, and a higher bit rate.

The notation “All” in Table 2 and

Table 3. Summary of measurement results and a comparison with state-of-the-art TRNG designs across different technology nodes.

	[8]	[9]	[10]	[22]	This Work
Technology	45 nm	180 nm	120 nm	130 nm	65 nm
Supply (V)	1.1	Not reported	Not reported	Not reported	0.4
Entropy Source	Metastability	Oscillator jitter	Metastability	Metastability	GRO (jitter) + metastability
Power (μW)	7000	2300	50	1000	0.226
Efficiency (nJ/bit)	0.0029	0.23	0.25	5	0.0014
Post Processing	No	No	Yes	No	Yes
NIST Pass	All	Not reported *	Not reported	5	10
Bit Rate (Mb/s)	2400	10	0.2	0.2	0.165
Area (μm2)	4004	16,000	9000	36,000	10,500
Normalized FOM	0.81	256	156	12,516	1

* The NIST FIPS 140-2 test results are provided, composed of 4 tests only, which is less rigorous than the NIST SP800-22A test.

denotes that the corresponding design successfully passed all NIST SP800-22 statistical tests evaluated by the authors of the referenced work. This typically corresponds to passing all fifteen NIST tests (15/15).

Moreover, the notation “2 LSBs passed all tests” indicates that the two least significant bits were selected as the random output. In other words, the NIST evaluation confirmed that the first two LSBs exhibited the statistical characteristics expected from a random source, while the higher-order bits were not considered sufficiently random and were therefore not used for random number generation. The same applies to the notation “3 LSBs passed all tests”.

Regarding our proposed work, all ten executed tests were successfully passed. The remaining five tests were not performed because they require a substantially longer bitstream, significantly larger memory resources, and greater computational capability than those available in the simulation environment used in this work. These tests often require very large datasets and extensive processing time, making their execution challenging on resource-constrained systems.

Table 3 compares the performance of several TRNGs across different technology nodes. Although the design in [8] achieves a slightly lower FOM value, it is implemented using a more advanced technology node, which naturally provides advantages in power consumption, speed, and area optimization. In contrast, our proposed work is implemented in 65 nm technology and still achieves a comparable FOM, indicating high efficiency despite the larger technology node. If our design were implemented using the same 45 nm technology as [8], the FOM is expected to improve further. This highlights the scalability and effectiveness of our proposed architecture. Furthermore, unlike several previous works that either do not employ post-processing or do not report NIST statistical test results, our proposed TRNG incorporates post-processing to improve randomness quality and successfully passes 10 NIST statistical tests, confirming the reliability and robustness of the generated random sequence.

5. Conclusions

In this paper, a new low-power TRNG is proposed. It converts unavoidable transistor noise into timing jitter using a morphable gated ring oscillator, integrates this jitter using a counter over a controlled window, samples the result, extracts entropy from jitter-dominated bits, and stabilizes operation using a feedback controller. Thus, three new adaptive modules are utilized and integrated together. LOMOS topology is used in the implementation of these modules. These modules are: Morphing GRO (reconfigurable GRO), Lightweight Entropy Monitor, and Adaptive Controller. Together, they introduce a low-power, fully digital, temporally controlled TRNG.

The results show that the proposed TRNG architecture achieves a balanced trade-off between energy efficiency, robustness, and implementation overhead, in contrast to high-throughput but power-intensive designs, such as in [8,9]. Moreover, it adopts a fully digital implementation without any analog components, ensuring scalability, portability, and compatibility with standard-cell synthesis flow, thereby improving upon [10,11]. In addition, it improves statistical uniformity and mitigates entropy degradation compared to single-oscillator designs, as explored in [6,7], by introducing an adaptive windowing mechanism to dynamically adjust the sampling and halting intervals based on real-time entropy estimates.

In order to reduce power consumption, besides optimizing the system design and operating in the subthreshold region, LOMOS topology is very useful and correctly performs its functionality over a wide temperature range. Thus, our proposed architecture achieves the least power consumption, situating itself as the best option for low-power applications such as IoT and wearable devices.