Wang, S.; Ling, Y.; Cai, D.; Zhang, H.; Liu, M.; Cheng, C.; Ding, Q.; Fu, Z.; Zhao, J.; Zhou, H.;
et al. Optimizing Convolutional Operation and Dataflow in FPGA Acceleration of Bayesian Convolutional Neural Network. Electronics 2026, 15, 2603.
https://doi.org/10.3390/electronics15122603
AMA Style
Wang S, Ling Y, Cai D, Zhang H, Liu M, Cheng C, Ding Q, Fu Z, Zhao J, Zhou H,
et al. Optimizing Convolutional Operation and Dataflow in FPGA Acceleration of Bayesian Convolutional Neural Network. Electronics. 2026; 15(12):2603.
https://doi.org/10.3390/electronics15122603
Chicago/Turabian Style
Wang, Shulei, Yun Ling, Daolin Cai, Hao Zhang, Mingxin Liu, Cheng Cheng, Qihang Ding, Zhu Fu, Jiale Zhao, Haoyu Zhou,
and et al. 2026. "Optimizing Convolutional Operation and Dataflow in FPGA Acceleration of Bayesian Convolutional Neural Network" Electronics 15, no. 12: 2603.
https://doi.org/10.3390/electronics15122603
APA Style
Wang, S., Ling, Y., Cai, D., Zhang, H., Liu, M., Cheng, C., Ding, Q., Fu, Z., Zhao, J., Zhou, H., & Zhang, J.
(2026). Optimizing Convolutional Operation and Dataflow in FPGA Acceleration of Bayesian Convolutional Neural Network. Electronics, 15(12), 2603.
https://doi.org/10.3390/electronics15122603
