Composite Anti-Disturbance Control for DC-DC Buck Converters via Self-Evolving Fuzzy Neural Network and Arctangent Super-Twisting Sliding Mode

Abstract

To address the voltage regulation problem of the DC-DC buck converter under multi-source disturbances, this paper proposes a composite anti-disturbance control strategy integrating a Chebyshev-based self-evolving fuzzy neural network (SECFNN) and an arctangent super-twisting sliding mode control (ASTSMC). First, to construct the composite anti-disturbance framework, a load algebraic reconstruction compensator (LARC) is utilized to analytically estimate real-time load dynamics, providing active feedforward compensation for extreme load steps. Second, targeting the unmodeled nonlinearities and parameter uncertainties, the SECFNN is deeply integrated into the control loop. It employs a bidirectional structural learning mechanism—dynamically growing and pruning fuzzy rules—to achieve high-precision adaptive approximation and intelligent compensation. Furthermore, serving as the robust inner-loop core of this composite strategy, the ASTSMC is introduced. By replacing the traditional discontinuous sign function with a continuous arctangent operator, it effectively mitigates sliding mode chattering while ensuring the rapid finite-time convergence of the current tracking error. Ultimately, by synergistically fusing feedforward disturbance rejection (LARC), intelligent nonlinear approximation (SECFNN), and robust tracking (ASTSMC), the proposed strategy significantly reduces transient voltage drops and achieves smoother steady-state performance. Comparative simulation experiments demonstrate the superiority of the proposed method, achieving a rapid startup settling time of 6.5 ms, limiting the maximum transient voltage drop to 15 mV, and completing dynamic reference tracking in 1.2 ms. Furthermore, hardware experimental results confirm its practical engineering feasibility, demonstrating a fast startup of 8.3 ms with zero overshoot, effectively mitigating transient voltage drops during load step changes, and completing dynamic tracking in just 2.2 ms, which verifies its reliable dynamic agility and strong robustness under various test conditions.

1. Introduction

The DC-DC buck converter, serving as a core module in modern power electronic systems, is responsible for regulating power flow and outputting stable low-voltage electric energy [1,2,3,4]. With the growing deployment of data centers, telecommunication infrastructure, and electric vehicles, the demand for reliable power conversion is increasing. During practical operation, the converter faces various lumped disturbances, including external load current steps and internal parameter drifts primarily caused by capacitor aging [5]. For modern digital loads, such as microprocessors and graphics processing units, the core operating voltage is scaling down while the dynamic current demand is rising. Under these operating conditions, transient voltage fluctuations can trigger logic errors or system failures. Therefore, designing a nonlinear controller with proper robustness and fast transient response capability has become an important research focus for enhancing the reliability of power electronic systems.

To address these challenges, linear control strategies, such as PI/PID control [6,7], were widely adopted in early power electronic applications due to their structural simplicity and ease of hardware implementation. However, their control gains are typically designed based on small-signal linearization around a specific nominal operating point. Consequently, their control bandwidth may struggle to meet the dynamic regulation requirements under large-signal disturbances. Subsequently, various nonlinear control algorithms have been introduced, such as sliding mode control (SMC) [8], fuzzy control [9], and backstepping control [10], leveraging their robustness to handle nonlinear dynamics [11]. Meanwhile, observer-based feedforward compensation techniques have been introduced into feedback control loops, such as extended state observers (ESO) [12] and disturbance observers (DOB) [13,14], which estimate and reject load disturbances through feedforward links. Besides sliding modes and observers, Model Predictive Control (MPC) [15] is also a widely studied algorithm [16,17]. However, MPC is constrained by its computational load and dependency on accurate mathematical models, whereas physical parameters exhibit nonlinear drift under varying environmental conditions.

In contrast, utilizing neural networks to estimate unknown nonlinear terms offers practical advantages [18]. Compared with single-layer artificial neural networks [19], Fuzzy Neural Networks (FNN) exhibit higher approximation efficiency because they combine the reasoning capability of fuzzy logic with the learning ability of neural networks [20]. Incorporating Chebyshev orthogonal polynomials into the network can further improve the approximation speed [21,22,23], as their orthogonality helps mitigate the multi-collinearity problem during weight updates. However, for polynomial-based high-dimensional mapping, the network weight parameters can increase rapidly as the expansion order or input dimension grows. This consumes the memory and computational resources of embedded microprocessors, which can lead to algorithmic instability or over-fitting.

Despite the performance improvements offered by the aforementioned methods, some technical challenges remain. Traditional DOBs in industrial applications may misidentify nominal parameter mismatches as external disturbances, leading to over-compensation. Recent Unknown Input Observers (UIO) [24] and ESOs rely on integration and filtering processes; when facing load steps with high slew rates, the estimated trajectories often exhibit phase lag. This lag delays the feedforward action, resulting in initial voltage drops. Furthermore, existing FNNs mostly adopt fixed topological structures, where insufficient nodes limit estimation accuracy, while excessive nodes impose a heavy computational burden within short control periods. As for traditional SMC, its reliance on discontinuous signum functions can cause high-frequency chattering. This chattering increases electromagnetic interference (EMI) and the thermal stress on power switches [25]. To mitigate these effects [26], adaptive SMC strategies were proposed in [27,28], and advanced super-twisting sliding mode techniques have been recently investigated to smooth the control signals [29]. Moreover, the super-twisting algorithm has been successfully integrated with extended state observers and non-singular terminal sliding mode surfaces to effectively suppress chattering and enhance active disturbance rejection in multi-output buck converters [30] and motor drive systems [31]. For instance, reference [32] introduced a method combining terminal sliding mode (TSM) with bounded nonlinear functions. Although TSM offers finite-time convergence, it suffers from the singularity problem, and non-singular variants usually involve a trade-off with convergence speed [33]. More recently, fixed-time non-singular TSMC strategies combined with sliding mode observers have been proposed to effectively handle mismatched uncertainties in buck converters, guaranteeing convergence times strictly independent of initial states [34].

To address these issues, this paper proposes a composite control strategy integrating LARC, SECFNN, and ASTSMC, aiming to improve the voltage regulation accuracy and dynamic response of the buck converter. The originality of this specific composite architecture is reflected in the following aspects: First, the architecture establishes the LARC-SECFNN cooperation. On the one hand, the Load Algebraic Reconstruction Compensator (LARC) utilizes physical circuit equations for algebraic derivation, reducing the reliance on the integration stages of traditional observers to achieve the rapid reconstruction of load disturbances, which effectively weakens the transient disturbances caused by load variations. On the other hand, the Self-Evolving Chebyshev Fuzzy Neural Network (SECFNN) is dedicated to estimating unmodeled internal system dynamics and fitting lumped disturbances. Second, by introducing a bidirectional self-evolving mechanism, the SECFNN dynamically generates or prunes rule nodes based on system residuals, balancing approximation accuracy while effectively avoiding the computational overload typical of traditional fixed networks. Finally, for the inner current loop, an Arctangent Super-Twisting Sliding Mode Control (ASTSMC) is adopted to ensure a continuous control output at the zero-crossing point, suppressing high-frequency chattering while maintaining the robustness of the second-order sliding mode.

To practically verify the engineering feasibility of the proposed complex nonlinear control strategy in resource-constrained systems, and to demonstrate it as a highly efficient embedded implementation strategy, a hardware experimental platform for a 60 V input, 48 V output buck converter is constructed based on an STM32G431RBT6 microcontroller, which is designed for high-frequency digital power supplies. The platform utilizes real MOSFET power devices operating at a switching frequency of 100 kHz, and the tests include large-signal load step conditions from 30 $\Omega$ to 20 $\Omega$. Implementing the control algorithm within a 10 μs period under physical disturbances imposes rigorous requirements on both computational efficiency and real-time disturbance rejection.

The main contributions of this paper are summarized as follows:

• Proposes a physical equation-based load algebraic reconstruction compensator (LARC). It eliminates the phase lag of traditional integral observers, enabling rapid feedforward compensation to mitigate transient voltage undershoots during load steps.
• Develops a self-evolving Chebyshev fuzzy neural network (SECFNN) featuring a bidirectional rule generation and pruning mechanism. It accurately approximates unmodeled dynamics and parameter drifts (e.g., capacitor aging) with low computational cost, enhancing the system’s parameter immunity.
• Designs an arctangent super-twisting sliding mode control (ASTSMC) for the inner loop. It guarantees finite-time convergence and fundamentally eliminates high-frequency chattering, thereby safely reducing the electrical stress on power switches, with global stability proven by Lyapunov theory.

The remainder of this paper is organized as follows: Section 2 establishes the dynamic model of the DC-DC buck converter and formulates the control problem along with the software dual-loop architecture. Section 3 details the design of the composite control law, which encompasses the outer-loop LARC strategy, the SECFNN topology with its evolution mechanism, the inner-loop ASTSMC, and the rigorous global stability analysis. Section 4 presents the comparative simulation results, as well as comprehensive experimental validations. Finally, Section 5 draws the conclusions of this paper.

2. System Description and Dynamic Modeling

2.1. Dynamic Modeling of the DC-DC Buck Converter

As depicted in Figure 1, the topology of the DC-DC synchronous buck converter investigated in this paper consists of a DC input voltage source $V_{in}$, a main power switch $S_1$, a synchronous rectifier switch $S_2$, a filter inductor L, an output filter capacitor C, and a load resistor R. Due to the complementary conduction mechanism of the dual switches, the system consistently operates in the continuous conduction mode (CCM) throughout the entire switching cycle. According to Kirchhoff’s Voltage and Current Laws (KVL/KCL), under ideal parameter conditions, when the main switch $S_1$ is turned on and $S_2$ is turned off (denoted as Mode I in Figure 1), the dynamic differential equations of the system are described as:

$$\left\{\begin{array}{c}L{\displaystyle \frac{d{i}_L}{dt}}=V_{in}-v_o\hfill \\ C{\displaystyle \frac{d{v}_o}{dt}}=i_L-{\displaystyle \frac{v_o}{R}}\hfill \end{array}\right.$$

(1)

Conversely, when the main switch $S_1$ is turned off and $S_2$ is turned on (denoted as Mode II in Figure 1), the dynamic differential equations are:

$$\left\{\begin{array}{c}L{\displaystyle \frac{d{i}_L}{dt}}=-v_o\hfill \\ C{\displaystyle \frac{d{v}_o}{dt}}=i_L-{\displaystyle \frac{v_o}{R}}\hfill \end{array}\right.$$

(2)

Defining the continuous conduction duty cycle of the switches as the control input $u\in [0, 1]$, the state-space averaging method is applied to perform time-weighted averaging of the above two operating modes over a switching period. The ideal continuous large-signal model of the modern buck converter can be derived as:

$$\left\{\begin{array}{c}{\displaystyle \frac{d{i}_L}{dt}}={\displaystyle \frac{V_{in}}{L}}u-{\displaystyle \frac{v_o}{L}}\hfill \\ {\displaystyle \frac{d{v}_o}{dt}}={\displaystyle \frac{i_L}{C}}-{\displaystyle \frac{v_o}{RC}}\hfill \end{array}\right.$$

(3)

To facilitate the subsequent design of the composite anti-disturbance controller, let the desired reference output voltage be $V_{ref}$, and define the voltage tracking error as the first state variable $x_1=v_o-V_{ref}$. Based on the aforementioned large-signal model, the time derivative of the tracking error $x_1$ can be derived as:

$${\dot{x}}_1={\dot{v}}_o-{\dot{V}}_{ref}={\displaystyle \frac{i_L}{C}}-{\displaystyle \frac{v_o}{RC}}-{\dot{V}}_{ref}$$

(4)

Further defining the second state variable as $x_2={\dot{x}}_1$, and utilizing the equivalent relations $v_o=x_1+V_{ref}$ and ${\dot{v}}_o=x_2+{\dot{V}}_{ref}$, the time derivative of $x_2$ can be expanded as:

$${\dot{x}}_2=-{\displaystyle \frac{1}{LC}}(x_1+V_{ref})-{\displaystyle \frac{1}{RC}}(x_2+{\dot{V}}_{ref})-{\ddot{V}}_{ref}+{\displaystyle \frac{V_{in}}{LC}}u$$

(5)

In practical engineering applications, the operating environment of data center power supplies is often harsh. The load resistance is typically unknown and prone to severe sudden changes. Simultaneously, the values of the input voltage, filter capacitor, and inductor will deviate from their nominal values due to temperature drift and component aging. Considering these parameter uncertainties and unmodeled external disturbances, the actual dynamic equation for $x_2$ should be rewritten as:

$${\dot{x}}_2=-{\displaystyle \frac{x_1+V_{ref}}{(L_0+\Delta L)(C_0+\Delta C)}}-{\displaystyle \frac{x_2+{\dot{V}}_{ref}}{(R_0+\Delta R)(C_0+\Delta C)}}-{\ddot{V}}_{ref}+{\displaystyle \frac{V_{in0}+\Delta V_{in}}{(L_0+\Delta L)(C_0+\Delta C)}}u+d\left(t\right)$$

(6)

where $L_0, C_0, R_0$, and $V_{in0}$ represent the known nominal values of the inductor, capacitor, resistor, and input voltage, respectively; $\Delta L, \Delta C, \Delta R$, and $\Delta V_{in}$ represent the unknown perturbation amounts of the corresponding physical parameters; and $d\left(t\right)$ denotes unknown bounded external disturbances (such as high-frequency electromagnetic interference or unmodeled high-order parasitic dynamics).

To decouple the control law design from unknown disturbances, algebraic transformations are used to separate the nominal and uncertain terms, restructuring the equation as:

$${\dot{x}}_2=-{\displaystyle \frac{1}{L_0{C}_0}}(x_1+V_{ref})-{\displaystyle \frac{1}{R_0{C}_0}}(x_2+{\dot{V}}_{ref})-{\ddot{V}}_{ref}+{\displaystyle \frac{V_{in0}}{L_0{C}_0}}u+q\left(t\right)$$

(7)

where the lumped disturbance $q\left(t\right)$ encompasses the sum of all perturbations caused by system nonlinear parameter drifts and external environmental changes:

$$q\left(t\right)=\left({\displaystyle \frac{1}{L_0{C}_0}}-{\displaystyle \frac{1}{LC}}\right)(x_1+V_{ref})+\left({\displaystyle \frac{1}{R_0{C}_0}}-{\displaystyle \frac{1}{RC}}\right)(x_2+{\dot{V}}_{ref})+\left({\displaystyle \frac{V_{in}}{LC}}-{\displaystyle \frac{V_{in0}}{L_0{C}_0}}\right)u+d\left(t\right)$$

(8)

For simplicity, the completely known nominal composite nonlinear physical model in the ${\dot{x}}_2$ dynamics is defined as $f\left(x\right)$:

$$f\left(x\right)=-{\displaystyle \frac{1}{L_0{C}_0}}(x_1+V_{ref})-{\displaystyle \frac{1}{R_0{C}_0}}(x_2+{\dot{V}}_{ref})-{\ddot{V}}_{ref}$$

(9)

and the known control gain is defined as $b_0={\displaystyle \frac{V_{in0}}{L_0{C}_0}}$. Thus, the dynamic model of the buck converter with severe uncertainties is finally transformed into a standard strict-feedback state-space form:

$$\left\{\begin{array}{c}{\dot{x}}_1=x_2\hfill \\ {\dot{x}}_2=f\left(x\right)+b_{0}u+q\left(t\right)\hfill \end{array}\right.$$

(10)

Remark 1.

It should be noted that in actual power electronic systems, due to the energy limits of physical devices and the inertial effects of parasitic parameters, the external lumped disturbance $q\left(t\right)$ and its first derivative are typically bounded. Therefore, in the subsequent control design and stability analysis, it is reasonably assumed that there exist unknown positive constants ${\rho }_1$ and ${\rho }_2$ such that $\left|q\left(t\right)\right|\le {\rho }_1$ and $|\dot{q}\left(t\right)|\le {\rho }_2$. This physical constraint provides a rigorous objective basis for the convergence of the closed-loop system.

Based on this strict-feedback model, the core control objective of the subsequent work in this paper is to design a cascaded composite anti-disturbance controller combining feedforward estimation technology and self-organizing intelligent approximation technology to reconstruct and compensate for the unknown lumped disturbance $q\left(t\right)$ online. While effectively overcoming nonlinear parameter mismatches, it ensures that the control input u is free from high-frequency chattering, thereby driving the state trajectory $(x_1, x_2)$ of the closed-loop system to converge rapidly and asymptotically to the equilibrium origin $(0, 0)$, achieving high-precision robust tracking of the output voltage $v_o$ to the reference command $V_{ref}$.

2.2. Software Dual-Loop Control Architecture

To achieve precise voltage regulation against severe lumped disturbances, a software-based composite dual-loop control architecture is proposed. The overall block diagram of the proposed composite LARC-SECFNN-ASTSMC control strategy is visually summarized in Figure 2. Macroscopically, the outer voltage loop is responsible for generating the reference current command $i_{ref}$, while the inner current loop ensures the actual inductor current $i_L$ rapidly tracks $i_{ref}$.

In the conventional dual-loop structure, the outer loop primarily relies on a baseline Proportional–Integral (PI) controller to synthesize the base current:

$$i_{PI}\left(t\right)=K_{pv}{e}_v\left(t\right)+K_{iv}\int e_v\left(\tau \right)d\tau$$

(11)

The baseline parameters $K_{pv}$ and $K_{iv}$ are systematically determined using the closed-loop pole placement method. By mapping the outer-loop dynamics to a standard second-order system and setting the damping ratio to the optimal engineering value of 0.707, the transient overshoot is minimized while ensuring rapid convergence, referring to the parameter design principles in [35].

However, pure PI control lacks the bandwidth to handle extreme transient load steps and non-linear parameter drifts. Furthermore, according to recent advancements in cascaded converter control [36,37], ensuring global closed-loop stability dictates a strict time-scale (or bandwidth) separation between the nested loops. To effectively avoid dynamic loop interactions, the inner current loop must possess an extremely high bandwidth to act as a nearly instantaneous controlled current source. Conversely, to strictly guarantee stability, the outer voltage loop must be deliberately designed with a significantly lower bandwidth. Applying highly aggressive nonlinear algorithms to both loops makes it extremely difficult to maintain this necessary order-of-magnitude bandwidth separation. Therefore, this paper introduces a synergistic compensation mechanism for the low-bandwidth outer loop, where the total virtual current reference is reconstructed by superimposing the feedforward and compensation terms:

$$i_{ref}\left(t\right)=i_{PI}\left(t\right)+i_{LARC}\left(t\right)+i_{SECFNN}\left(t\right)$$

(12)

Here, the Load Algebraic Reconstruction Compensator (LARC) is utilized to provide low-delay feedforward compensation for external load steps ($i_{LARC}$), while the Self-Evolving Chebyshev Fuzzy Neural Network (SECFNN) is embedded to fit the unknown system terms through fuzzy estimation ($i_{SECFNN}$).

In the inner current loop, to enforce the tracking of the composite reference $i_{ref}$ while suppressing the chattering phenomenon inherent in conventional sliding mode control, an Arctangent Super-Twisting Sliding Mode Control (ASTSMC) is adopted as the robust execution law. This macroscopic composite architecture will undergo rigorous algorithmic synthesis and global stability proof in Section 3.

3. Composite Control Law Design and Stability Analysis

This section details the rigorous algorithmic synthesis of the advanced outer-loop compensation terms and the inner-loop robust execution law. Under complex operating conditions, a single compensation mechanism often struggles to balance large-signal transient response speed and steady-state tracking accuracy. Traditional observers inherently introduce phase lag during filtering, whereas fixed-structure neural networks suffer from the dilemma of balancing computational burden and approximation precision.

Therefore, a heterogeneous synergistic compensation architecture is proposed in this paper: on the one hand, the Load Algebraic Reconstruction Compensator (LARC) is utilized to rapidly reconstruct the load current from the physical model level to suppress macroscopic external step disturbances; on the other hand, the nonlinear mapping capability of the Self-Evolving Chebyshev Fuzzy Neural Network (SECFNN) is employed to perform fuzzy estimation of internal parameter drifts and microscopic unmodeled dynamics. Their synergistic interaction comprehensively reshapes the reference current command, which is subsequently tracked by the continuous super-twisting inner loop.

3.1. Load Algebraic Reconstruction Compensator (LARC) Design

According to the nodal current dynamic characteristics of the output filter capacitor branch, the current flowing through the capacitor equals the difference between the inductor current and the load current. Defining the voltage tracking error as $e_v=V_{ref}-v_o$, and noting that the derivative of the constant reference voltage ${\dot{V}}_{ref}$ is zero, the theoretical raw estimated value of the unknown load current $i_{\mathrm{load}\_\mathrm{raw}}$ can be algebraically reconstructed using the mechanism model as:

$$i_{\mathrm{load}\_\mathrm{raw}}\left(t\right)=i_L\left(t\right)+C{\dot{e}}_v\left(t\right)$$

(13)

The primary advantage of algebraic reconstruction over conventional Luenberger observers or Extended State Observers (ESO) lies in its mathematical directness. Traditional observers rely on integrating the estimation error, which inherently acts as a low-pass filter and unavoidably introduces phase delay during rapid load steps. By directly utilizing the measurable states, the LARC eliminates this integration-induced lag, granting the system an exceptionally high dynamic estimation bandwidth.

Specifically, under steady-state conditions (${\dot{e}}_v=0$), the nominal capacitance term mathematically vanishes, granting LARC theoretical immunity to capacitance inaccuracies. Conversely, during transients where the actual capacitance is degraded due to aging ($C_{real}<C_{nom}$), the LARC produces a slightly larger feedforward current based on the nominal $C_{nom}$, which physically acts as a transient over-compensation to accelerate voltage recovery.

However, directly applying the derivative term ${\dot{e}}_v\left(t\right)$ in a physical control system would heavily amplify high-frequency PWM switching noise and sensor measurement noise. Thus, a second-order lead-lag composite filtering structure $G_{LARC}\left(s\right)={\displaystyle \frac{{\tau }_{in}s+1}{{\tau }_{LARC}s+1}}$ is constructed. Its physical significance is strictly decoupled into two aspects: the lag element (${\tau }_{LARC}$) acts as a strict low-pass boundary to attenuate high-frequency switching ripple, while the lead characteristic (${\tau }_{in}$) provides positive phase shifts to proactively compensate for the calculation delay of the digital microprocessor and the hardware sampling latency within the control bandwidth.

To execute this algorithm in an embedded digital signal processor (DSP), the Backward Euler method is adopted for precise discretization mapping. Assuming the sampling period is $T_s$, the discrete iterative evolution law implemented in the microcontroller is derived as:

$$\left\{\begin{array}{c}{z}_3\left[k\right]={\displaystyle \frac{1}{1-A_{LARC}{T}_s}}{z}_3[k-1]+{\displaystyle \frac{T_s{B}_{LARC}}{1-A_{LARC}{T}_s}}{i}_{\mathrm{load}\_\mathrm{raw}}\left[k\right],\hfill \\ i_{LARC}\left[k\right]=C_{LARC}{z}_3\left[k\right]+D_{LARC}{i}_{\mathrm{load}\_\mathrm{raw}}\left[k\right]\hfill \end{array}\right.$$

(14)

where $A_{LARC}, B_{LARC}, C_{LARC}$, and $D_{LARC}$ are the corresponding state-space matrices of the continuous filter $G_{LARC}\left(s\right)$.

Remark 2.

Noise Suppression Mechanism in LARC Implementation.

In practical digital power supplies, utilizing the pure derivative of the voltage error (${\dot{e}}_v$) is inherently sensitive to high-frequency disturbances, such as PWM switching ripple and ADC quantization noise. To ensure robust engineering feasibility, a multi-stage noise suppression mechanism is integrated into the proposed architecture. First, at the data acquisition layer, the raw voltage signals are processed through hardware RC low-pass filters. Second, at the algorithmic layer, the LARC does not employ a pure differentiator; instead, the transfer function $G_{LARC}\left(s\right)$ serves as a practical differentiator where the pole $1/{\tau }_{LARC}$ acts as a strict low-pass boundary to aggressively attenuate high-frequency noise amplification. Finally, at the physical layer, while minor residual high-frequency chattering may persist in the LARC output command ($i_{LARC}$), it does not degrade the actual voltage quality. This is because $i_{LARC}$ merely constitutes the virtual current reference. The physical filter inductor (L) inherently functions as a massive low-pass filter. Synergized with the continuous arctangent smoothing action of the ASTSMC inner loop, this residual high-frequency command ripple is physically dampened, guaranteeing clean and stable voltage regulation (e.g., restricting the high-frequency noise in the output voltage to a peak-to-peak value of approximately 0.2 V).

3.2. Self-Evolving Chebyshev Fuzzy Neural Network (SECFNN)

Although LARC rapidly compensates for macroscopic external loads, internal parameter drifts caused by component aging and continuous temperature variations still compromise the steady-state accuracy. To intelligently fit these lumped uncertainties $f\left(X\right)$ through fuzzy estimation without requiring an accurate mathematical plant, a 6-layer SECFNN feedforward topology is proposed.

3.2.1. Forward Propagation and Chebyshev Mapping

Defining the network input state vector as $X={[e_v, {\dot{e}}_v]}^T$, the input variables are first transmitted and fuzzified using Gaussian basis functions. The firing strength for the i-th input in the j-th rule is:

$$O_{ij}^{\left(2\right)}=exp\left(-{\displaystyle \frac{{(O_i^{\left(1\right)}-c_{ij})}^2}{{\sigma }_{ij}^2}}\right),j=1, 2,\dots ,N$$

(15)

Subsequently, the original firing strength of each rule is deduced using the product inference operator, and an infinitesimal constant ${ϵ}_0$ is added to prevent computational singularity during subsequent normalization:

$$O_j^{\left(3\right)}={\displaystyle \prod _{i=1}^2}{O}_{ij}^{\left(2\right)}+{ϵ}_0$$

(16)

To enhance the nonlinear fitting capability and alleviate the multicollinearity problem associated with traditional polynomial expansions, Chebyshev orthogonal polynomials $T_m(·)$ are introduced to perform high-dimensional spatial mapping of the inputs. The expansion follows a strict recurrence relation:

$$T_0\left(x\right)=1,T_1\left(x\right)=x,T_{m+1}\left(x\right)=2x{T}_m\left(x\right)-T_{m-1}\left(x\right)$$

(17)

Besides their strict orthogonality, Chebyshev polynomials are bounded within $[-1, 1]$. This crucial property inherently prevents numerical overflow in 32-bit embedded DSPs during high-order expansions, ensuring the algorithmic stability of the neural network. Finally, the normalized firing strengths and the Chebyshev expansion terms are weighted and fused. The estimated current output of the network is synthesized in a compact vector inner product form:

$$i_{SECFNN}={\widehat{W}}^T\Phi \left(X\right)$$

(18)

where $\widehat{W}$ represents the adaptive weight vector, and $\Phi \left(X\right)$ denotes the multidimensional joint basis vector. The corresponding internal architecture and layer-by-layer signal propagation of the proposed SECFNN are illustrated in Figure 3.

3.2.2. Bidirectional Topological Evolution Mechanism

To address the parameter space exponential expansion and computational overload issues inherent in traditional fixed-topology networks, an adaptive topology evolution mechanism based on the dynamic evaluation of spatiotemporal features is proposed. As specifically illustrated in the algorithmic flowchart in Figure 4, the real-time execution logic of the SECFNN operates through a continuous, self-organizing loop.

Following the initial Initialization and the real-time Input Processing & Fuzzification, the algorithm enters the core decision-making phase of Self-Organizing Topology Evolution. This bidirectional mechanism dynamically manages the network structure through two complementary criteria:

(1) Rule Generation (Growth): To capture sudden large-signal transients, the Euclidean distance $d_{min}={\min }_{1\le j\le N}\parallel X-C_j\parallel$ between the current input X and all existing rule centers is continuously evaluated. A new candidate rule is immediately generated if $d_{min}$ exceeds a predefined spatial threshold $d_{th}$, indicating that the current operating point has entered an unmapped domain. This threshold dictates the structural resolution of the fuzzy partition.

(2) Rule Pruning (Decay): To limit the parameter scale and release microprocessor memory, the algorithm tracks an importance factor $I_j$ for each rule in real time by introducing a forgetting factor $\rho \in (0, 1)$:

$$I_j\left(k\right)=\rho I_j(k-1)+O_j^{\left(3\right)}\left(k\right)$$

(19)

Whenever $I_j\left(k\right)$ drops below a specified threshold $I_{th}$, it implies that the corresponding rule has rarely been activated recently. This inactive candidate rule is pruned, ensuring the computational complexity remains strictly bounded within the 10 μs control cycle.

Remark 3.

To ensure structural stability in noisy environments and prevent “structural chattering,” the SECFNN incorporates a time-window constraint. A newly generated rule is granted a survival period during which pruning is prohibited. Furthermore, the importance factor $I_j$ is calculated cumulatively, functioning as a numerical low-pass filter that prevents high-frequency noise from triggering premature rule deletions. These measures, combined with smooth weight initialization, guarantee the continuity of the control signal $i_{\mathit{SECFNN}}$ during topological evolution.

As depicted in the flowchart, if the evolutionary criteria are met (Yes), the algorithm generates or prunes candidate rules to restructure the topology; if not (No), it bypasses the structural change. Subsequently, the algorithm proceeds to Network Inference & Synthesis based on the updated or existing rule base. After yielding the control output, Parameter Learning & Update is executed to continuously tune the network weights. Finally, a Termination Check determines whether the process ends or loops back for the next digital control cycle.

3.3. Arctangent Super-Twisting Sliding Mode Control (ASTSMC) for Inner Loop

After constructing the comprehensively compensated composite reference command $i_{ref}$, a highly robust inner-loop control law is required to force the actual inductor current $i_L$ to track it. The global current tracking sliding surface is directly defined as the tracking error:

$$s=i_{ref}-i_L=(i_{PI}+i_{LARC}+i_{SECFNN})-i_L$$

(20)

Taking the time derivative of the sliding surface and substituting the nominal inductor physical dynamics of the Buck converter $L_n{\dot{i}}_L=V_{in}u-v_o$, the sliding mode evolution equation of the system is obtained:

$$\dot{s}={\dot{i}}_{ref}-{\displaystyle \frac{V_{in}}{L_n}}u+{\displaystyle \frac{v_o}{L_n}}$$

(21)

Based on the design principle of separating equivalent control and switching control, the total control law can be decomposed as $u=u_{eq}+u_{sw}$. Setting $\dot{s}=0$, the equivalent feedforward control law $u_{eq}$ aimed at canceling the nominal system dynamics is strictly designed as:

$$u_{eq}={\displaystyle \frac{L_n}{V_{in}}}\left({\dot{i}}_{ref}+{\displaystyle \frac{v_o}{L_n}}\right)$$

(22)

For the switching control law $u_{sw}$, although the traditional Super-Twisting Algorithm (STA) shifts the discontinuous switching term into the integral action, the signum function $\mathrm{sgn}\left(s\right)$ contained in its proportional term still causes high-frequency severe jumps near the sliding surface. To effectively suppress this high-frequency chattering and relieve the electrical stress on power switches, a continuously differentiable arctangent operator $\arctan \left(\alpha s\right)$ is introduced to replace the signum function.

Its core mathematical and physical mechanism is as follows: The coefficient $\alpha >0$ regulates the steepness of the boundary layer. When far from the sliding surface (large $\left|s\right|$), ${\lim }_{\left|s\right|\to \infty }\arctan \left(\alpha s\right)=(\pi /2)\mathrm{sgn}\left(s\right)$. This exhibits saturation characteristics similar to the signum function, ensuring the controller maintains the strong non-linear reaching capability required for large-signal transients. Conversely, near the sliding surface ($s\to 0$), the Taylor expansion yields $\arctan \left(\alpha s\right)\approx \alpha s$. The controller seamlessly and naturally transitions into a high-gain linear damping mode. This progressive blending eliminates the hard switching inherent in sliding mode, dynamically dampening potential LC resonances. Consequently, the designed Arctangent Super-Twisting (ASTSMC) switching control law $u_{sw}$ is formulated as:

$$\left\{\begin{array}{c}{u}_{sw}=K_p{\left|s\right|}^{1/2}\arctan \left(\alpha s\right)+w\hfill \\ \dot{w}=K_i\arctan \left(\alpha s\right)\hfill \end{array}\right.$$

(23)

where $K_p$ and $K_i$ are the positive robust gains. Combining the equivalent control and switching control, the overall composite control execution law sent to the PWM modulator is:

$$u={\displaystyle \frac{L_n}{V_{in}}}\left({\dot{i}}_{ref}+{\displaystyle \frac{v_o}{L_n}}\right)+K_p{\left|s\right|}^{1/2}\arctan \left(\alpha s\right)+\int K_i\arctan \left(\alpha s\right)dt$$

(24)

3.3.1. Optimization of the Steepness Coefficient $\alpha$

The steepness coefficient $\alpha$ dictates the fundamental trade-off between maximizing the non-linear reaching speed and suppressing discrete-time chattering. To optimize $\alpha$, its theoretical bounds are established based on the system’s disturbance rejection requirements and hardware sampling constraints.

Given the established experimental parameters ($V_{in}=60\mathrm{V}$, $L=0.5\mathrm{mH}$, the robust gain $K_p=0.25$, and the microcontroller sampling period $T_s=10\mathsf{\mu }\mathrm{s}$), we aim to restrict the steady-state tracking error within a band of ${ϵ}_s=0.01\mathrm{A}$. First, to overcome the maximum residual disturbance $M_{eq}$ within this prescribed error band, the generalized reaching condition $s\dot{s}<0$ dictates that the control effort must provide a sufficient non-linear restoring force. By evaluating the local gradient, this establishes the theoretical lower bound:

$$\alpha >{\displaystyle \frac{1}{{ϵ}_s}}\tan \left({\displaystyle \frac{L·M_{eq}}{V_{in}{K}_p\sqrt{{ϵ}_s}}}\right)\approx 0.33$$

(25)

Second, $\alpha$ cannot be infinitely large. Inspired by the discrete sliding mode stability analysis in [26], the discrete-time state trajectory must maintain monotonic convergence to avoid zero-crossing chattering. This requires the local derivative to strictly satisfy the discrete-time non-overshoot condition:

$$1-T_s{\left|{\displaystyle \frac{\partial \dot{s}}{\partial s}}\right|}_{s={ϵ}_s}>0\Rightarrow \alpha <23.5$$

(26)

By synthesizing these physical and algorithmic constraints, the feasible optimization interval is evaluated as $0.33<\alpha <23.5$. In this study, $\alpha =2.0$ is selected, which ensures a transient response while preventing high-frequency digital chattering.

3.3.2. Analytical Interconnection Between Convergence Time and Steady-State Error

In the proposed ASTSMC framework, the transient response speed and ultimate steady-state precision are interconnected through the residual lumped disturbance $M_{eq}$. To quantify this inherent trade-off, the maximum convergence time for the state to reach the equilibrium neighborhood is first defined via Lyapunov finite-time theory as $T_{max}\approx {\displaystyle \frac{\pi }{2\alpha \sqrt{K_i{K}_p}}}$, where $K_p$ and $K_i$ represent the robust gains.

Concurrently, as the system enters the steady-state phase ($s\to 0$), it must counteract the residual disturbance $M_{eq}$ persisting after compensation. By utilizing the linear approximation $\arctan \left(\alpha s\right)\approx \alpha s$ near the origin, the steady-state error upper bound is derived as ${ϵ}_{ss}\le {\displaystyle \frac{1}{\alpha }}\tan \left({\displaystyle \frac{\pi ·M_{eq}}{2K_i}}\right)$.

By eliminating the intermediate shape parameter $\alpha$ from these two analytical expressions, a direct coupling equation representing the proportional relationship between response speed and precision is established:

$${\displaystyle \frac{{ϵ}_{ss}}{T_{max}}}={\displaystyle \frac{2\sqrt{K_i{K}_p}}{\pi }}\tan \left({\displaystyle \frac{\pi ·M_{eq}}{2K_i}}\right)$$

(27)

Equation (27) reveals the physical essence of the system’s performance boundary: the proportional relationship between the convergence time and the steady-state error is strictly governed by the magnitude of the residual lumped disturbance $M_{eq}$. A larger $M_{eq}$ results in an increase in this ratio, thereby necessitating a trade-off between the convergence speed and the steady-state accuracy. Conversely, a reduction in the residual disturbance intensity mathematically shrinks the value of the tangent term, compressing the analytical coupling ratio.

3.3.3. Global Closed-Loop Composite Stability Analysis

To analyze the stability of the cascaded dual-loop architecture, the mathematical proof sequentially evaluates the inner-loop practical finite-time reaching phase and the outer-loop ultimate bounded behavior in a unified framework.

First, focusing on the inner-loop practical finite-time convergence, the current tracking error dynamics driven by the ASTSMC law can be formulated as $\dot{s}=D_{in}\left(t\right)-b_0{K}_p{\left|s\right|}^{1/2}\arctan \left(\alpha s\right)-b_0\int K_i\arctan \left(\alpha s\right)dt$, where $D_{in}\left(t\right)$ represents bounded inner-loop lumped perturbations. Unlike the standard discontinuous signum function, the continuous arctangent operator smooths the control action around the origin. According to the stability analysis of continuous super-twisting algorithms [38,39], this robust mechanism achieves practical finite-time convergence. Specifically, by selecting a sufficiently large steepness factor $\alpha$ and robust gains $K_p, K_i$, the inner-loop sliding surface s converges to a residual neighborhood $\left|s\right|\le \delta$ within a finite time $t_r$.

Second, to evaluate the outer-loop ultimate boundedness based on the inner-loop convergence, we proceed to formulate the composite positive-definite Lyapunov candidate function for the outer voltage loop and the observer:

$$V_{outer}={\displaystyle \frac{1}{2}}{s}_v^2+{\displaystyle \frac{1}{2\gamma }}{\tilde{W}}^T\tilde{W}+{\displaystyle \frac{1}{2}}{e}_{obs}^2$$

(28)

Driven by the PI-based virtual current reference $i_{ref}$, the closed-loop tracking error dynamics inherently contain a stabilizing linear proportional feedback term $-k_v{s}_v$. According to the Universal Approximation Theorem, by substituting the SECFNN compensation ${\widehat{W}}^T\Phi \left(X\right)$ and the LARC observer outputs, the time derivative of the generalized outer-loop sliding surface $s_v$ satisfies:

$${\dot{s}}_v=-k_v{s}_v+{\beta }_v{\tilde{W}}^T\Phi \left(X\right)+{\epsilon }_0+{\tilde{d}}_{\mathrm{LARC}}+{\Delta }_s$$

(29)

where ${\beta }_v>0$ is a scaling factor, ${\epsilon }_0$ is the inherent approximation error of the neural network, ${\tilde{d}}_{\mathrm{LARC}}$ is the bounded observation error of the observer, and ${\Delta }_s=-c_{v}s$ represents the cross-coupling perturbation originating from the inner-loop current tracking error.

Noting that the ideal optimal weight $W^{\ast }$ is a constant vector (yielding $\dot{\tilde{W}}=-\dot{\widehat{W}}$), and substituting the proposed adaptive update law $\dot{\widehat{W}}=\gamma {\beta }_v{s}_v\Phi \left(X\right)$, the network weight error terms are canceled out. Consequently, applying the absolute value inequalities, the time derivative of the Lyapunov function becomes:

$${\dot{V}}_{outer}\le -k_v{s}_v^2+|s_v|D_{out}+|s_v\left|\right|{\Delta }_s|-{\lambda }_o{e}_{obs}^2$$

(30)

where $D_{out}\ge |{\epsilon }_0+{\tilde{d}}_{\mathrm{LARC}}|$ denotes the strict upper bound of the residual lumped disturbances, and ${\lambda }_o>0$ ensures the convergence of the LARC error states.

Once the inner loop converges to the practical sliding manifold ($t\ge t_r$), the aforementioned coupling perturbation is restricted by $|{\Delta }_s|\le c_v\delta$. The Lyapunov derivative subsequently reduces to:

$${\dot{V}}_{outer}\le -k_v{s}_v^2+\left|s_v\right|(D_{out}+c_v\delta )-{\lambda }_o{e}_{obs}^2$$

(31)

By appropriately designing the baseline proportional tracking gain such that $k_v>0$, the negative quadratic term $-k_v{s}_v^2$ will mathematically dominate the linear perturbation term $|s_v|(D_{out}+c_v\delta )$ outside a compact boundary defined by $|s_v|>(D_{out}+c_v\delta )/k_v$. This demonstrates that ${\dot{V}}_{outer}<0$ strictly holds outside a specific compact residual set around the origin.

Therefore, all signals operating within the closed-loop cascaded system are confined within this compact set. The interconnected composite system is proven to be Semi-Globally Uniformly Ultimately Bounded (SGUUB) [40], ensuring stable voltage tracking performance even under parameter uncertainties.

4. Simulation and Experimental Validation

4.1. Simulation Analysis

To verify the effectiveness and superiority of the proposed composite control strategy for the DC-DC buck converter, a high-fidelity simulation model is established in the MATLAB/Simulink 2024b environment, as depicted in Figure 5. The comprehensive simulation architecture is primarily composed of three sections: the physical circuit model of the buck converter power stage, the embedded discrete “Buck Controller” block, and the dynamic command generators. To rigorously emulate the computational behavior, sampling delays, and zero-order hold (ZOH) effects of an actual digital signal processor (DSP), the control algorithm is executed using a fixed-step discrete solver (Euler method) with a fundamental sample time of $T_s=10$ μs (strictly corresponding to the 100 kHz switching frequency).

To highlight the performance gains and validate the structural rationality of the proposed architecture, four comparative configurations are implemented. These include a standard baseline, an ablation study, and two state-of-the-art intelligent strategies: (1) PI Control: The traditional linear proportional–integral feedback baseline. (2) PI + LARC + SECFNN: An ablation configuration that replaces the proposed ASTSMC inner loop with a traditional PI current loop, explicitly designed to verify the necessity of the robust sliding mode execution law. (3) NFTSMC-SOCFNN: Non-singular Fast Terminal Sliding Mode Control with Self-Organizing Cascade Fuzzy Neural Network. (4) STSMC-SERCFNN: Super-Twisting Sliding Mode Control with Self-Evolving Recurrent Chebyshev Fuzzy Neural Network.

The system is evaluated under four rigorous scenarios closely related to practical industrial applications: startup transient response, dynamic disturbance rejection under abrupt load variations, dynamic reference voltage tracking, and robustness evaluation under parameter uncertainties. The nominal physical parameters of the converter used in this study are summarized in

Table 1. Buck Converter Nominal Parameters.

Description	Parameter	Value	Units
Input voltage	$V_{in}$	60	V
Reference voltage	$V_{ref}$	48	V
Inductor	L	0.5	mH
Capacitor	C	1000	μF
Load resistance	R	30	$\Omega$
Switching frequency	$f_{sw}$	100	kHz

.

To ensure a rigorous and objective evaluation, the tuning procedure for all comparative controllers is strictly governed by uniform performance criteria and physical constraints. First, the fairness condition dictates that all controllers are executed under the exact same discrete-time environment (sampling period $T_s=10\mathsf{\mu }\mathrm{s}$) and identical hardware parameters. Each controller is individually fine-tuned to its respective Pareto-optimal frontier before the comparison. Second, regarding saturation and hardware safety limits, the final control command (duty cycle u) for all algorithms is strictly bounded within the operational limit of $[0, 0.95]$ to prevent integral windup. Simultaneously, based on practical current demands and hardware protection, a threshold current limit of 8 A is established to prevent overcurrent damage. Third, to comply with control signal constraints and protect the MOSFETs from severe thermal stress, the discontinuous switching gains of the comparative sliding mode controllers are constrained so that the high-frequency control chattering does not exceed 5% of the nominal duty cycle. Finally, the performance criterion for parameter optimization is guided by minimizing the Integral Time Absolute Error (ITAE) of the voltage tracking, striking the best possible balance between rapid transient response and steady-state ripple suppression. The specific optimal gain values for all evaluated controllers, which perfectly match the digital C-code implementation in the microcontroller, are detailed in

Table 2. Detailed Control Parameters of Evaluated Controllers.

Controller	Parameters and Values/Symbols
Proposed Strategy	Outer (PI): $K_{pv}=120.0, K_{iv}=3000.0$ Outer (LARC): ${\tau }_{in}=20\mathsf{\mu }\mathrm{s}, {\tau }_{LARC}\approx 53\mathsf{\mu }\mathrm{s}$ Outer (SECFNN): $N_{init}=2, N_{max}=30$, Dimension $=3$    Thresholds: $d_{th}=0.6, I_{th}=0.05$, Factor $\rho =0.995$    Learning rate: ${\eta }_{nn}=5.0$ Inner (ASTSMC): $K_{p,in}=30.0, K_{i,in}=6000.0, \alpha =2.0$
NFTSMC-SOCFNN	Sliding: ${\sigma }_1=11/9, {\sigma }_2=5/3, k_1=200, k_2=0.1$ Reaching: ${\lambda }_1=6\times {10}^5, {\lambda }_2=4\times {10}^5$
STSMC-SERCFNN	Sliding: $\lambda =100, k_1=0.05, k_2=30.0$ SECFNN: $D_{th}=0.5, {\rho }_I=0.99$
PI Control	Outer: $K_{pv}=120.0, K_{iv}=3000.0$

.

4.1.1. Startup Transient Process Analysis

The startup test evaluates the system’s capability to safely establish the target 48 V output from an unpowered state ($t=0$ s). During this phase, it is critical to supply a large initial charging current to the output filter capacitor while suppressing destructive voltage overshoots. Figure 6 displays the comparative trajectories. The traditional PI controller displays typical linear feedback limitations, exhibiting a sluggish settling time of 19.0 ms and suffering from a residual 20 mV steady-state error due to its limited gain bandwidth. In contrast, the other four controllers utilize intelligent feedforward or neural network mechanisms to successfully eliminate steady-state errors and high-voltage spikes.

However, a distinct performance gap exists in their convergence speeds. NFTSMC-SOCFNN and STSMC-SERCFNN exhibit a relatively slow, overdamped rise, requiring 12.0 ms and 10.0 ms, respectively, to settle. This latency is primarily due to the conservative sliding gains required to avoid severe initial chattering caused by traditional signum functions. The ablation configuration (PI+LARC+SECFNN) improves this metric to 8.8 ms, validating the initial acceleration provided by the SECFNN feedforward action; however, its linear PI inner loop limits the ultimate tracking bandwidth. In contrast, the proposed strategy utilizes the ASTSMC with a smooth arctangent boundary layer, which allows the algorithm to securely employ much more aggressive tracking gains. From an energy perspective, the ASTSMC effectively maximizes the inductor charging rate in the early stage and seamlessly provides damping near the reference. Consequently, it establishes a precise 48 V steady state in only 6.5 ms with an absolutely smooth trajectory and zero overshoot.

4.1.2. Disturbance Rejection Under Load Variation

To simulate real-world industrial perturbations, the load resistance is abruptly stepped from $30\Omega$ to $20\Omega$ at $t=0.4$ s. Physically, this step instantaneously increases the load current demand, inevitably causing a transient voltage sag as the output capacitor supplies the deficit. The detailed recovery dynamics are visually captured in Figure 7.

The results highly emphasize the vulnerabilities of linear controllers. The pure PI control suffers a massive 90 mV voltage drop and completely fails to recover to the nominal 48 V within the transient observation window. STSMC-SERCFNN and NFTSMC-SOCFNN perform better but still suffer from a 20 mV and 18 mV drop, requiring 4.0 ms and 5.0 ms to recover, respectively, as they rely on integration-based loops that inherently introduce phase lag.

Notably, the ablation configuration (PI+LARC+SECFNN) effectively limits the maximum undershoot to just 16 mV, proving that the algebraic nature of the LARC pre-emptively modulates the reference current before the capacitor significantly discharges. However, because its inner execution loop relies on a traditional PI controller, it requires a sluggish 20.0 ms to fully restore the steady state. The proposed fully configured LARC-SECFNN-ASTSMC strategy perfectly synergizes active feedforward and robust non-linear tracking: it strictly constrains the maximum undershoot to a negligible 15 mV and forcefully drives the system back to steady state in a mere 0.2 ms. Furthermore, supplementary tests evaluating extreme large-signal steps (e.g., $30\Omega$ to $15\Omega$) confirm that the proposed algorithm consistently prevents system collapse and maintains rapid recovery.

4.1.3. Dynamic Reference Voltage Tracking Performance

Rapid reference tracking is a crucial metric for modern power converters employing Dynamic Voltage Scaling to optimize system-level power dissipation. At $t=0.5$ s, the reference $V_{ref}$ is stepped from 48 V to 53 V. As illustrated in Figure 8 and

Table 3. Summary of Simulation Performance Indicators.

Metric	Proposed (ASTSMC)	NFTSMC + SOCFNN	STSMC + SERCFNN	PI + LARC + SECFNN	PI Control
Startup settling time ($t_s$)	6.5 ms	12.0 ms	10.0 ms	8.8 ms	19.0 ms
Max. load undershoot ($\Delta V$)	15 mV	18 mV	20 mV	16 mV	90 mV
Load recovery time ($t_{rec}$)	0.2 ms	5.0 ms	4.0 ms	20.0 ms	Unrecovered
Voltage tracking time ($t_{tr}$)	1.2 ms	7.0 ms	10.0 ms	1.6 ms	4.0 ms
Steady-state error ($e_{ss}$)	0	0	0	0	20 mV

, STSMC-SERCFNN and NFTSMC-SOCFNN exhibit significant tracking delays, taking 10.0 ms and 7.0 ms to align with the new target. Specifically, the NFTSMC-SOCFNN trajectory displays a disjointed, two-stage piecewise ascent due to transient control saturation. The PI controller manages to track the step in 4.0 ms, although it severely lacks disturbance rejection capabilities, as proven in the previous load step test.

Benefiting from the intelligent compensation, the PI + LARC + SECFNN ablation configuration achieves a highly accelerated tracking time of 1.6 ms, as the SECFNN instantly evolves to map the new operational state dynamics and provides the shifted steady-state duty cycle. Nevertheless, the proposed LARC-SECFNN-ASTSMC ultimately provides an ultra-fast tracking time of just 1.2 ms. The continuous ASTSMC inner loop precisely manages the current slew rate without trajectory bifurcation, ensuring a consistent, smooth, and rapid ascent. Additionally, wide-range tracking evaluations stepping down to a 36 V reference level were conducted, further validating the algorithm’s generalized dynamic tracking capabilities across various operational points.

4.1.4. Robustness Evaluation Under Parameter Uncertainties

To rigorously demonstrate the robustness of the proposed composite algorithm against parameter mismatches (such as capacitor degradation due to aging), a comprehensive parameter uncertainty experiment was conducted. In this test, the physical plant’s actual capacitance remained at its nominal value ($C=1000\mathsf{\mu }\mathrm{F}$), while the nominal capacitance parameter utilized within all digital control algorithms was deliberately mismatched by −20% ($C_n=800\mathsf{\mu }\mathrm{F}$).

To explicitly evaluate the performance degradation caused by this mismatch, the absolute voltage error between the nominal parameter model output and the mismatched parameter model output was continuously evaluated. The absolute tracking error waveforms are illustrated in Figure 9, and the quantitative Mean Absolute Error (MAE) results are summarized in

Table 4. Mean Absolute Error (MAE) of the Output Voltage Under −20% Parameter Mismatch.

Algorithm Configuration	Mean Absolute Error (MAE)
PI Control	63.266 mV
PI + LARC + SECFNN (Ablation)	5.129 mV
SOCFNN-NFTSMC	3.731 mV
STSMC + SOCFNN	0.832 mV
Proposed Strategy	0.789 mV

.

As demonstrated in the results, the traditional PI control exhibits the highest sensitivity to parameter variations, yielding an MAE of 63.266 mV. The ablation PI + LARC + SECFNN configuration yields an MAE of 5.129 mV. The baseline nonlinear controllers (SOCFNN-NFTSMC and STSMC + SOCFNN) show improved robustness, yielding MAEs of 3.731 mV and 0.832 mV, respectively. In contrast, the proposed strategy compensates for the parameter mismatch, achieving the lowest MAE of 0.789 mV. The corresponding error trajectory in Figure 9 confirms that the proposed method maintains tracking accuracy with minimal fluctuations under the evaluated capacitance degradation.

4.2. Experimental Validation

To further verify the practical feasibility, real-time control performance, and hardware deployment capability of the proposed control strategy, a hardware prototype of the 48 V DC-DC buck converter was constructed in the laboratory. As shown in Figure 10, the experimental testbed mainly consists of a programmable DC power supply, the main buck converter power stage (including switching devices, sensors, and LC filters), an electronic load, and a high-definition digital storage oscilloscope for capturing real-time waveforms.

Remark 4.

Computational Complexity and Real-Time Hardware Feasibility.

Implementing complex nonlinear algorithms imposes stringent computational constraints. The selected STM32G431RBT6 microcontroller (170 MHz, FPU) provides exactly 1700 clock cycles within the 10 μs control period.

To prevent calculation overrun under these limits, the lightweight SECFNN minimizes computational burden via two structural optimizations: first, the 3rd-order Chebyshev polynomials ($T_1=x$, $T_2=2x^2-1$, $T_3=4x^3-3x$) are executed using simple recursive algebra, strictly avoiding expensive transcendental functions; second, the active pruning mechanism limits the maximum firing nodes (typically maintained under 7 nodes during experiments).

To provide a comprehensive comparative analysis, the proposed control scheme is compared with three other control strategies under the same experimental conditions: (1) PI Control (Baseline Proportional–Integral Control). (2) NFTSMC-SOCFNN (Non-singular Fast Terminal Sliding-Mode Control with Self-Organizing Chebyshev Fuzzy Neural Network). (3) STSMC-SERCFNN (Super-Twisting Sliding-Mode Control with Self-Evolving Recurrent Chebyshev Fuzzy Neural Network).

The comprehensive experimental results, including startup settling times, dynamic tracking times, and load disturbance recovery performances, are detailed in the subsequent subsections.

4.2.1. Startup Phase Analysis

During the experiment, the reference voltage $V_{ref}$ is stepped from 0 to 48 V, and the load resistance remains unchanged at 30 $\Omega$. The response curves of the output voltage during the startup phase for the four evaluated control schemes are shown in Figure 11.

As observed in the experimental results, the traditional STSMC-SERCFNN scheme displays a sluggish, overdamped response, taking approximately 18.7 ms to reach the steady state. The NFTSMC-SOCFNN scheme is faster, requiring 16.3 ms, but it exhibits a noticeable voltage overshoot before settling. The PI control scheme (Figure 11d) displays typical linear feedback limitations, resulting in noticeable overshoot and a significantly prolonged settling process. In stark contrast, the output voltage of the proposed control scheme rises rapidly and converges to the 48 V reference accurately in merely 8.3 ms without any overshoot. Through the experimental results, it is evident that the proposed control scheme achieves a perfect balance between dynamic response and steady-state characteristics during the startup phase.

4.2.2. Linear Load Resistance Variations

In this experiment, the linear load resistance is changed abruptly between 30 $\Omega$ and 20 $\Omega$ by the electronic load, and the output voltage reference value remains unchanged at 48 V. The detailed results of the four control schemes are shown in Figure 12.

Due to the introduction of severe external disturbance when the resistance steps down, the output voltages of both the NFTSMC-SOCFNN and STSMC-SERCFNN control schemes experience noticeable voltage drops and require a prolonged recovery period to return to the 48 V reference. As shown in Figure 12d, although the traditional PI controller achieves a relatively fast recovery time, it is highly sensitive to the external disturbance, exhibiting the deepest voltage drop among all evaluated schemes. In contrast, owing to the active feedforward compensation of the LARC module, the voltage drop of the proposed control scheme is effectively suppressed, and the system achieves a rapid recovery. This indicates that the proposed scheme provides favorable robustness and anti-disturbance capability under load step conditions.

4.2.3. Reference Voltage Variations

To evaluate dynamic tracking performance, the reference voltage is stepped from 48 V to 53 V, as illustrated in Figure 13.

The traditional STSMC exhibits a sluggish, overdamped response, requiring 28.5 ms to reach the new voltage level. While the NFTSMC scheme achieves a faster 3.25 ms settling time, its trajectory is suboptimal, displaying an aggressive initial jump followed by a disjointed, two-stage piecewise ascent. The PI controller (Figure 13d) tracks the new reference but exhibits a relatively slow response with a slightly underdamped trajectory compared to the proposed strategy.

In contrast, the proposed scheme achieves an ultra-fast tracking time of just 2.2 ms with excellent transient smoothness. It climbs to the 53 V target via a continuous and uniform slope, completely avoiding the disjointed trajectory of the NFTSMC. These results verify that the proposed strategy delivers superior dynamic tracking, ensuring rapid transitions without sacrificing waveform quality.

4.2.4. Control Quantity and Chattering Mitigation Analysis

To observe how the proposed ASTSMC mitigates sliding mode chattering, the real-time control quantity (PWM duty cycle u) was captured during the hardware experiments.

As depicted in Figure 14, the traditional sliding mode controllers (STSMC and NFTSMC) produce control signals characterized by noticeable high-frequency oscillations near the sliding manifold. While the linear PI controller (Figure 14a) naturally generates a continuous PWM signal, its dynamic tracking bandwidth is limited. Conversely, by replacing the discontinuous signum function with the arctangent operator, the duty cycle waveform of the proposed ASTSMC (Figure 14d) exhibits slightly smaller high-frequency spikes compared to the other nonlinear methods. Furthermore, it can be observed from the waveforms that the proposed ASTSMC yields the smallest duty cycle fluctuation among the evaluated sliding mode algorithms, indicating that its associated chattering loss is relatively smaller.

4.2.5. Summary of Hardware Experimental Results

To provide a clearer and more direct comparison, the key performance metrics extracted from the hardware experimental waveforms are quantitatively summarized in

Table 5. Performance Summary of Hardware Experimental Validation.

Experimental Metric	Proposed	NFTSMC	STSMC	PI Control
Startup settling time ($t_s$)	8.3 ms	16.3 ms	18.7 ms	20.2 ms
Startup overshoot	0 V	0.8 V	0 V	0.2 V
Reference tracking time ($t_{tr}$)	2.2 ms	3.25 ms	28.5 ms	7.7 ms

. The data clearly validates that the proposed LARC-SECFNN-ASTSMC strategy overwhelmingly outperforms the comparative methods in real-world physical implementations.

5. Conclusions

To address the voltage regulation requirements of 48 V data center power systems under dynamic loads, this paper proposes a composite control strategy integrating LARC, SECFNN, and ASTSMC. In this strategy, the LARC module achieves the analytical reconstruction of unknown load states based on algebraic mechanisms, providing rapid compensation for the system during load steps. This effectively reduces the phase lag caused by pure feedback control and the initial transient voltage drops during disturbances. Based on the compensation of major external disturbances by LARC, the SECFNN is utilized to fit the nonlinear residuals of the system. Its bidirectional evolution mechanism enables the network to dynamically adjust its topology without computational redundancy, thereby handling internal lumped disturbances caused by parameter drift and unmodeled dynamics. Furthermore, the inner-loop ASTSMC serves as the execution law, employing a continuous arctangent operator to generate control actions. While ensuring the finite-time convergence of the system state, it effectively attenuates the chattering phenomenon of traditional sliding mode control and reduces the electrical stress on power devices. Simulation and experimental results demonstrate that under demanding operating conditions, including unpowered startup, sudden large-signal load steps, dynamic reference voltage transitions, and capacitor parameter drift, the proposed composite control strategy effectively guarantees the dynamic recovery performance and steady-state precision of the system. In summary, the proposed scheme combines algebraic state reconstruction and dynamic intelligent approximation, providing a practical and feasible control architecture for the high-performance voltage regulation of 48 V buck converters.