A Self-Powered, Fast-Response High-Voltage Safety Discharge Topology Based on Cascaded Depletion-Mode NMOS for Compact Pulse Generators

Abstract

High-voltage short pulse generators play a critical role in medical and industrial applications. However, the presence of residual stored energy can pose significant electrical safety hazards. To mitigate these hazards, the implementation of rapid discharge mechanisms is imperative. To address the limitations of slow passive bleeders and auxiliary-dependent active circuits, and the issue of excessive size for compact pulse generators, this study proposes a self-powered, fast-response discharge topology utilizing cascaded depletion-mode NMOS transistors. The method utilizes the inherent normally-on characteristic of depletion-mode devices to ensure fail-safe activation during power loss, employing a self-biased feedback loop to regulate a constant discharge current. The theoretical models were validated through simulations and a hardware prototype testing a 1200 V/220 nF capacitor. The experimental results demonstrate the capability to successfully discharge 1200 V to a safe level within a span of one second. Additionally, the discharge time can be programmed within the range from 72 milliseconds to 1.02 s by adjusting the current-limiting resistor. In summary, the proposed topology offers a reliable, compact, and adjustable solution for high-voltage safety, addressing the limitations of conventional discharge technologies in terms of volume and speed.

1. Introduction

The short pulse generator has the capacity to convert long-term low-power input into short-term high-power output, characterized by high voltage, high current, and fast rise time. It is capable of generating single shot or periodic high-voltage pulses [1,2,3,4].

Short pulse generators have found diverse applications across various high-impact fields. In the medical domain, these generators are widely used in electroporation, a technique that involves the application of short electric pulses to enhance the permeability of cell membranes, facilitating drug delivery and gene therapy [5,6]. Furthermore, short-pulse generators have been demonstrated to play a crucial role in the generation of plasma, where they facilitate the creation of high-energy plasma states that are necessary for a variety of applications in material processing and surface modification [2,7]. The high-voltage, rapid-pulse characteristics of these generators facilitate more efficient plasma formation, thereby enhancing the performance of industrial systems [8]. In the industrial sector, they are integral to ignition systems, where their ability to generate precise, high-energy pulses ensures reliable combustion [4]. In the domain of defense, short pulse generators play a pivotal role in the development of sophisticated weapon systems, encompassing electromagnetic weapons and directed-energy devices. These generators facilitate the generation of high-powered electromagnetic pulses with the potential to disable electronic systems or modify the functionality of enemy devices [9,10]. Driven by the growing demand for compact and integrated systems across these diverse applications, miniaturizing high-voltage pulse generators has become a key area of research [11,12,13]. Traditionally, these generators relied on bulky gas-based switches and large-scale capacitor banks, which limited their use in environments with space constraints. Recent research has primarily focused on overcoming these limitations through a multi-pronged strategy. One significant trend is the shift from conventional spark gaps to robust, all-solid-state switching architectures that leverage the superior performance of devices such as SiC, MOSFET and IGBT [11,14,15,16]. These solid-state switches offer exceptional reliability, precise jitter control, and crucially, the potential for monolithic integration. Concurrently, innovations in passive component technology are being actively pursued. This includes developing compact, high-energy-density dielectric materials for pulse forming networks, such as advanced polymer films and ferroelectric capacitors [17,18], and adopting sophisticated topologies, like Blumlein lines, which are implemented on printed circuit boards or in planar integrated formats [19]. Additionally, three-dimensional packaging and heterogeneous integration techniques enable unprecedented miniaturization by co-locating power semiconductors, passive elements, and control circuitry within a single module [16]. These advances collectively shrink the physical footprint and enhance the pulse fidelity and operational stability of high-voltage, short-pulse generators [20], unlocking new possibilities for next-generation applications.

As illustrated in Figure 1, the architecture of a short pulse generator generally utilizes a cascaded topology consisting of four distinct operational stages: power supply, energy storage, pulse compression, and switching control [21,22]. The initial energy is derived from the power supply module, which can employ standard AC/DC power sources, high-capacity batteries, or supercapacitors [23,24]. Furthermore, in advanced integrated systems, the initial energy can also be acquired through emerging wireless power transfer technologies [25]. This energy is subsequently conditioned during the energy storage phase, where intermediate storage capacitors are charged to the initial voltage level via high-voltage converter topologies such as boost or flyback circuits [21]. The core high-voltage generation process takes place during the pulse compression stage. This stage employs voltage-doubling and shaping networks, such as Marx generators [26,27] or Tesla transformers [28], to achieve the necessary peak voltage and pulse steepness. The final pulse output is governed by the switching stage. The integration of electromechanical reed switches, high-voltage spark gap switches, or solid-state semiconductor devices (e.g., thyristors, MOSFETs, and IGBTs) in this stage is contingent upon the frequency and power requirements, thereby ensuring precise commutation [29,30].

A critical challenge in the development of compact and miniaturized pulse generators is the adaptation of low-voltage power inputs within a highly restricted volume while still achieving the required high-power pulse outputs. This discrepancy in power levels underscores the necessity for an efficient energy storage system that can accumulate energy from the source and release it instantaneously [31,32]. Among the various technologies available, capacitors remain the classic and quintessential choice for energy storage due to their fast discharge rates, high reliability, and scalability. However, the high-voltage transients inherent in their operation pose significant electrical safety hazards. In contrast to operational risks, which can be mitigated through external insulation or physical isolation, the dangers stemming from residual stored energy persist even after power disconnection, rendering passive barrier measures ineffective. In order to ensure the safety of personnel, contemporary designs must rigorously adhere to pertinent safety standards. For instance, IEC 62368-1 categorizes such energy storage systems as Category 3 hazards [33], stipulating that residual voltage must decay to safe levels (typically below 60 V DC) within two seconds following the disconnection of power. Meeting these stringent time constraints within the confined spaces of modern compact systems imposes extreme demands on power density [34,35].

The necessity for rapid and reliable discharge of high-voltage buses or energy storage capacitors extends far beyond compact pulse generators, playing a critical role in a wide spectrum of applications, including electric vehicles (EVs), renewable energy inverters, medical equipment, and high-power industrial drives [36,37]. To mitigate the safety hazards associated with these phenomena, various discharge mechanisms have been developed and deployed. In essence, these strategies can be classified into two primary categories: passive and active discharge mechanisms. While passive methods, such as the implementation of bleeding resistors, offer structural simplicity, they inherently exhibit continuous power loss and slow, uncontrollable discharge rates. Conversely, active mechanisms offer faster and highly controllable discharge capabilities, though often at the expense of increased system complexity and the need for auxiliary power. A thorough comparison of these conventional topologies, emphasizing their operational characteristics, power leakage, and inherent limitations, is presented in

Table 1. Comparison of Passive and Active Discharge Mechanisms for High-Voltage Systems [37].

Category	Discharge Topology	Topology Description	Additional Components	Power Leakage During Blocking Process	Auxiliary Power Required During Discharge Process	Limitation
Passive	Bleeding Resistor	A Resistor in Parallel	Yes	High (Continuous $V^2/R_{bleed}$)	No	Uncontrollable and Slow
Active	Motor Winding Bleeding	Motor Winding Resistance via PWM-Controlled Switches	No	Zero	Yes	Only for motors
	Current-Limiting Bleeding	Current-Limiting Circuit	Yes	Leak Current of Switch	Yes	High Requirements for Switches
	Active Bleeding Resistor	Power Switch and Bleeding Resistor	Yes	Leak Current of Switch	Yes	Bulky Resistor
	Hybrid	Combinations of the Above Topologies	/	/	/	/

.

As demonstrated in Table 1, passive mechanisms are inherently constrained in their capabilities. They exhibit a deficiency in dynamic controllability, incapable of facilitating expeditious discharge, and exhibit adverse interference with standard system operation through continuous power dissipation. Consequently, contemporary research has undergone a shift in focus, with a notable emphasis on active discharge solutions. A synopsis of the extant literature pertaining to these active discharge mechanisms is provided in

Table 2. Summary of Existing Active Discharge Mechanisms in the Literature.

Ref.	Discharge Topology	Key Components	Initial Voltage ${\mathit{V}}_{\mathit{i}\mathit{n}\mathit{i}\mathit{t}}$	Energy Storage Capacitance ${\mathit{C}}_{\mathit{s}\mathit{t}\mathit{o}\mathit{r}\mathit{e}}$	Discharge Time ${\mathit{T}}_{\mathit{d}\mathit{i}\mathit{s}}$	Circuit Size	Aux Input While Discharging	Application
[38]	Motor Winding	/	310 V	560 μF	3.0 s	/	d- and q-axis current control	PMSM in EVs
[39]	Active Bleeding Resistor + Motor Winding Hybrid	Bleeding Resistor Module	310 V	420 μF	1.25 s	0.5 kg/60 cm3	d- and q-axis current control	PMSM in EVs
[40]	Current-Limiting Bleeding	IGBT Module	400 V	1000 μF	1.2 s	Not Mentioned	PWM signal	DC Link Capacitor
[41]	Current-Limiting Bleeding	SiC Switch (TO-247 or Module)	1000 V	600 μF	1 s	Compact	Variable Gate-Source Voltage	EV Powertrain
Proposed	Current-Limiting Bleeding	Depletion-Mode NMOS (SOT-223)	1200 V	220 nF	<1 s	Single-Layer PCB with SMT Components	No	Compact Pulse Generators

.

As demonstrated by the data presented in Table 2, the majority of existing active discharge topologies are designed with large-scale applications, such as electric vehicles (EVs) or heavy motor drives, in mind. These conventional methods generally address substantial energy storage capacitances and necessitate the use of voluminous components. Moreover, they mandate the continuous transmission of auxiliary control signals during the discharge phase. However, a significant discrepancy emerges when these solutions are applied to compact high-voltage pulse generators. These systems are distinguished by their high operational voltages and low target capacitances, which are further compounded by their limited spatial dimensions. The cumbersome physical footprint and auxiliary power dependency of current methods render them impractical for these highly integrated environments. Consequently, there is an imperative need for a novel discharge architecture that utilizes small surface-mount components and single-layer PCB to execute rapid, safe discharge autonomously, thereby eliminating the reliance on external auxiliary inputs.

In order to address these imperatives, the present paper proposes a novel self-powered, fast-response discharge topology that leverages cascaded depletion-mode NMOS transistors. The proposed circuit is designed to function reliably even in the event of a complete system power failure. This objective is accomplished by capitalizing on the inherent normally-on characteristic of depletion-mode NMOS devices, thereby eliminating the requirement for external auxiliary power supplies. The topology incorporates a cascaded configuration to withstand high-voltage transients while maintaining a compact footprint suitable for miniaturized pulse generators. Furthermore, a control mechanism has been integrated to facilitate a constant-current discharge profile. This approach effectively addresses the trade-off between the rapid discharge requirements and the stringent volume constraints of contemporary compact pulsed-power systems.

The rest of this paper is systematically organized as follows. Section 2 outlines the design and theoretical operational principles of the proposed discharge circuit topology. Section 3 details the simulation analysis conducted to evaluate parameter sensitivity and statistical reliability. Section 4 presents experimental verification through hardware prototype testing, focusing on discharge performance, long-term repeatability, and thermal stability. Finally, the discussion and concluding remarks are presented in Section 5 and Section 6, respectively.

2. Circuit Topology Design

As illustrated in Figure 2, the proposed topology utilizes a cascaded configuration of depletion-mode NMOS transistors to achieve high-voltage handling capabilities. The circuit under consideration is principally constituted by a voltage-balancing network, a cascaded MOSFET switch array, and an isolated gate drive circuit.

The input source is applied across terminals $V_{IN}^{+}$ and $V_{IN}^{-}$. A passive static voltage-balancing network, consisting of $N$ series-connected resistors $R_{12}$ to $R_{n2}$ and parallel capacitors $C_{12}$ to $C_{n2}$, is placed in parallel with the main power stage. This network functions by dividing the high input voltage into equal steps at nodes $J_1$ through $J_n$. This ensures uniform voltage distribution across the switch stack in the off-state.

The primary current path is established through an $N$-stage series string of MOSFETs, denoted as $Q_1$ through $Q_n$. The current flows sequentially from the drain of the top-side transistor $Q_n$, cascading down through intermediate stages, and finally through the bottom-side transistor $Q_1$. The control mechanism is divided into two distinct parts:

• The Master Stage $Q_1$: The bottom-most transistor $Q_1$ fuctions as the master control switch. The gate is driven by an optocoupler $U_1$, which provides the necessary galvanic isolation for the control signals $CTR{L}^{+}$ and $CTR{L}^{-}$. A pull-down resistor $R_b$ is connected between the gate and source of $Q_1$ to ensure a reliable off-state in the absence of a control signal. The source of $Q_1$ is connected to the output terminal $V_{OUT}^{+}$ via a current-limiting resistor $R_c$.
• The Slave Stages $Q_2$ to $Q_n$: The upper transistors fuction in a self-biased cascade follower configuration. The gate of each upper-stage MOSFET $Q_k$ (where $k > 1$) is referenced to the voltage divider node $J_{k-1}$ of the previous stage. For instance, the gate of $Q_2$ is connected to node $J_1$, and the gate of $Q_n$ is connected to node $J_{n-1}$.

In order to safeguard the gate dielectrics of the upper-stage MOSFETs, a clamping network comprising a Zener diode (e.g., $D_{21}$ to $D_{n1}$) and a series resistor (e.g., $R_{21}$ to $R_{n1}$) is connected between the gate and source of each respective transistor. These Zener diodes $D_{k1}$ serve to clamp the gate-source voltage $V_{GS}$ within safe operating limits during switching transients. The reverse breakdown voltage of the Zener diodes is selected to be significantly lower than the static voltage drop across the corresponding balancing resistors $R_{k1}$. This ensures that the Zener diodes effectively protect the MOSFETs without interfering with the static voltage distribution determined by the resistive network.

2.1. Depletion-Mode NMOS Characteristics and Self-Biasing Principle

The selection of depletion-mode NMOS transistors as the core switching elements is fundamentally motivated by their inherent normally-on characteristic. In contrast to enhancement-mode devices, which require an external gate bias to establish a conductive channel, a depletion-mode NMOS maintains the on-state at zero or part negative gate-source bias. This property renders it an optimal selection for fail-safe discharge mechanisms, wherein switches are required to default to the conducting state automatically upon loss of the control signal.

The electrical behavior of the depletion-mode N-channel MOSFET is characterized by its transfer and output characteristics, as illustrated in Figure 3. The transfer characteristic, denoted by $I_D$ versus $V_{GS}$, demonstrates a decline in the drain current $I_D$ as the gate-source voltage $V_{GS}$ becomes more negative, ultimately reaching a state of zero when the gate-source voltage $V_{GS}$ attains the pinch-off voltage $V_{GS\left(off\right)}$. The output characteristic, denoted by $I_D$ versus $V_{DS}$, demonstrates that for a constant $V_{GS}$, $I_D$ remains relatively constant once the drain-source voltage $V_{DS}$ exceeds the saturation voltage. This behavior is characterized by a distinct constant-current response [42].

Utilizing this saturation behavior, a straightforward yet remarkably efficacious constant current source can be engineered, as demonstrated in Figure 4. This configuration employs a self-biasing mechanism, wherein a source resistor, designated as $R_C$, is connected in series with the source terminal. The gate is referenced to the bottom of $R_C$ [43].

In this configuration, the voltage drop across $R_C$ provides a negative bias to the gate relative to the source, expressed as:

$$V_{GS}=-I_D\times R_C$$

(1)

Assuming the depletion-mode MOSFET operates in the saturation region, the drain current is governed by the square-law equation:

$$I_D=I_{DSS}{\left(1-{\displaystyle \frac{V_{GS}}{V_{GS\left(off\right)}}}\right)}^2$$

(2)

The substitution of Equation (1) into Equation (2) results in the derivation of the relationship between the target constant current $I_{set}$ and the required resistance $R_C$. In the event that a desired current $I_{set}$ is established, with the stipulation that $I_{set}$ is less than the designated threshold, referred to as $I_{DSS}$, the requisite resistance value can be determined through:

$$R_C={\displaystyle \frac{{-V}_{GS\left(off\right)}}{I_{set}}}\left(1-\sqrt{{\displaystyle \frac{I_{set}}{I_{DSS}}}}\right)$$

(3)

This negative feedback mechanism ensures that any increase in $I_D$ leads to a more negative $V_{GS}$; consequently, the current rise is counteracted, thereby stabilizing the output current against variations in the supply voltage, provided the device remains in saturation.

This self-biasing principle constitutes the core mechanism of the proposed topology. The master switch $Q_1$, in conjunction with the current-limiting resistor $R_C$, constitutes a self-biased constant-current sink. In the discharge mode, the normally-on characteristic of $Q_1$ ensures automatic activation without the need for an external drive. The source degeneration provided by $R_C$ stabilizes the discharge current against bus voltage decay.

The intrinsic characteristics of depletion-mode MOSFETs render them highly suitable for fail-safe discharge applications. However, the direct employment of a single device to discharge high-voltage energy storage components imposes extreme demands on its breakdown voltage $B{V}_{DSS}$. Monolithic ultra-high-voltage depletion-mode devices necessitate cumbersome physical packaging to guarantee sufficient creepage distances, a practice that profoundly contravenes the imperative for miniaturization. Additionally, a significant discrepancy in parameters has been identified. These specialized devices are typically designed to manage substantial on-state currents. However, safety discharge circuits typically operate within the milliampere to low-ampere range. This discrepancy can lead to increased costs and wasted current-handling capacity. Consequently, the distribution of high-voltage stress across multiple smaller, commercially available low-voltage devices through the cascaded configuration previously described is imperative for achieving a compact, cost-effective design.

2.2. Operational Principle and Theoretical Analysis of Mode Control

The proposed topology is controlled via the differential terminals $CTR{L}^{+}$ and $CTR{L}^{-}$, which drive the isolation optocoupler $U_1$. To ensure system safety, the control logic is designed with a normally-on characteristic that utilizes the inherent properties of depletion-mode MOSFETs. The operation consists of two primary states, which are determined by the input voltage level:

• Discharge Mode ($V_{CTRL}=0$/Logic Low)

The discharge mode signifies the fail-safe state of the proposed topology, which is automatically engaged in the event of a power failure, emergency shutdown, or loss of the control signal (i.e., $V_{CTRL}=0$). As illustrated in Figure 5, the sequence of operations is initiated by the deactivation of the optocoupler $U_1$.

In the absence of a drive current on the input side of $U_1$, its output phototransistor enters a cutoff state, resulting in a high-impedance output. Consequently, the gate of the master switch $Q_1$ is pulled to its source potential via the resistor $R_b$, establishing a gate-source voltage of approximately zero ($V_{GS}\approx 0$). Due to the depletion-mode characteristic of the NMOS devices, $Q_1$ is normally on at zero bias. Therefore, $Q_1$ instantaneously enters the conduction region, thereby establishing a current path from its drain to the ground (or negative rail) through the current-limiting resistor $R_c$.

The activation of $Q_1$ instigates a cascaded turn-on process for the upper stages $Q_2$ to $Q_n$ through a domino effect:

• As $Q_1$ conducts, it pulls down the source potential of the subsequent stage, $Q_2$;
• The gate of $Q_2$, however, remains referenced to the voltage divider node $J_1$. This node is maintained by the parallel capacitor $C_{12}$ and resistor $R_{12}$;
• This potential difference generates a positive effective gate-source voltage for $Q_2$, driving it into conduction;
• This mechanism propagates sequentially up the stack until the topmost transistor $Q_n$ is activated.

Subsequent to the attainment of complete conductivity throughout the string, the energy stored in the high-voltage capacitors or the input source $V_{IN}$ is discharged through the MOSFET chain. This configuration leverages the inherent saturation characteristics of depletion-mode MOSFETs. In the event that $V_{GS}$ is maintained at a value approximating zero or negative voltage, $Q_1$ functions within its saturation region, thereby operating as a constant current sink. This operation is subject to limitations imposed by two factors: the saturation drain current $I_{DSS}$ and the source degeneration effect of $R_c$.

During this process, the Zener diode networks $D_{21}$ to $D_{n1}$ positioned between the gate and source of each upper-stage MOSFET serve a dual purpose: they clamp the $V_{GS}$ to prevent gate oxide breakdown during the transient voltage redistribution and ensure that the transistors operate within their safe operating area (SOA) during the high-voltage discharge.

As the discharge current $I_{dis}$ flows through $R_c$, it elevates the source potential $V_S$ of $Q_1$. Given the grounded nature of the gate, the effective gate-source voltage, denoted by $V_{GS}$, assumes a negative value:

$$V_{GS}=V_G-V_S=0-I_{dis}\cdot R_c=-I_{dis}\cdot R_c$$

(4)

For a depletion-mode MOSFET operating in the saturation region ($V_{DS}>V_{GS}-V_{GS\left(off\right)}$), the drain current is governed by the Shockley equation:

$$I_D=I_{DSS}{\left(1-{\displaystyle \frac{V_{GS}}{V_{GS\left(off\right)}}}\right)}^2$$

(5)

where $I_{DSS}$ is the saturation drain current at zero bias, and $V_{GS\left(off\right)}$ is the pinch-off voltage (a negative value for depletion-mode NMOS) [44]. Substituting Equation (4) into Equation (5) yields the governing equation for the discharge current:

$$I_{dis}=I_{DSS}{\left(1-{\displaystyle \frac{-I_{dis}\cdot R_c}{V_{GS\left(off\right)}}}\right)}^2=I_{DSS}{\left(1+{\displaystyle \frac{I_{dis}\cdot R_c}{\left|V_{GS\left(off\right)}\right|}}\right)}^2$$

(6)

This relationship indicates that $I_{dis}$ is self-stabilized to a value less than $I_{DSS}$. The resistor $R_c$ functions as a programming element. By selecting an appropriate resistance value, the discharge current can be precisely defined.

The total high voltage $V_{IN}\left(t\right)$ is distributed across the cascaded stages. Assuming a balanced resistive network $R_{12}=\cdots =R_{n2}$, the potential at the $k$-th node $J_k$ is linear:

$$V_{J_k}=V_{IN}\left(t\right)\cdot {\displaystyle \frac{k}{n}}$$

(7)

Therefore, the drain-source voltage for each stage is clamped to $V_{DS}\approx V_{IN}\left(t\right)/n$, ensuring uniform stress distribution.

The discharge time $T_{dis}$ is defined as the duration required to deplete the energy storage capacitance $C_{store}$ from a initial high voltage $V_{init}$ to a safe threshold $V_{safe}$. This discharge time derived from the constant-current discharge integration:

$$T_{dis}={\int }_{V_{safe}}^{V_{init}}{\displaystyle \frac{C_{store}}{I_{dis}}}\hspace{0.17em}d\mathrm{V}={\displaystyle \frac{C_{store}\cdot \left(V_{init}-V_{safe}\right)}{I_{dis}}}$$

(8)

This linear decay characteristic is in contrast to the exponential decay of passive RC bleeders. The proposed circuit utilizes the self-biased topology $Q_1$ and $R_c$ to maintain a high and constant discharge rate even as the bus voltage drops. This approach significantly reduces the time-to-safe interval compared to traditional methods.

A critical reliability metric for fail-safe systems is the deterministic consistency of the discharge time $T_{dis}$ across varying manufacturing tolerances and environmental conditions. Commercial depletion-mode MOSFETs inherently exhibit significant discrete dispersion in both their zero-bias saturation current $I_{DSS}$ and pinch-off voltage $V_{GS\left(off\right)}$. Additionally, the thermoelectric properties of $I_{DSS}$ are found to be significantly temperature-dependent, owing to the diminished carrier mobility that occurs at elevated junction temperatures. A formal sensitivity analysis is imperative to quantitatively evaluate the robustness of the proposed constant-current regulation against such device dispersion.

By implicitly differentiating Equation (6) with respect to $V_{GSoff}$, the absolute sensitivity of the discharge current to the pinch-off voltage is derived as:

$${\displaystyle \frac{\partial I_{dis}}{\partial V_{GSoff}}}={\displaystyle \frac{-2I_{dis}{R}_c\sqrt{I_{DSS}{I}_{dis}}}{V_{GSoff}\left(V_{GSoff}-2R_c\sqrt{I_{DSS}{I}_{dis}}\right)}}$$

(9)

Similarly, differentiating Equation (6) with respect to the saturation current $I_{DSS}$ yields:

$${\displaystyle \frac{\partial I_{dis}}{\partial I_{DSS}}}={\displaystyle \frac{I_{dis}{V}_{GSoff}}{I_{DSS}\left(V_{GSoff}-2R_c\sqrt{I_{DSS}{I}_{dis}}\right)}}$$

(10)

In order to comprehend the impact of these current variations on the system-level safety threshold, the chain rule is employed to analyze Equation (8). The paramount engineering concern pertains to the relative sensitivity coefficient $S_x^{T_{dis}}$, which quantifies the percentage change in the total discharge time $T_{dis}$, resulting from a change in the intrinsic parameter $x$. The relative sensitivity coefficients for $V_{GSoff}$ and $I_{DSS}$ are respectively expressed as:

$$S_{V_{GSoff}}^{T_{dis}}={\displaystyle \frac{\partial T_{dis}}{\partial V_{GSoff}}}{\displaystyle \frac{V_{GSoff}}{T_{dis}}}={\displaystyle \frac{2R_c\sqrt{I_{DSS}{I}_{dis}}}{V_{GSoff}-2R_c\sqrt{I_{DSS}{I}_{dis}}}}$$

(11)

$$S_{I_{DSS}}^{T_{dis}}={\displaystyle \frac{\partial T_{dis}}{\partial I_{DSS}}}{\displaystyle \frac{I_{DSS}}{T_{dis}}}={\displaystyle \frac{-V_{GSoff}}{V_{GSoff}-2R_c\sqrt{I_{DSS}{I}_{dis}}}}$$

(12)

In the context of depletion-mode NMOS devices, the pinch-off voltage is defined as negative, indicating that the threshold voltage $V_{GSoff}$ is less than zero. Consequently, the denominator in both relative sensitivity equations is the sum of two negative terms. An analysis of these bounds reveals a mathematically characteristic of the proposed topology. Specifically, the magnitudes of both relative sensitivity coefficients are constrained to be less than unity.

$$\left|S_{V_{GSoff}}^{T_{dis}}\right|<1\mathrm{and}\left|S_{I_{DSS}}^{T_{dis}}\right|<1$$

(13)

This mathematical boundary demonstrates that the self-biasing source degeneration resistor $R_c$ effectively functions as an attenuation factor. Consequently, even if standard commercial MOSFETs demonstrate considerable batch-to-batch variation in $V_{GSoff}$ or $I_{DSS}$, the resulting fractional variance in the safety discharge time $T_{dis}$ will invariably be disproportionately smaller.

Moreover, this attenuation inherently safeguards the system against thermal drift. During the high-voltage transient, the MOSFETs dissipate energy, causing an increase in junction temperature and, consequently, a decrease in $I_{DSS}$. According to the sensitivity function, the thermal reduction causes a slight, attenuated elongation of $T_{dis}$. This dynamic reduction in peak power dissipation prevents thermal runaway, thereby ensuring the system’s reliable compliance with safety standards under extreme, non-ideal conditions.

Operating in the linear saturation region inherently subjects the discharge circuit to simultaneous high-voltage stress. In order to comprehensively assess the thermal reliability and ensure that the devices operate strictly within their Safe Operating Area, it is essential to evaluate the instantaneous power dissipation.

During the constant-current discharge phase, the bus voltage $v\left(t\right)$ decays linearly from the initial voltage $V_{init}$. The total instantaneous power dissipated by the entire topology at any given time is expressed as:

$$P_{dis}\left(t\right)=\mathrm{v}\left(t\right)\cdot I_{dis}=\left(V_{init}-{\displaystyle \frac{I_{dis}}{C_{store}}}t\right)I_{dis}$$

(14)

The total thermal energy is distributed by the passive current-limiting resistor $R_c$ and the active cascaded MOSFET string. Given the strict regulation of the discharge current, the instantaneous power dissipated by the source resistor remains constant throughout the active window.

$$P_{Rc}=I_{dis}^2\cdot R_c$$

(15)

Therefore, under the assumption that the static and dynamic voltage-balancing network effectively equalizes the voltage stress across the N cascaded stages, the instantaneous power dissipation imposed on each individual depletion-mode MOSFET $P_Q\left(t\right)$ is calculated by subtracting the resistor’s fixed dissipation from the total power and dividing by the number of stages.

$$P_Q\left(t\right)={\displaystyle \frac{v\left(t\right)I_{dis}-I_{dis}^2{R}_c}{N}}={\displaystyle \frac{\left(V_{init}-\frac{I_{dis}}{C_{store}}t\right)I_{dis}-I_{dis}^2{R}_c}{N}}$$

(16)

This mathematical formulation underscores a pivotal thermal benefit inherent to the proposed topology. The peak power dissipation per MOSFET occurs precisely at the initiation of the discharge ($t = 0$), when the bus voltage is at its absolute maximum. The peak thermal stress per stage is defined as:

$$P_{Q\_peak}={\displaystyle \frac{V_{init}{I}_{dis}-I_{dis}^2{R}_c}{N}}$$

(17)

It has been demonstrated that by deliberately shifting a portion of the initial thermal burden onto the passive power resistor, denoted by the subtractive term $I_{dis}^2{R}_c$, the peak instantaneous power dissipation upon the semiconductor junctions is inherently reduced. This distributed thermal mechanism is designed to ensure that the transient thermal impedance of the MOSFETs is not exceeded. As a result, the cascaded string can safely navigate the high-stress linear region without violating the boundary conditions of the devices’ SOA limits.

In order to undertake a fundamental evaluation of the thermal stability of the proposed safety discharge topology, it is necessary to conduct a quantitative analysis of the temperature-dependent characteristics of the depletion-mode MOSFET. The thermal drift of the steady-state discharge current $I_{dis}$ is governed by the competing physical mechanisms of carrier mobility, denoted by $\mathrm{\mu }\left(T\right)$, and the pinch-off voltage $V_{GSoff}\left(T\right)$.

The carrier mobility demonstrates a negative temperature coefficient due to enhanced acoustic phonon scattering at elevated temperatures, which can be mathematically modeled as:

$$\mathrm{\mu }\left(T\right)=\mathrm{\mu }\left(T_0\right){\left({\displaystyle \frac{T}{T_0}}\right)}^{-\mathsf{\alpha }}$$

(18)

where $T_0$ is the reference room temperature and $\mathsf{\alpha }$ is a material-specific mobility degradation constant. In contrast, the pinch-off voltage exhibits a positive temperature coefficient, which is attributable to the intrinsic carrier concentration shift. This can be approximated by:

$$V_{GSoff}\left(T\right)=V_{GSoff}\left(T_0\right)+\mathrm{\kappa }\left(T-T_0\right)$$

(19)

where $\mathrm{\kappa }$ represents the temperature coefficient of the threshold voltage. It is a well-established convention in this field that this coefficient is typically positive, which indicates that the negative $V_{GSoff}$ moves closer to zero.

By integrating these thermal dependencies into the classical square-law saturation model for the self-biased configuration (where $V_{GS}=-I_{dis}{R}_c$), the temperature-dependent discharge current is expressed as:

$$I_{dis}\left(T\right)={\displaystyle \frac{1}{2}}\mathrm{\mu }\left(T\right)C_{ox}{\displaystyle \frac{W}{L}}{\left[-I_{dis}\left(T\right)R_c-V_{GS\left(off\right)}\left(T\right)\right]}^2$$

(20)

The differentiation of this implicit equation with respect to temperature $T$ unveils the system’s dynamic thermal equilibrium. In the proposed topology, the self-biasing resistor $R_c$ enforces operation at a relatively high current density. In this strong-inversion saturation regime, the mobility degradation term $\partial \mathrm{\mu }/ \partial T$ strictly dominates the threshold voltage shift $\partial V_{GSoff}/\partial T$. Consequently, the derivative $\partial I_{dis}/\partial T<0$, ensuring that the overall discharge current intrinsically exhibits a negative temperature coefficient behavior. Instantaneous power dissipation has been shown to elevate the junction temperature during a high-voltage discharge event. This, in turn, has been demonstrated to result in a deterministic, self-limiting reduction in the current $I_{dis}$. This quantitative framework demonstrates that the cascaded architecture inherently suppresses thermal runaway, thereby ensuring operations remain strictly within the dynamic SOA without the intervention of external active cooling mechanisms.

• Blocking Mode ($V_{CTRL}=3.3\hspace{0.17em}\mathrm{V}/\mathrm{Logic} \mathrm{High}$)

The system transitions to Blocking Mode when the external control signal transitions to a logic high state (e.g., 3.3 V). This effectively isolates the input source from the load. As depicted in Figure 6, this transition is initiated by the activation of the optocoupler $U_1$.

Upon reception of the high-level control signal, the internal LED of $U_1$ is energized. The output stage of $U_1$, configured to drive the depletion-mode device, generates a specific bias voltage $V_{bias}$ across the gate-source terminals of the master switch $Q_1$. In contrast to conventional enhancement-mode drivers, the polarity of this bias is configured to reduce the gate potential below the source potential.

Quantitatively, the gate-source voltage $V_{GS1}$ of $Q_1$ is constrained to:

$$V_{GS1}=-V_{bias}$$

(21)

In order to ensure the reliable cutoff of the depletion-mode MOSFET, it is necessary that the magnitude of this generated bias exceed the absolute value of the device’s threshold voltage $V_{GS\left(off\right)}$, which is negative for depletion NMOS. The cutoff condition is satisfied when:

$$V_{GS1}<V_{GS\left(off\right)}<0\Rightarrow \left|-V_{bias}\right|>\left|V_{GS\left(off\right)}\right|$$

(22)

In this condition, the conductive channel of $Q_1$ is fully depleted, forcing the transistor into the cutoff region ($I_D\approx 0$).

The deactivation of the bottom-stage MOSFET $Q_1$ instigates a synchronous turn-off sequence for the upper stages $Q_2$ to $Q_n$ through a self-biasing mechanism.

• Once $Q_1$ turns off, the current path to the ground undergoes an interruption.
• Consequently, the source potential $V_{S2}$ of the second-stage MOSFET $Q_2$ (which is connected to the drain of $Q_1$) begins to rise due to the leakage current from the high-voltage side.
• The gate of $Q_2$ is clamped to a fixed potential $V_{J1}$ by the resistive divider network $R_{12}$.
• Conversely, an increase in $V_{S2}$ results in a decrease in the gate-source voltage of $Q_2$. This relationship can be expressed as $V_{GS2}=V_{J1}-V_{S2}$. It is evident that when the value of $V_{S2}$ increases to a sufficient extent, resulting in a decrease in $V_{GS2}$ to below the threshold value, $Q_2$ will transition into the cutoff region.

This mechanism propagates upward through the stack. In the steady Blocking Mode, the drain-source voltage $V_{DS}$ of each MOSFET is effectively determined by the static voltage-balancing network:

$$V_{DS\_k}\approx V_{J_k}-V_{J_{k-1}}={\displaystyle \frac{V_{IN}}{N}}$$

(23)

where $V_{IN}$ is the total DC link voltage and $N$ is the number of stages.

In this mode, the main power loop exhibits high impedance. The sole power consumption is attributable to the static leakage current that permeates the voltage-balancing resistors $R_{k2}$ and the control side of $U_1$. This configuration guarantees that the high-voltage switch can withstand the full bus voltage indefinitely while concurrently maintaining a safe, low-power standby state.

In order to comprehensively address the system’s energy profile and ensure a thorough evaluation of total losses, it is imperative to assess the static power dissipation when the circuit is operating in the standby blocking mode. In this state, the cascaded MOSFETs are driven into the cutoff region, thereby presenting a high impedance to the DC link. However, a persistent leakage path has been identified, primarily through the static voltage-balancing network.

The total standby leakage current $I_{leak}$ drawn from the high-voltage bus $V_{init}$ is the sum of two components: the current flowing through the resistive divider string $I_{string}$ and the equivalent off-state leakage current of the MOSFET stack $I_{DSS\_leak}$. Because the design dictates that $I_{string}\ge 10\cdot I_{DSS\_leak}$ to guarantee uniform static voltage division and mitigate device dispersion, the total leakage current can be conservatively approximated by the resistive network alone:

$$I_{leak}\approx I_{string}={\displaystyle \frac{V_{init}}{{\sum }_{k=1}^N{R}_{k2}}}={\displaystyle \frac{V_{init}}{N\cdot R_{k2}}}$$

(24)

Consequently, the steady-state static power loss ${ P}_{leak}$, which dissipates continuously by the topology during the high-voltage blocking phase, is calculated as follows:

$$P_{leak}=V_{init}\cdot I_{leak}\approx {\displaystyle \frac{V_{init}^2}{N\cdot R_{k2}}}$$

(25)

2.3. Design Considerations

The reliability and performance of the proposed high-voltage discharge topology are contingent upon the precise selection of core components. The design rationale for the depletion-mode MOSFETs, voltage-balancing network, isolation interface, and current-limiting elements is detailed below.

2.3.1. Depletion-Mode MOSFETs

The selection of the power transistors is governed by three primary constraints: breakdown voltage $B{V}_{DSS}$, saturation drain current $I_{DSS}$, and the safe operating area.

• Voltage Rating: Reliability is contingent upon the breakdown voltage of each stage exceeding the theoretical distributed voltage $V_{IN}/n$ by a safety margin of at least 20%. Consequently, the device is selected in such a manner that $B{V}_{DSS}>1.2\cdot \left(V_{I{N}_{max}}/n\right)$. The utilization of identical devices for both the master stage, designated as $Q_1$, and the slave stages, ranging from $Q_2$ to $Q_n$, is implemented to ensure uniform thermal and electrical characteristics.
• Linear Mode Capability: It is imperative that the MOSFETs possess a robust DC SOA, given that the circuit operates in the saturation region during the discharge phase and functions as a constant current source. Devices that have been optimized for linear applications or those with a low thermal resistance junction-to-case $R_{\mathrm{\theta }JC}$ are preferred to prevent thermal runaway caused by simultaneous high voltage and current stress.
• Threshold Voltage: The pinch-off voltage must be sufficiently negative (typically ranging from −1.0 to −3.5 volts) to provide a clear distinction between the conducting state and the blocking state. This must be achieved while remaining within the drive capability of the optocoupler circuit.

2.3.2. Voltage-Balancing Network

The passive balancing network plays a critical role in mitigating the effects of parameter mismatch among the cascaded devices [45].

• Static Balancing Resistors $R_{k2}$

These resistors ensure uniform voltage division in the steady-state Blocking Mode. The resistance value is determined by a trade-off between leakage loss and balancing efficacy. It is imperative that the current flowing through the resistor string, denoted here as $I_{string}$, is at least 5 to 10 times larger than the maximum drain-source leakage current $I_{DSS\_leak}$ of the MOSFETs at elevated temperatures.

$$R_{k2}\le {\displaystyle \frac{V_{IN}/n}{10\cdot I_{DS{S}_{leak}}}}$$

(26)

• Dynamic Balancing Capacitors $C_{k2}$

During the transient switching phases (i.e., discharge to blocking or vice versa), parasitic capacitances $C_{oss}$ can induce substantial voltage imbalances. The parallel capacitors, denoted by $C_{k2}$, are selected to dominate these parasitics. A prevailing principle in the field suggests that the balancing capacitance should be considerably larger than the device’s output capacitance.

$$C_{k2}>10\cdot C_{oss\left(max\right)}$$

(27)

This ensures that the voltage distribution during transients is governed by the external capacitors rather than the nonlinear intrinsic capacitances of the MOSFETs.

2.3.3. Control Interface and Isolation

The control stage bridges the low-voltage logic and the high-voltage power loop.

• Photovoltaic-Output Optocoupler $U_1$

Conventional gate drive optocouplers necessitate an external secondary power rail; however, $U_1$ is selected as a photovoltaic-output optocoupler. The device’s internal configuration consists of a highly efficient Gallium Aluminum Arsenide (GaAlAs) infrared LED optically coupled to a series-connected photodiode array [46]. Upon activation, the photodiode array functions as an isolated voltage source, generating an open-circuit voltage $V_{OC}$ that exceeds 7 V. This voltage magnitude provides a robust safety margin for driving the gate-source voltage $V_{GS}$ of the depletion-mode MOSFET well below its negative cutoff threshold $V_{GS\left(off\right)}$, which is typically −1.5 V to −3.5 V. This ensures a reliable blocking mode. The device also offers superior galvanic isolation, effectively decoupling the control logic from high-voltage transients.

• Gate-Source Impedance Matching Resistor $R_b$

The selection of $R_b$ is strictly constrained by the output characteristics of the photovoltaic coupler. Given the inherent limitations of the photodiode array’s drive capability, typically ranging from microamps, it is essential to ensure sufficient load impedance to prevent voltage collapse. A resistor in the mega-ohm class is selected for $R_b$ (e.g., 1 or 5 MΩ). This high resistance reduces the leakage current drawn from $U_1$, enabling the gate voltage to reach the required cutoff level (>7 V) during the Blocking Mode. Conversely, when the control signal is removed, the photovoltaic output ceases. In this configuration, $R_b$ serves as the discharge path for the gate-source capacitance $C_{gs}$. This ensures that the gate-source voltage $V_{GS}$ relaxes to zero potential, thereby enabling the passive activation of the depletion-mode MOSFET $Q_1$.

2.3.4. Current-Limiting Resistor

The resistor $R_c$ fulfills two distinct functions: current programming and thermal management. As elucidated in Section 3.1, $R_c$ establishes the negative feedback that stabilizes the discharge current $I_{dis}$. The value of the discharge is determined by the target discharge time $T_{dis}$ and the desired current $I_{dis}$ as illustrated in Equation (8). During the discharge event, the resistor dissipates a portion of the stored energy. It is imperative that the power resistor possesses a high pulse-load capability. Non-inductive wirewound or thick-film power resistors are preferred to minimize parasitic inductance, which could induce oscillation during the fast turn-on transient.

3. Simulation Analysis

3.1. Simulation Setup and Nominal Performance

A detailed simulation study was conducted to validate the theoretical analysis presented in Section 2 and to comprehensively evaluate the dynamic performance of the proposed circuit. The implementation of the simulation model was executed within the PSIM 2025.0 software environment. The comprehensive simulation schematic of the proposed high-voltage safety discharge topology is illustrated in Figure 7.

The configuration of the simulation setup is designed to replicate critical operating conditions, including the static high-voltage blocking state and the transient constant-current discharge phase. To ensure the fidelity of the results, the Infineon BSP135 was selected as the specific depletion-mode MOSFET model. The selection of this device was predicated on its high breakdown voltage $B{V}_{DSS}$ and its compact SOT-223 package, in conjunction with its demonstrated reliability in established high-voltage applications. Consequently, the simulation parameters are closely aligned with the characteristics of practical hardware implementation. The key system specifications and component parameters employed in the simulation are enumerated in

Table 3. Main parameters of the simulation topology.

Category	Parameter	Symbol	Value
System Specifications	Capacitance Initial Voltage	$V_{init}$	1200 V
	Energy Storage Capacitance	$C_{store}$	220 nF
	Number of Stages	$N$	3
Power Stage (MOSFETs)	Depletion-Mode NMOS	$Q_1-Q_n$	BSP135 (Model)
Balancing Network	Static Balancing Resistor	$R_{k2}$	100 MΩ
	Dynamic Balancing Capacitor	$C_{k2}$	4.7 nF
Control and Protection	Current-Limiting Resistor	$R_c$	1 kΩ/Variable
	Gate Pull-down Resistor	$R_b$	2 MΩ
	Gate Protection Zener	$D_{k1}$	7.5 V
	Series Gate Resistor	$R_{k1}$	880 kΩ
	Optocoupler Bias Voltage	$V_{bias}$	7 V

.

In addition, to accurately simulate the transient and static behaviors of the selected depletion-mode MOSFET, the device model was meticulously configured based on its datasheet characteristics. The configuration parameters for the BSP135 model employed in the simulation are enumerated in

Table 4. Detailed simulation parameters for the BSP135 depletion-mode MOSFET.

Parameter	Value
Drain-Source Breakdown Voltage $B{V}_{DSS}$	600 V
On-State Resistance $R_{ds\left(on\right)}$	30 Ω
Threshold Voltage $V_{GS\left(off\right)}$	−1.4 V
Transconductance $g_{fs}$	0.16 S
Capacitance $C_{gs}$	94.6 pF
Capacitance $C_{gd}$	3.4 pF
Capacitance $C_{ds}$	5.1 pF
Diode Forward Voltage $V_{SD}$	0.78 V

.

The dynamic response of the proposed topology during the safety discharge phase is evaluated by initiating a control signal transition ($V_{CTRL}$ set to logic low). The ensuing discussion will focus on the simulation results corresponding to an initial bus voltage of 1200 V and a load capacitance of 220 nF. These results are presented in Figure 8.

As illustrated in Figure 8a, the transient voltage waveforms at the inter-stage nodes $V_{J1}$ to $V_{J3}$ are presented. The node voltages undergo a synchronous decrease, thereby ensuring the maintenance of equal spacing throughout the discharge process. This finding serves to substantiate the efficacy of the balancing network in mitigating overvoltage stress on a per-MOSFET stage basis. The discharge curves manifest a unidirectional linear slope, contrasting with the exponential decay characteristic of passive resistor bleeders. This linearity indicates that the discharge current remains constant, effectively independent of the decreasing bus voltage.

As illustrated in Figure 8b, the gate-source voltage $V_{GS}$ dynamics of the cascaded MOSFETs $Q_1$ to $Q_3$ are revealed, unveiling the mechanism of the self-biased constant current operation. During the 0 to 0.2 s time interval, the circuit operates in constant-current mode, with each transistor’s gate-source voltage $V_{GS}$ maintaining a stable negative plateau. This negative bias is generated by the voltage drop across the source resistor $R_c$, which clamps the device in saturation to regulate the discharge current. The discharge process is complete after 0.2 s. When the stored energy is depleted, the discharge current ceases, and the negative feedback voltage across $R_c$ disappears. Consequently, the voltage across the primary switch $Q_1$ reverts to zero. A negligible amount of residual negative bias persists across some MOSFETs due to charge retention effects in the output capacitance. However, this potential remains significantly above the cutoff threshold $V_{GS\left(off\right)}$, thereby ensuring the device remains in the on state for subsequent cycles.

The system successfully discharges the 220 nF capacitor bank from 1200 V to a safe voltage level (near 0 V) in approximately 0.2 s when the current-limiting resistor $R_c$ is set to 1 kΩ. This outcome underscores the circuit’s capacity to facilitate expeditious and foreseeable safety discharging.

3.2. Programmability and Mode Transition

A parametric sweep analysis was conducted on the current-limiting resistor $R_c$ to verify the programmability of the discharge current and its impact on the safety discharge time. The resistance value was systematically increased from 0.1 kΩ to 5 kΩ. The simulation results are outlined in Figure 9.

As illustrated in Figure 9a, the bus voltage decay profiles vary with different $R_c$ values. It was observed that the discharge curves maintain a strict linear decay characteristic across the entire range of resistances. This finding indicates that the topology maintains robust constant-current operation, irrespective of the specific current setpoint. The discharge duration demonstrates a direct correlation with the resistance value. As the resistance $R_c$ increases, the slope of the discharge curve becomes shallower, leading to a prolonged discharge time. This finding indicates that the safety time window can be meticulously customized by selecting the appropriate $R_c$ value to align with specific system requirements.

As illustrated in Figure 9b, the corresponding discharge current $I_{dis}$ waveforms are depicted. The simulation results unequivocally demonstrate that the magnitude of the constant discharge current is inversely modulated by $R_c$. The waveforms manifest as stable, unvarying plateaus, suggesting that the negative feedback mechanism (source degeneration) effectively compensates for the fluctuating drain-source voltage during the discharge process. The relationship between the steady-state current amplitude and $R_c$ aligns with the theoretical model derived in Equation (8). For instance, an increase in $R_c$ from 0.1 kΩ to 5 kΩ results in a proportional reduction in the discharge current, thereby validating $R_c$ as an effective programming element for the discharge rate.

In order to validate the mode transition capability and the system’s rapid response to an emergency shutdown command, a transient simulation of the switching sequence was performed. The control signal $V_{CTRL}$ transitioned from a Logic High state, also referred to as Blocking Mode, to a Logic Low state, otherwise termed Discharge Mode, at a precise time instant $t = 0.5 \mathrm{s}$. The resulting dynamic waveforms of the bus voltage $V_{init}$ and the discharge current $I_{dis}$ are plotted in Figure 10.

Prior to the specified time frame, the circuit functions in a state of Blocking Mode, during which the discharge current is effectively negligible, and the high voltage remains constant. At the moment of signal removal, the system exhibits an immediate response. The discharge current $I_{dis}$ exhibits a pronounced increase, reaching its steady-state value with minimal delay. This rapid activation process serves to confirm the fast intrinsic switching speed of the depletion-mode MOSFETs. Subsequent to the activation, the bus voltage undergoes a linear decay, decreasing from an initial 1200 V to a safe voltage level (near 0 V) over a duration of approximately 0.2 s. Throughout the specified discharge window, the value of $I_{dis}$ ranges from 0.5 to 0.7 s, exhibiting consistent stability, with no discernible oscillatory tendencies or overshoot.

The simulation results unequivocally demonstrate the circuit’s ability to seamlessly transition from the standby blocking state to the active safety discharge state. The absence of current spikes during the transition, in conjunction with the linearity of the voltage drop, serves to further validate the design of the self-biased control loop.

3.3. Sensitivity Analysis of Intrinsic Parameters

In order to validate the theoretical sensitivity model derived in Section 2.2 and assess the system’s robustness against semiconductor manufacturing tolerances, a parametric sweep analysis was conducted. The master depletion-mode MOSFET $Q_1$ was subjected to variations in its core intrinsic parameters, namely the pinch-off voltage $V_{GSoff}$ and the zero-bias saturation current $I_{DSS}$. The current-limiting resistor was maintained at 1 kΩ and the bus voltage at 1200 V. The corresponding variations in the total discharge time $T_{dis}$ are illustrated in Figure 11.

As illustrated in Figure 11a, $V_{GSoff}$ was swept from $-2.1 \mathrm{V}$ to $-1.0 \mathrm{V}$ to simulate extreme gate threshold dispersion. While the absolute discharge time $T_{dis}$ displays a nonlinear increase as $V_{GSoff}$ becomes less negative, the proportional variation strictly adheres to the mathematical boundaries established by the theoretical model. It has been demonstrated that the self-biasing feedback acts as an attenuation factor, thereby constraining the fractional change in $T_{dis}$. This finding provides empirical validation that the magnitude of the relative sensitivity coefficient is strictly less than unity ($\left|S_{V_{GSoff}}^{T_{dis}}\right|<1$).

As illustrated in Figure 11b, the stabilizing effect of the source degeneration mechanism is most evident when $I_{DSS}$ is swept across a range from $0.02 \mathrm{A}$ to $0.08 \mathrm{A}$, simulating severe batch-to-batch dispersion and high-temperature thermal drift. According to the analytical model derived in Equation (12), the theoretical relative sensitivity coefficient $S_{I_{DSS}}^{T_{dis}}$ at the nominal operating point is approximately −0.06.

The simulation results precisely mirror this theoretical quantitative prediction. As illustrated in Figure 11b, a decrease in $I_{DSS}$ from $0.02 \mathrm{A}$ to $0.08 \mathrm{A}$ leads to a conspicuously narrow variation in the discharge time, increasing it from approximately 0.193 s to 0.203 s—a minor deviation of approximately 5%. This quantitative alignment between the theoretical sensitivity function and the empirical parametric sweep conclusively proves that the proposed topology inherently desensitizes the discharge process against intrinsic parameter fluctuations. Consequently, the safety timing remains deterministic and reliable under extreme device degradation or severe thermal drift.

In order to unequivocally establish the fail-safe reliability of the proposed topology, a rigorous Worst-Case Circuit Analysis (WCCA) is mathematically formulated. The objective is to derive the absolute maximum discharge time $T_{dis\left(max\right)}$ under the most severe combination of parametric tolerances and environmental drifts.

The fundamental discharge time is determined by the energy storage capacitance $C_{store}$, the initial bus voltage $V_{init}$, the safe-touch voltage threshold $V_{safe}$, and the regulated discharge current $I_{dis}$. The extreme boundary condition that maximizes the discharge time is characterized by the capacitive load and initial voltage being at their upper tolerance limits, while the discharge current is at its absolute minimum. This is mathematically defined as:

$$T_{dis\left(max\right)}={\displaystyle \frac{C_{store}\left(1+{\mathrm{\delta }}_C\right)\left[V_{init}\left(1+{\mathrm{\delta }}_V\right)-V_{safe}\right]}{I_{dis\left(min\right)}}}$$

(28)

where ${\delta }_C$ and ${\delta }_V$ represent the maximum positive fractional tolerances of the bus capacitor and the charging voltage, respectively.

In order to calculate $I_{dis\left(min\right)}$, it is necessary to apply the boundary conditions to the intrinsic parameters according to Equation (11). These are the maximum source degradation resistance $R_{c\left(max\right)}=R_c\left(1+{\mathrm{\delta }}_R\right)$, the minimum zero-bias saturation current $I_{DSS\left(min\right)}$ (accounting for mobility degradation at high temperatures), and the minimum cutoff voltage $V_{GSoff\left(min\right)}$ (which determines the earliest channel cutoff).

$$I_{dis\left(min\right)}=I_{DSS\left(min\right)}{\left(1+{\displaystyle \frac{I_{dis\left(min\right)}{R}_{c\left(max\right)}}{V_{GSoff\left(min\right)}}}\right)}^2$$

(29)

The performance limits of the system are derived by substituting the extreme boundary parameters established in

Table 5. Parameter Boundaries and Statistical Distributions for WCCA and Monte Carlo Analysis.

Parameter	Symbol	Nominal Value	WCCA Boundary (for ${\mathit{T}}_{\mathit{d}\mathit{i}\mathit{s}\left(\mathit{m}\mathit{a}\mathit{x}\right)}$)	Monte Carlo Distribution
Capacitance Initial Voltage	$V_{init}$	1200 V	$+5\%$	Gaussian ($+5\%$, $3\sigma$)
Energy Storage Capacitance	$C_{store}$	220 nF	$+20\%$	Gaussian ($20\%$, $3\mathrm{\sigma }$)
Threshold Voltage	$V_{GS\left(off\right)}$	−1.4 V	−1.0 V	Uniform (−2.1 V to −1.0 V)
Saturation Current	$I_{DSS}$	80 mA	20 mA	Uniform (20 mA to 100 mA)
Static Balancing Resistor	$R_{k2}$	100 MΩ	N/A	Gaussian ($+5\%$, $3\sigma$)
Dynamic Balancing Capacitor	$C_{k2}$	4.7 nF	N/A	Gaussian ($+20\%$, $3\sigma$)
Current-Limiting Resistor	$R_c$	1 kΩ	$+5\%$	Gaussian ($+5\%$, $3\sigma$)
Bus Inductance	$L_{bus}$	0	N/A	Uniform (20 nH to 100 nH)

into the derived explicit analytical model. In accordance with nominal conditions and typical component values, the baseline discharge time of the proposed topology is calculated to be 0.215 s. However, when all component tolerances, high-temperature mobility degradation, and pinch-off voltage variations are simultaneously skewed to their most adverse extremes, the comprehensive Worst-Case Circuit Analysis mathematically proves that the maximum discharge time, $T_{dis\left(max\right)}$, extends to 0.434 s.

3.4. Statistical Reliability via Monte Carlo Analysis

While the WCCA establishes the absolute deterministic boundaries, a Monte Carlo analysis provides the probabilistic yield and statistical distribution of the discharge performance under complex non-idealities. In order to develop this analysis mathematically in full, the component parameters are modeled as continuous random variables following the probability density functions defined in Table 3.

The specified Gaussian tolerances are mapped to a $\pm 3\mathrm{\sigma }$ sigma confidence interval, ensuring a 99.73% statistical coverage. Furthermore, in order to address the impact of printed circuit board (PCB) layout variations, a bus inductance $L_{bus}$ is modeled with a uniform distribution and injected into the high-voltage loop.

It is asserted that, in accordance with the statistical framework, a multi-variable Monte Carlo simulation is to be executed, encompassing 500 iterations. As illustrated in Figure 12, the resultant discharge times adhere to a well-defined normal distribution. The statistical mean ${\mathrm{\mu }}_{tdis}$ of the discharge time is 0.203 s, with a standard deviation ${\mathrm{\sigma }}_{tdis}$ of 0.047 s. The detailed statistical histogram reveals that the probability of the discharge time exceeding the 2.0 s safety limit is mathematically negligible.

Furthermore, transient waveform monitoring during the 500 iterations confirmed that the random injection of $L$ did not induce catastrophic high-frequency ringing or undamped oscillations. The localized gate-source clamping networks $D_{k1}$ and series damping resistors $R_{k1}$ effectively absorbed the transient $Ldi/dt$ spikes, ensuring the cascaded MOSFETs remained strictly within their dynamic Safe Operating Area (SOA).

4. Experimental Verification

4.1. Experimental Setup and Prototype Implementation

In order to experimentally validate the performance and reliability of the proposed safety discharge topology, a compact high-voltage short pulse generator was developed to serve as the application testbed, as shown in Figure 13. This system generates the requisite high-voltage bus potential, thereby establishing the operational environment for the discharge circuit.

As illustrated in Figure 13a, the fabricated hardware assembly comprises multiple components. This system integrates low-voltage control logic with a high-voltage boost stage within a minimized PCB footprint. The core high-voltage generation section employs a flyback converter topology, as illustrated in the simplified schematic shown in Figure 13b. The application of a PWM signal to the primary-side switch Q1 results in an augmentation of the low-voltage input through transformer T1, which is subsequently rectified by diode D1. This process facilitates the charging of the energy storage capacitor C1; all relevant components are surface-mount devices to achieve a compact design. Figure 13c offers experimental validation of the dynamic boost characteristics of this stage. The charging curve demonstrates that the bus voltage successfully attains the target high-voltage level of 1200 V within a charging time of 0.3 s. Upon completion of the charging cycle, the system can be programmed to generate the high-intensity short pulse. The short-circuit discharge waveform is illustrated in Figure 13d. The resulting output exhibits a rapid voltage collapse accompanied by a peak discharge current of approximately 1500 A (with typical ringing, a characteristic of underdamped RLC pulse discharge). This test platform effectively provides the extreme electrical stresses necessary to verify the robustness and fast response characteristics of the integrated safety discharge circuit.

Subsequent to the simulation analysis, a hardware prototype of the proposed safety discharge topology was fabricated in order to verify its practical performance. The selection of critical components, including the depletion-mode MOSFETs, the voltage-balancing network, and the photovoltaic driver, adheres to the design specifications listed in Table 3.

The experimental test bench is illustrated in Figure 14. The configuration of the setup is designed to assess the circuit’s performance under actual high-voltage conditions.

• Prototype Assembly: The discharge circuit is implemented on a custom printed circuit board (PCB) and integrated with the compact pulse generator described in Section 4.1.
• The process of signal synchronization is defined as follows: A dedicated pulse-width modulation (PWM) controller orchestrates the system timing. The system generates control signals to manage the charging phase (via the pulse generator’s flyback circuit) and the discharging phase (via the proposed topology’s optocoupler interface), ensuring a transition between blocking and discharge modes.
• Data Acquisition: The transient voltage response across the energy storage capacitor is monitored using a digital oscilloscope (Tektronix TBS2104B from Tektronix, Beaverton, OR, USA) equipped with a 500:1 high-voltage passive probe (PINTEON PT-5240 from Guangzhou PINTEON, China).
• Power Source: The regulated DC power supplies (Agilent E3632A from Agilent Technologies, Santa Clara, CA, USA and WANPTEK WPS305H from Shenzhen Guce Electronic Technology, Shenzhen, China) provide the low-voltage input for the pulse generator’s boost stage and the logic controller separately.

4.2. Comparative Discharge Performance and Programmability

To comprehensively evaluate the effectiveness of the proposed architecture, an experimental comparative analysis was conducted. As illustrated in Figure 15, based on the analysis of the discharge mechanism, we designed three distinct discharge configurations for the testbed and compared them under identical high-voltage load conditions:

• Passive Resistor: This approach is considered a standard passive discharging method. In order to guarantee that the velocity and efficacy of the high-voltage charging process would not be adversely affected by excessive continuous leakage current, the passive bleeder resistance was selected to match the resistance value of the static voltage-balancing network utilized in the proposed topology, specifically 100 MΩ.
• Active IGBT Bleeder: This active configuration utilizes a 1600 V power IGBT as the primary discharging device, coupled with an operational amplifier that functions as the constant-current control unit. In order to ensure an evaluation of performance under equivalent conditions, the input of the operational amplifier was calibrated so that the IGBT’s discharge current matched the discharge rate of the proposed circuit. This configuration is contingent upon a continuous 12 V auxiliary power supply to function optimally.
• Proposed Topology: The self-biased cascaded architecture developed in this study. In order to validate the constant-current discharge capability and the programmability of the proposed topology, a series of discharge tests were conducted by varying the current-limiting resistor ${\mathrm{R}}_{\mathrm{c}}$. The selection of resistance values was made to encompass a broad spectrum of discharge currents, ranging from 4.7 kΩ to 220 Ω.

The comparative oscilloscope waveforms of the bus voltage decay profiles are presented in Figure 16, providing an experimental validation of the discharge methods. As illustrated in Figure 16a–d, the proposed topology demonstrates a linear voltage decline across all tested configurations. This linearity serves to confirm the constant-current discharge capability that is inherent to the cascaded depletion-mode NMOS architecture. In addition, the subfigures illustrate the programmability of the proposed circuit. By adjusting the source limiting resistor $R_c$, from 4.7 kΩ down to 220 Ω, the discharge time can be flexibly tuned from 1.02 s to 72.0 ms.

In order to underscore the merits of the proposed topology, a comparative analysis was conducted against both traditional active and passive bleeder circuits. While the active IGBT bleeder (Figure 16e) also achieves a linear, constant-current discharge with a comparable speed of 75.2 milliseconds, its flaw lies in its power dependency. In the context of a total power loss scenario, the active IGBT bleeder is rendered non-functional. In contrast, the proposed topology employs a 3.3 V control signal to ensure the maintenance of the blocking state during standard operation. In the event of power loss, the depletion-mode devices inherently revert to their normally-on state, executing the safety discharge entirely without external power. Finally, the traditional passive bleeder (Figure 16f) is characterized by a pronounced exponential long-tail decay, dictated by the RC time constant. Utilizing a 100 MΩ resistor necessitates a duration of 53.3 s to attain a safe voltage limit.

In order to provide a quantitative assessment, the voltage drop $\mathrm{\Delta }V$ and the discharge time $T_{dis}$ were extracted from the oscilloscope cursors in Figure 16. The experimental average discharge current $I_{dis}$ was subsequently determined through the application of Equation (8). The measured data and calculated currents, which summarize the superior speed and power-loss resilience of the proposed topology, are presented in

Table 6. Summary of experimental discharge data and calculated current.

Discharge Method	Auxiliary Power Input During Blocking Process	Auxiliary Power Input During Discharge Process	Limiting Resistor	Measured Voltage Drop $\Delta \mathit{V}$	Measured Discharge Time ${\mathit{T}}_{\mathit{d}\mathit{i}\mathit{s}}$	Calculated Discharge Current ${\mathit{I}}_{\mathit{d}\mathit{i}\mathit{s}}$
Proposed Topology	3.3 V	0	$R_c=4.7\hspace{0.17em}\mathrm{k}\mathrm{\Omega }$	1.18 kV	1.02 s	0.24 mA
Proposed Topology	3.3 V	0	$R_c=1.5\hspace{0.17em}\mathrm{k}\mathrm{\Omega }$	1.18 kV	424 ms	0.61 mA
Proposed Topology	3.3 V	0	$R_c=680 \mathrm{\Omega }$	1.17 kV	172 ms	1.50 mA
Proposed Topology	3.3 V	0	$R_c=220 \mathrm{\Omega }$	1.16 kV	72.0 ms	3.54 mA
Active IGBT Bleeder	0	12 V	/	1.18 kV	75.2 ms	3.45 mA
Active IGBT Bleeder	0	0	/	Cannot Function
Passive Resistor	0	0	$R_{bleed}=100\hspace{0.17em}\mathrm{M}\mathrm{\Omega }$	1.16 kV	53.3 s	4.95 μA (average)

.

In order to validate the proposed constant-current discharge mechanism, a comparative analysis was performed among theoretical models, simulations, and hardware measurements. As illustrated in Figure 17, the discharge current $I_{dis}$ is presented as a function of the programming resistor $R_c$. The downward trajectory observed in both the theoretical derivation (Equation (6)) and the simulation results confirms the fundamental inverse relationship between the programming resistance and the regulated current when the depletion-mode MOSFETs operate in the saturation region.

An analysis of the experimental data (black squares) reveals trend consistency with the ideal models. However, a slight but systemic downward deviation is observable, where the experimental discharge currents are marginally lower than the theoretical predictions. This negative offset can be attributed to several practical physical factors inherent in the hardware assembly:

• Parasitic Series Resistance: The theoretical model posits an ideal $R_c$. In the fabricated prototype, the equivalent series resistance of the high-voltage capacitor, the PCB trace impedance, and the contact resistances of the wiring introduce an additive parasitic term. This increased effective source resistance inevitably strengthens the negative feedback loop of the MOSFET, further restricting the steady-state discharge current and pulling the experimental data points downward.
• Device Parameter Spread: The discrete BSP135 MOSFETs employed in the prototype inherently manifest manufacturing tolerances in critical parameters, such as the zero-gate-voltage drain current and pinch-off voltage, which may deviate slightly from the standardized SPICE model parameters.
• Capacitor Tolerance Propagation: As the experimental average current is calculated indirectly from the measured discharge time, the tolerance in the physical high-voltage capacitor will mathematically propagate as a lower calculated current.

4.3. Repeatability Testing and Statistics

To evaluate the statistical consistency and repeatability of the physical hardware’s endurance, an automated cyclical test was performed. The PWM controller alternated continuously between the high-voltage charging phase and the active discharging phase for 100 cycles. The tests were conducted using the $R_c$ = 220 Ω configuration to enable quick discharging.

Figure 18a shows a portion of the continuous oscilloscope recording from this automated test. It demonstrates reliable mode transitions without triggering ringing or system failure. To establish a performance benchmark, a 100-cycle endurance test was conducted on the proposed cascaded topology and the IGBT-based active bleeder.

The discharge time $T_{dis}$ for each cycle was recorded and plotted in Figure 18b. The extracted data reveals two behavioral trends.

• Proposed topology: The discharge time was uniform across 100 iterations. The physical hardware yielded a mean of 73.36 ms and a standard deviation of 0.98 ms.
• IGBT bleeder: The active IGBT circuit demonstrated pronounced upward thermal drift. Over 100 cycles, the discharge time increased from approximately 73 ms to over 82 ms.

4.4. Robustness Against Parameter Dispersion

A component replacement experiment was conducted to validate the theoretical sensitivity models and prove the circuit’s robustness against manufacturing dispersion. Standard commercial depletion-mode MOSFETs exhibit variation in their pinch-off voltage $V_{GSoff}$ from batch to batch. To evaluate the impact of this variation, MOSFET samples with different $V_{GSoff}$ values were systematically installed in the $Q_1$ position of the prototype.

The discharge time $T_{dis}$ was recorded for each sample and plotted alongside the theoretical prediction and the parametric sweep simulation results. As shown in Figure 19, the experimental measurements align somewhat with the theoretical curve. The discharge time $T_{dis}$ varied from 60.0 ms to 72.0 ms as the $V_{GSoff}$ fluctuated from −1.61 V to −1.26 V.

Notably, there is a systematic deviation between the simulation curve and the physical/theoretical data. This discrepancy can be attributed to the difference between the software model of the BSP135 device and its actual physical components. The software model’s idealized transconductance and default saturation characteristics differ from those of the real-world hardware, resulting in a faster simulated discharge rate. However, the nonlinear trend across all three curves verifies the core self-biasing mechanism.

4.5. Thermal Stability Testing

A thermal chamber test was conducted to evaluate the thermal stability and validate the theoretical temperature-dependent characteristics of the proposed topology. The prototype was placed in a temperature testing chamber and the temperature was systematically increased from 25 °C to 80 °C. The discharge time $T_{dis}$ was measured at each temperature checkpoint. The experimental results are summarized in

Table 7. Experimental Discharge Characteristics Under Varying Ambient Temperatures.

Ambient Temperature	Measured Voltage Drop $\Delta \mathit{V}$	Measured Discharge Time ${\mathit{T}}_{\mathit{d}\mathit{i}\mathit{s}}$	Calculated Discharge Current ${\mathit{I}}_{\mathit{d}\mathit{i}\mathit{s}}$
25 °C	1.16 kV	72.0 ms	3.54 mA
40 °C	1.17 kV	76.2 ms	3.38 mA
60 °C	1.17 kV	82.8 ms	3.11 mA
80 °C	1.18 kV	91.0 ms	2.85 mA

.

As the ambient temperature increased to 80 °C, the discharge current $I_{dis}$ decreased from 3.54 mA to 2.85 mA. This led to a proportional extension of the discharge time $T_{dis}$. This empirical data aligns with the dynamic thermal equilibrium. In the strong-inversion saturation regime, which is maintained by the self-biasing resistor $R_c$, the reduction in carrier mobility $\mathrm{\mu }\left(T\right)$ due to enhanced acoustic phonon scattering strictly dominates the threshold voltage shift. Consequently, the overall discharge current intrinsically exhibits a negative temperature coefficient. This characteristic serves as a self-limiting safety mechanism that reduces dynamic power dissipation at elevated temperatures.

In addition to the ambient temperature sweep, an extreme operational fault condition was evaluated in which both the high-voltage charging module and the safety discharge circuit were engaged simultaneously. As illustrated in Figure 20a, the proposed topology effectively overpowers the charging circuit, ensuring the bus voltage is safely clamped at a stable intermediate level, rather than inducing a thermal breakdown. The cascaded MOSFETs effectively function within the linear region, continuously dissipating the incoming power until the PWM signal is terminated.

Furthermore, an infrared thermal imager was used to evaluate the steady-state thermal distribution during this high-dissipation equilibrium. Figure 20b shows that the maximum PCB surface temperature was 50.7 °C when operated at an ambient temperature of 23.5 °C. These results confirm that the prototype can safely navigate the high-stress region without violating the devices’ Safe Operating Area (SOA) limits.

5. Discussion

The experimental outcomes presented in this study corroborate the working hypothesis that a self-biased, cascaded depletion-mode MOSFET topology can effectively function as a reliable high-voltage safety discharge mechanism. The physical robustness of the theoretical models has been validated through a systematic evaluation of the prototype. This evaluation included nominal operation, cycle endurance testing, parameter replacement, and ambient temperature sweeps.

In order to quantitatively assess the advantages of the proposed architecture, an experimental benchmarking analysis was performed against two standard solutions: an active enhancement-mode bleeder (utilizing a 1600 V IGBT and operational amplifier) and a passive resistive bleeder. A synopsis of the comparative performance is presented in

Table 8. Experimental Benchmarking and Discharge Speed Density Comparison.

Discharge Method	Discharge Profile	Minimum Discharge Time Measured	Aux Power Required	Prototype Dimensions (Package Info)	Discharge Speed Density ${\mathbf{\rho }}_{\mathit{d}\mathit{i}\mathit{s}}={\mathit{v}}_{\mathit{d}\mathit{i}\mathit{s}}/{\mathit{V}}_{\mathit{e}\mathit{f}\mathit{f}}$	Features
Proposed Topology	Linear	60.0 ms	0	31 × 48 × 10 mm3 (SOT-223 x3)	1344 V/s/cm3	Fail-safe
Active IGBT Bleeder	Linear	71.6 ms	12 V input	30 × 24 × 30 mm3 (TO247-3)	775 V/s/cm3	Fails without aux power
Passive Resistor	Exponential	53.3 s	0	14 × 10 × 10 mm3 (R2512)	16.08 V/s/cm3	Passive and uncontrollable

.

As indicated in Table 8, passive bleeders are distinguished by their exponential decay tails and consequent protracted safety hazards, which contravene the imperative for rapid-discharge safety measures. While the passive method is characterized by its fail-safe nature, its discharge speed density is significantly low. In contrast, the IGBT active bleeder aligns with the linear decay and velocity of the proposed topology. However, it introduces vulnerabilities, such as its dependence on an auxiliary supply, rendering it ineffective in scenarios of power loss.

The proposed self-biased topology has been demonstrated to effectively address these trade-offs. It is imperative to note that the constant discharge current is governed by the source feedback resistor $R_c$. This behavior is consistent with the Shockley equation for depletion-mode devices operating in the saturation region, as evidenced by the linearity of the experimental voltage–time profiles. The elimination of auxiliary power supplies and external gate drivers results in a minimized physical footprint. This, in turn, yields an approximate high discharge speed density of 1344 V/s/cm³.

Additionally, the programmability of the discharge rate, as demonstrated by the parametric variation of $R_c$, offers a distinct advantage over fixed-resistance solutions. This capability enables engineers to optimize the balance between discharge speed and thermal dissipation, tailored to the specific energy storage constraints of the system under design. Of particular significance is the transition from the blocking mode to the discharge mode, which is initiated by the removal of the logic control signal. This transition serves to validate the fail-safe functionality of the design. This activation protocol is designed to ensure that the system automatically transitions to a safe state in the event of a power loss or control failure.

The proposed circuit provides an effective methodology by utilizing a cascaded configuration. This configuration enables the use of depletion-mode MOSFETs with breakdown voltages significantly lower than the total bus voltage as primary discharge devices. This architectural approach circumvents the necessity of employing bulky, large-packaged ultra-high-voltage switching devices, thereby substantially reducing the physical volume and cost of the safety discharge circuit. Consequently, the topology is well-suited for integration into compact, miniaturized pulse generators.

The demonstration of the versatility of the approach under consideration is facilitated by

Table 9. Theoretical Design Parameters of the Proposed Discharge Circuit for Various Pulse Generators.

Reference	Application	Stored Energy Parameters (${\mathit{V}}_{\mathit{i}\mathit{n}\mathit{i}\mathit{t}}$/${\mathit{C}}_{\mathit{s}\mathit{t}\mathit{o}\mathit{r}\mathit{e}}$)	Proposed MOSFET Model ($\mathit{B}{\mathit{V}}_{\mathit{D}\mathit{S}\mathit{S}}$)	Stages N	Target ${\mathit{I}}_{\mathit{d}\mathit{i}\mathit{s}}$/${\mathit{t}}_{\mathit{d}\mathit{i}\mathit{s}}$
[6]	Electroporation	4 kV/125 μF	IXTA6N100D2 (1200 V)	4	1 A/0.5 s
[47]	Tumor Treatment	2 kV/20 μF	DN2470K4-G (700 V)	3	50 mA/0.8 s
[48]	Plasma Jet	1 kV/160 nF	BSP135 (600 V)	2	1 mA/0.16 s

, which provides the theoretical design parameters for the implementation of the proposed discharge circuit with various pulse generators as reported in the extant literature. However, it is imperative to acknowledge that the specific control logic and targeted discharge speed must be meticulously tailored and adjusted according to the precise design objectives and energy constraints inherent to the individual pulse generator system.

While the current study validates the self-biased discharge mechanism, future research endeavors will focus on the following directions to further expand the topology’s capabilities:

• Application of SiC Devices: Investigating the implementation of the proposed topology using Silicon Carbide (SiC) depletion-mode devices. This will enable the circuit to accommodate higher bus voltages, scaling into the tens of kilovolts regime, by leveraging the superior high-voltage and thermal characteristics of wide-bandgap materials.
• Verification of Higher-Stage Scaling: The construction and experimental validation of circuits with a considerably higher number of cascaded stages is imperative. This is critical to further verify the scalability of the voltage-balancing network and the robustness of the topology under ultra-high-voltage string configurations.
• System-Level Integration and Comprehensive Testing: Developing an integrated design within a miniaturized pulse generator system. This will be coupled with more comprehensive environmental testing and extended long-term reliability testing to thoroughly assess the operational endurance of the topology in real-world field conditions.
• Component-Level Integration: Pursuing the integrated design of the repeated components within each cascaded stage. By combining the MOSFETs and the balancing passive networks, the physical volume and total component count can be further minimized, maximizing the discharge speed density for ultra-compact applications.

6. Conclusions

In this study, a novel fail-safe high-voltage safety discharge topology utilizing cascaded depletion-mode NMOS transistors was proposed, theoretically analyzed, and experimentally validated. The system’s design incorporates a self-biased architecture in conjunction with a photovoltaic-output optocoupler, ensuring an automatic, constant-current discharge in the event of a loss of control signals or system power. This configuration fulfills the requirements for fail-safe operation, bypassing the need for an auxiliary power supply.

A series of experimental evaluations were conducted on a 1200 V, 220 nF short pulse generator testbed. The proposed topology consistently achieved a linear voltage decay, successfully discharging the high-voltage load to safe levels in as little as 60.0 ms. The adjustment of the current-limiting resistor $R_c$ enables programming of the discharge current and the resultant discharge time. Additionally, the cascaded design effectively distributed high-voltage stress across small-scale packaging devices, thereby eliminating the necessity for bulky ultra-high-voltage switches. This configuration yielded a compact physical footprint (31 × 48 × 10 mm³)—a substantial enhancement over passive bleeders, which exhibited exponential decay and required 53.3 s to discharge the same load.

The proposed circuit demonstrated robust statistical consistency, parameter desensitization, and thermal stability. During a continuous endurance test, the prototype demonstrated a high degree of repeatability in its discharge time, with a mean of 73.36 milliseconds and a minimal standard deviation of 0.98 milliseconds. Thermal chamber evaluations from 25 °C to 80 °C empirically validated that the self-biasing mechanism intrinsically provides a negative temperature coefficient, safely limiting dynamic power dissipation at elevated temperatures. In scenarios involving concurrent charging and discharging, the prototype demonstrated its capacity to safely clamp the bus voltage, with the maximum surface temperature reaching a stabilized level of 50.7 °C.

This self-biased cascaded topology was demonstrated to provide a reliable, compact, and cost-effective solution for rapid energy depletion in high-voltage applications. By surmounting the constraints imposed by passive bleeders and conventional active switches, it shows potential for integration into miniaturized pulse generators. Subsequent research endeavors will investigate the scaling of the architecture to tens of kilovolts through the utilization of SiC depletion-mode devices and the advancement of its component-level integration for ultra-compact systems.