A 3.3–8.0 GHz Wideband LNA with a 0.81–1.09 dB Noise Figure in 0.15 µm GaAs pHEMT Technology

Abstract

This paper presents the design and fabrication of a wideband low-noise amplifier (LNA) covering C-band, using the 0.15 µm GaAs pHEMT process. To achieve both low noise performance and wide matching characteristics, a two-stage cascaded architecture is implemented. In the first stage, circular inductors and an inductive source degeneration technique are employed to minimize the noise figure (NF) while ensuring wideband input matching. Furthermore, an RC feedback structure is incorporated to effectively enhance the stability of the amplifier. The proposed LNA operates under a supply voltage of 3.3 V and a gate bias of 0.35 V, with a total DC power consumption of 69.3 mW. The fabricated MMIC occupies a total chip area of 1.98 mm², including the probing pads. Measurement results demonstrate that the LNA achieves an NF of 0.81–1.09 dB and a gain of over 20.1 dB in the frequency range of 3.3–8.0 GHz. The input and output return losses are maintained over 10 dB and 9.7 dB, respectively.

1. Introduction

Recent advances in radio frequency (RF) technology have enabled its widespread application in various fields, including satellite communications, fifth generation (5G) mobile infrastructure, automotive and military radar systems, and high-resolution remote sensing. Among these, the S-band (2–4 GHz) is widely utilized in long-range radar and air traffic control (ATC) systems, as it offers an optimal balance between antenna size and atmospheric attenuation, ensuring reliable performance even under adverse weather conditions [1]. In contrast, the C-band (4–8 GHz) offers an advantageous balance between coverage range and spatial resolution, making it highly suitable for applications such as weather monitoring, military radar detection, and broadband wireless communications [2]. In such applications, the low-noise amplifier (LNA) serves as a critical building block in the receiver front-end, as it amplifies weak incoming signals while largely determining the overall system performance, particularly the noise figure (NF). Since the LNA is positioned at the initial stage of the receiver chain, its noise contribution directly impacts the sensitivity of the entire system.

In this work, a two-stage LNA monolithic microwave integrated circuit (MMIC) operating in the C-band and a portion of the S-band is designed using the 0.15 µm GaAs pHEMT process. The main contributions of this work are summarized as follows. (1) Simultaneous wideband matching and noise minimization: A two-step matching technique based on inductive source degeneration and gate inductor optimization is employed. Furthermore, high-Q circular inductors are strategically utilized exclusively in the first stage to tightly suppress thermal noise contributions, thereby enhancing the overall NF performance. (2) Analytical design for wideband gain flatness: Unlike conventional GaAs LNAs that often rely on empirical tuning, this work systematically optimizes gain flatness. Specifically, the output matching network (OMN) is designed based on a rigorous voltage gain analysis, securing a highly flat gain response across a wide frequency range. (3) Systematic optimization of multi-dimensional trade-offs: The complex trade-offs among linearity, gain, and stability are comprehensively analyzed. Rather than utilizing trial-and-error methodologies, these parameters are analytically optimized through source degeneration to achieve a robust and reliable design. (4) Highly competitive wideband performance: As a result of the proposed analytical approaches and structural advantages, the implemented LNA achieves wideband impedance matching across the entire operating bandwidth. Notably, it maintains an exceptionally low noise profile, with a NF ranging from 0.81 dB to 1.09 dB.

2. The 0.15 µm GaAs pHEMT Process

In this paper, the PE15 process provided by WIN Semiconductors is employed. This technology is a GaAs-based enhancement-mode pseudomorphic high electron mobility transistor (pHEMT) MMIC process featuring a 0.15 µm gate length [3]. It is specifically developed for high-frequency RF and millimeter-wave circuit applications, with a nominal operating voltage of approximately 4 V. The process is well suited for the implementation of key RF building blocks, including LNAs, switches, mixers, and integrated RF front-end modules.

A pHEMT employs a pseudomorphic heterojunction to confine carriers, thereby forming a high-mobility two-dimensional electron gas (2DEG). An InGaAs-based channel provides high electron mobility, enabling a large transconductance (g_m) and enhanced RF performance in terms of gain and noise.

Figure 1 compares the NF performance across various process technologies. The 0.15 µm GaAs pHEMT process, utilized in LNA designs, facilitates high gain and minimal noise, offering enhanced high-frequency performance owing to its exceptional carrier mobility.

3. Active Device and Bias Selection

In the first step of LNA design, the selection of the active device is a key factor that determines the trade-off among NF, gain, and linearity. The 0.15 µm pHEMT process offers two transistor structures: Microstrip (MS) and Coplanar Waveguide (CPW) [5]. The CPW structure places the ground on the same plane as the signal line, thereby minimizing the parasitic inductance introduced by via-holes and providing favorable characteristics at high frequencies. Therefore, the CPW transistor structure was adopted in this work because it facilitates the implementation of inductive source degeneration for input impedance matching and noise performance improvement.

Table 1. Simulated RF performance of transistors with different total gate widths at 6 GHz.

Transistor Size	2 × 50 (100 µm)	4 × 25 (100 µm)	2 × 100 (200 µm)	4 × 50 (200 µm)	2 × 150 (300 µm)	4 × 75 (300 µm)
NFmin (dB)	0.316	0.273	0.304	0.262	0.322	0.259
MAG (dB)	22.750	22.043	23.080	22.619	23.178	22.836
Current Consumption (mA)	4.798	5.073	9.298	9.569	13.790	14.040

summarizes the simulated RF performance of the transistors with different total gate widths at 6 GHz. To investigate the influence of device geometry, the total gate width was fixed at 100 µm, 200 µm, and 300 µm, while both two-finger and four-finger configurations were evaluated. The corresponding minimum noise figure (NF_min), maximum available gain (MAG), and drain current at V_GS = 0.35 V were extracted to examine the relationship between the transistor structure and its RF performance. Based on the results, the transistors with a total gate width of 200 µm were selected for further analysis. Figure 2a,b illustrate the simulated NF_min and MAG over the frequency range of 2–20 GHz under gate bias conditions of V_GS = 0.35 V and V_DD = 3.3 V. As shown in Figure 2a,b, the 4 × 50 µm configuration maintains a comparable NF_min to that of the 8-finger configuration while achieving a higher MAG exceeding 16 dB across the operating frequency band. Based on this result, the number of fingers was fixed to four for further analysis. The device performance was analyzed by varying the finger width while maintaining the same finger number. To validate the device characteristics, additional simulations were performed at 6 GHz by sweeping V_GS from 0.2 V to 0.8 V, as shown in Figure 3a. Figure 3a shows that the 4 × 50 µm device achieves an NF_min lower than 0.29 dB and a MAG higher than 16.6 dB over the 3.3–8.0 GHz frequency range while maintaining an appropriate current level that satisfies the design requirements. The corresponding drain current variation under identical bias conditions is presented in Figure 3b. Based on these results, the 4 × 50 µm device was selected as the optimal transistor for the proposed LNA. The optimal operating condition was determined with V_GS = 0.35 V, where an NF_min of 0.275 dB was achieved. In addition, different device sizes were employed according to the role of each amplification stage. Figure 4a shows the 4 × 50 µm CPW transistor used in the first stage, while Figure 4b illustrates the 2 × 100 µm CPW transistor adopted in the second stage. The process-layer color labels used in the layouts have also been added for clarity. The detailed rationale for selecting the second-stage transistor size is discussed in Section 4.

4. Design of the LNA

4.1. Inductive Source Degeneration and Matching

Section 4 presents the circuit design methodology and detailed analysis of the proposed LNA. Figure 5 presents the overall schematic of the proposed LNA, including the detailed passive component values and bias conditions used in this design. Concurrent optimization of noise and input matching is a key consideration in LNA design. In this work, an inductive source degeneration technique is employed to achieve both simultaneously [6]. Figure 6 shows the equivalent circuit of the input stage used for analysis. For simplicity, the effect of the RC feedback network is neglected in this equivalent model. Based on this model, the total input impedance seen from the input port can be expressed as in (1). The first term represents the intrinsic gate–source capacitance$\left(C_{gs}\right)$ of the transistor, while the second term corresponds to the reactive components introduced by the gate inductor $\left(L_G\right)$ and source inductor $\left(L_S\right).$ The key feature of this structure lies in the final term, which represents the real part $\left(g_m{L}_s/C_{gs}\right)$. This indicates that the desired matching impedance can be achieved by adjusting the value of the source inductor $\left(L_S\right)$ without incorporating a physical resistive element. Consequently, impedance matching can be realized while avoiding additional thermal noise, thereby maintaining the NF_min [7].

$$Z_{in}\left(s\right)={\displaystyle \frac{1}{s{C}_{gs}}}+s\left(L_G+L_S\right)+{\displaystyle \frac{g_{m^{L}S}}{C_{gs}}}$$

(1)

Furthermore, the frequency-dependent impedance of the inductor increases with frequency. As a result, the inductor presents a larger impedance at higher frequencies, which helps suppress excessive high-frequency components that may otherwise be amplified. This behavior mitigates potential oscillations caused by parasitic capacitances and internal feedback paths of the transistor, thereby improving the overall circuit stability [8]. In addition, compared with resistive matching networks, the inductive matching approach provides improved voltage headroom, which is beneficial for low-power operation and linearity.

To simultaneously optimize input matching and noise performance, a two-step matching procedure is adopted [9]. In the first step, the effect of $L_S$ on the input impedance is investigated by sweeping its value, as shown in Figure 7. The results indicate that the input impedance varies significantly with the value of $L_S$. In particular, when $L_S$ is set to 0.33 nH, the input impedance is closest to 50 Ω at the target operating frequency, providing the best input matching performance. Therefore, the value of $L_S$ is selected as 0.33 nH in this design.

However, while $L_S$ strongly influences the movement of the input impedance, it has a relatively limited effect on the position of the optimum noise impedance (S_opt) [10]. Therefore, in the second step, the gate inductor $L_G$ is adjusted to simultaneously optimize input matching and noise performance. As illustrated in Figure 8a, the input impedance approaches 50 Ω as $L_G$ is tuned, and the optimal value of $L_G$ is determined to be 1.59 nH. In addition, Figure 8b presents the variation of S_opt, which also shifts toward the 50 Ω region with the same value of $L_G$. These results indicate that appropriate tuning of $L_G$ simultaneously improves both input and noise matching. Through this approach, both input matching and noise performance can be optimized using the combined effects of $L_s$ and $L_G$.

$$F_{total}=F_1+{\displaystyle \frac{F_2-1}{G_1}}+{\displaystyle \frac{F_3-1}{G_1{G}_2}}+···+{\displaystyle \frac{F_n-1}{G_1{G}_2···G_{n-1}}}$$

(2)

According to the Friis equation for cascaded stages shown in (2), the overall NF is primarily determined by the noise contribution of the first stage $\left(F_1\right)$. Therefore, minimizing the noise contribution of the first stage is essential for improving the overall NF performance. Accordingly, circular inductors are employed in the first stage of the proposed LNA. Figure 9a shows the simulated Q-factor of circular and rectangular inductors with the same inductance values as those used in the proposed LNA design. The circular inductors exhibit Q-factors ranging from 9.07 to 20.44, whereas the rectangular structures show Q-factors between 6.89 and 15.58. The higher Q characteristics effectively reduce losses caused by parasitic resistance, which in turn lowers the noise contribution of the input stage. Figure 9b shows the simulated NF performance as a function of the inductor geometry in the first stage. The simulation results indicate that circular inductors exhibit approximately 0.3 dB lower NF compared with rectangular inductors. As a result, the overall noise performance of the LNA is improved. Figure 10 illustrates the final layout of the proposed LNA, in which circular inductors are selectively employed in the first stage to enhance performance.

Following the optimization of the noise performance in the first stage, the second stage is further designed to maximize the overall linearity, gain flatness, and stability of the LNA. Since the transistor size in the second stage is a determining factor in the balance between gain and linearity, the total gate width was swept to investigate its impact on the circuit performance. Figure 11a shows the simulated IIP3 at 6 GHz, indicating that the linearity improves as the total gate width increases, achieving values higher than −5 dBm. However, as shown in Figure 11b, although the low-frequency gain increases with larger device size, the high-frequency gain starts to degrade when the total gate width exceeds 250 µm due to increased parasitic capacitances. Therefore, a total gate width of 200 µm was selected as an optimal trade-off between linearity and gain flatness. In addition, as observed in Figure 2b, a two-finger configuration exhibits higher gain compared to a four-finger structure and provides more favorable parasitic characteristics, such as gate resistance ($r_g$) and output resistance ($r_o$), which facilitate impedance matching. Based on these considerations, a 2 × 100 µm transistor size was finally adopted for the second stage.

The effect of source degeneration on linearity, gain, and stability can be characterized by the effective transconductance expression derived in (3) [7]:

$$G_m={\displaystyle \frac{g_{m1}}{{\omega }_0{C}_{gs}\left({ R}_s+{\omega }_T{L}_s\right)}}$$

(3)

where $g_{m1}$ is the intrinsic transconductance, R_s is the source resistance, ${\omega }_0$is the operating angular frequency, and ${\omega }_T$ is the transition frequency. As indicated in (3), the introduction of $L_s$ increases the denominator through the ${\omega }_T{L}_s$ term, which represents the input resistance generated by the negative feedback. This results in a reduction of the overall transconductance ($G_m$), suppressing nonlinear distortion at the expense of gain. To verify this trade-off, Figure 12 compares three configurations: without $L_s$, with $L_s$in the first stage only, and with $L_s$in both stages. As shown in Figure 12a, applying $L_s$ to both stages slightly increases the NF by approximately 0.1 dB compared to the first stage-only case, primarily due to the decrease in gain by the $L_s$. However, the gain remains above 20 dB across the 3.3–8.0 GHz band with a more uniform response. The improvement in linearity is clearly observed in Figure 12b, which compares the IIP3 performance among different configurations. The results demonstrate that applying $L_s$ to both stages achieves the highest IIP3 across the entire frequency band, which is consistent with the theoretical analysis [7]. In contrast, the configuration without $L_s$ exhibits a lower IIP3, dropping to −9 dBm in the low-frequency range. These results indicate that the dual-stage source degeneration is highly effective in maintaining robust linearity throughout the target bandwidth. Furthermore, as shown in Figure 12c, $L_s$ enhances the stability by providing local feedback, confirming the inherent trade-off between gain and stability. Consequently, the proposed design adopts optimized source degeneration inductance of $L_3$ = 0.33 nH and $L_7$ = 0.12 nH in the schematic of Figure 5, achieving a balanced performance in terms of stability, gain flatness, and linearity.

4.2. Analysis and Optimization of the Output Matching Network

To further elucidate the broadband matching mechanism, the output impedance ($Z_{out}$) of the proposed network can be derived as Equation (4):

$$Z_{out}=(s{L}_{10}+{\displaystyle \frac{1}{s{C}_{10}}})+[(s{L}_9||(s{L}_8+{\displaystyle \frac{1}{s{C}_{d2}}}))||({\displaystyle \frac{1}{s{C}_8}}+R_6)]$$

(4)

Equation (4) comprehensively illustrates the strategic role of each matching component. The initial series term acts as a resonant network to precisely match the final impedance to 50 Ω. Within the parallel core section, $L_9$functions as an RF choke by providing high impedance, while $L_8$ is introduced to resonate with and compensate for the large parasitic capacitance ($C_{d2}$) of the transistor, which otherwise degrades $Z_{out}$. The concurrent utilization of $L_8$ and $L_9$ for${ C}_{d2}$ compensation dictates a fundamental design trade-off among the bandwidth, chip area, and gain.

Moreover, the parallel RC feedback branch intricately governs the stability and gain profile. The resistor $R_6$ determines the overall feedback strength; a reduced $R_6$ enforces stronger feedback, which enhances stability but penalizes the total gain and NF. Conversely, an excessive $R_6$ limits the bandwidth and heavily risks oscillation by dropping the K-factor below unity. Concurrently, $C_8$ is tailored to control low-frequency stability. A deficient $C_8$ acts as an open circuit at lower frequencies, thereby weakening the feedback and inducing an excessive low-frequency gain that plunges the K-factor below 1. Therefore, an adequately sized $C_8$ is imperative to suppress the low-frequency gain and ensure unconditional stability. These physical impedance characteristics directly translate into the voltage gain profile. The output matching network (OMN) shown in Figure 5 consists of $L_8$, $L_9$, $L_{10}$, and $C_{10}$, playing a pivotal role in enhancing both gain and linearity. In this work, an OMN gain analysis approach is employed to systematically investigate the contribution of each component. The analytical expression for the small-signal voltage gain ($A_o$) of the proposed two-stage cascaded common-source LNA is given in (5). From the numerator of $A_{V2}$ in (5), it is observed that these OMN parameters directly influence the second stage gain, which large governs the overall performance. Therefore, precise optimization of these values is essential to achieve a stable gain exceeding 20 dB.

$$\begin{gathered} A_o=\stackrel{A_{V1}}{\overbrace{{\displaystyle \frac{-j\omega g_{m1}{L}_4-g_{m1}\left(\left(R_2+\frac{1}{j\omega C_3}\right) \left|\right| j\omega L_5 \left|\right|\left(\frac{1}{j\omega C_5}+j\omega L_6 \left|\right| \left(\frac{1}{j\omega C_6}+R_4 \left|\right| \left(R_6+\frac{1}{j\omega C_8}\right)\right)\right)\right)}{\left(1+j\omega g_{m1}{L}_3\right)}}}} \\ \times \underset{A_{V2}}{\underbrace{{\displaystyle \frac{-j\omega g_{m2}{L}_8-g_{m2}\left(\left(R_6+\frac{1}{j\omega C_8}\right) \left|\right| j\omega L_9\right)-j\omega g_{m2}{L}_{10}-\frac{g_{m2}}{j\omega C_{10}}}{\left(1+j\omega g_{m2}{L}_7\right)}}}} \end{gathered}$$

(5)

Regarding the primary gain detection, $L_8$ and $L_9$ function as the main load components. Inductor $L_8$ forms a resonance with the parasitic capacitance of the transistor at high frequencies, thereby selectively enhancing the gain in the upper region [11]. As shown in Figure 13a, $L_8$ effectively boosts high-frequency gain. However, exceeding 0.89 nH triggers in-band resonance below 8 GHz, degrading the matching condition (S(2,2) > −10 dB). Similarly, as illustrated in Figure 13b, $L_9$ serves as an RF choke and determines the drain load impedance. While reducing $L_9$ lowers low-frequency gain, an excessively large value (e.g., 4.09 nH) introduces undesirable peaking around 4 GHz. Consequently, $L_8$ and $L_9$ were optimized to 0.85 nH and 3.09 nH, respectively, to maintain a high gain profile without compromising matching or stability.

The gain flatness is further refined through the strategic adjustment of $L_{10}$ and $C_{10}$. $L_{10}$ controls the impedance profile in the mid-frequency region by exploiting its inductive reactance $\left(X_L=2\pi fL\right)$. As shown in Figure 13c, $L_{10}$ primarily alters the slope of the gain response rather than its magnitude, resulting in the selection of 0.29 nH to balance low-frequency suppression and high-frequency transmission [12]. Simultaneously, $C_{10}$ acts as a DC-blocking capacitor while compensating for the low-frequency matching variations introduced by $L_{10}$. Its capacitive reactance $\left(X_C=1/2\pi fC\right)$ mitigates gain roll-off at lower frequencies, as demonstrated in Figure 13d. By choosing $C_{10}$ = 0.56 pF, the trade-off between insufficient compensation and excessive loading was successfully resolved.

As a result, the proposed design achieves a gain higher than 20 dB, with a flatness of ±1.9 dB across the operating band. Furthermore, since $L_{10}$ and $C_{10}$ provide fine-tuning rather than primary gain control, the OMN structure maintains high robustness against process variations, ensuring stable and reliable performance.

To further substantiate this reliability and rigorously assess the practical applicability of the proposed LNA, comprehensive temperature simulations were conducted over a standard industrial temperature range from −40 °C to 85 °C [13]. Figure 14a illustrates the simulated NF under varying temperature conditions, where the NF at 85 °C exhibits a marginal increase of approximately 0.3 dB compared to that at −40 °C. Similarly, as depicted in Figure 14b, the S(2,1) demonstrates a minor reduction of roughly 1 dB at 85 °C relative to the −40 °C condition. These robust thermal characteristics firmly verify the environmental and operational reliability of the proposed design, explicitly demonstrating its suitability for practical system integration applications.

To ensure stable operation over a wide frequency range, an RC feedback network is employed [14]. The stability factor (K-factor) is a widely recognized metric for evaluating the unconditional stability of RF circuits, which is defined as follows:

$$\mathrm{K}={\displaystyle \frac{1-{\left|S_{11}\right|}^2-{\left|S_{22}\right|}^2+{\left|\Delta \right|}^2}{2\left|S_{12}{S}_{21}\right|}}$$

(6)

$$\Delta =S_{11}{S}_{22}-S_{12}{S}_{21}$$

(7)

where $S_{11}$ and $S_{22}$ represent the input and output reflection coefficients, while $S_{21}$ and $S_{12}$ denote the forward gain and reverse transmission, respectively. The parameter $\Delta$ in (7) characterizes the interaction between the input and output ports. A circuit is considered unconditionally stable when $\mathrm{K}$ > 1 as expressed in (6), confirming that stability is maintained for any passive source and load impedances.

Figure 15 compares the K-factor simulation results with and without the RC feedback network. While the circuit maintains stability at higher frequencies without the feedback, the K-factor degrades in the low-frequency region due to excessive gain. The introduction of the RC feedback network effectively improves the stability by suppressing excessive gain, ensuring that the K-factor exceeds unity across the entire operating band. Figure 16 shows the chip micrograph of the proposed LNA, which occupies a compact area of 1.8 × 1.1 mm² including the pads.

5. Results and Discussion

The proposed chip was fabricated using the WIN Semiconductors 0.15 µm GaAs pHEMT process. Figure 17a presents a photograph of the fabricated chip mounted on a PCB and wire-bonded. To ensure stable operation and suppress interference from the power supply lines, multiple decoupling capacitors are incorporated. In the gate bias network, where high-frequency performance is a key consideration, 100 pF and 1 nF capacitors are connected in shunt to prevent RF signal leakage. In the drain bias network, a combination of 100 pF, 1 nF, and 0.33 µF capacitors is employed in parallel to mitigate both high-frequency noise and low-frequency instability.

Measurements were carried out using an Agilent Technologies N8975A noise figure analyzer and an E5071C network analyzer. The proposed LNA operates at a supply voltage of 3.3 V with a gate bias of 0.35 V, resulting in a total DC power consumption of 69.3 mW. Figure 18a shows the measured NF across the 3.3–8.0 GHz band, covering portions of the S-band and C-band, with values ranging from 0.81 to 1.09 dB. The measured S-parameters are presented in Figure 18b. Over the entire frequency range, the input and output return losses remain below −10 dB and −9.7 dB, respectively. The gain exceeds 20.1 dB with a peak value of 23.9 dB, showing reasonable agreement with simulation results.

To ensure measurement reliability, a standard SOLT calibration was applied to the network analyzer to de-embed the effects of cables and connectors. The measurements were performed using K-connectors to maintain accuracy at high frequencies. The NF was measured using a calibrated noise source with a known excess noise ratio (ENR). In addition, packaging and interconnection parasitic components were taken into account during the design phase. The bond-wire inductance was modeled using two parallel wires, each having an inductance of approximately 0.5 nH, resulting in an effective inductance of about 0.3 nH when mutual coupling is considered.

The PCB loss was characterized using a through pattern, as shown in Figure 17b, which was used to extract the PCB transmission loss. The measured loss ranges from approximately 0.43 dB at 3.3 GHz to 0.87 dB at 8 GHz, exhibiting a frequency-dependent behavior. During noise de-embedding, half of the PCB loss was subtracted to account for the input-side attenuation. Furthermore, Figure 19a presents the measured output 1-dB compression point (OP1dB), which ranges from 4.4 to 11.5 dBm across the operating band. Figure 19b shows the measured input third-order intercept point (IIP3), with an average value of −5.7 dBm.

$$\mathrm{F}\mathrm{o}\mathrm{M}=20\mathrm{l}\mathrm{o}\mathrm{g}10\left({\displaystyle \frac{\mathrm{G}\mathrm{a}\mathrm{i}\mathrm{n}\left[\mathrm{a}\mathrm{b}\mathrm{s}\right]·\mathrm{B}{\mathrm{W}}_{3\mathrm{d}\mathrm{B}}\left[\mathrm{G}\mathrm{H}\mathrm{z}\right]}{(\mathrm{N}{\mathrm{F}}_{\min }\left[\mathrm{abs}\right]-1)·{\mathrm{P}}_{\mathrm{d}\mathrm{c}}\left[\mathrm{m}\mathrm{W}\right]}}\right)$$

(8)

To provide a comprehensive evaluation, a figure-of-merit (FoM) defined in (8) was employed, where the notation ‘abs’ denotes the absolute linear scale rather than decibels (dB). The proposed design achieved a highly competitive FoM among the reported works, demonstrating its well-balanced overall performance. In particular, the results demonstrate that the proposed LNA achieved a competitive NF with reduced power consumption compared to other GaAs-based designs. Although several recently reported state-of-the-art works employ similar inductive degeneration and feedback topologies, the proposed design differentiates itself through a detailed analytical approach to voltage gain and output impedance optimization. Specifically, high-Q circular inductors are selectively employed in the first stage to improve wideband performance while maintaining low-noise characteristics. Based on the theoretical analysis of gain and impedance behavior, the proposed design achieves a balanced trade-off among noise performance, linearity, and stability. As a result, the proposed LNA achieves a remarkably low NF of 0.81–1.09 dB while maintaining highly competitive overall RF performance. While CMOS implementations generally offer advantages in terms of low power consumption and compact chip area, GaAs technology can provide favorable RF characteristics, particularly for low-noise and high-frequency applications, due to its intrinsic material properties. Specifically, the higher electron mobility of GaAs enables increased transconductance, which can contribute to improved noise performance when properly matched. In addition, the semi-insulating substrate of GaAs enables the realization of high Q-factor passive components by minimizing substrate-induced losses, which are more pronounced in CMOS processes. Leveraging this advantage, the proposed architecture incorporates a high-Q circular inductor in the first stage, where the noise contribution significantly affects the overall NF. In particular, the reduced series loss of the circular inductor effectively suppresses the input-referred noise contribution, thereby improving the overall NF performance. Consequently, these intrinsic properties render GaAs technology highly compelling for high-frequency applications requiring exceptionally low-noise and robust signal integrity.

To further demonstrate the practical implications of this exceptionally low-noise performance, the system-level receiver sensitivity was evaluated based on the parameters of a commercial C-band weather radar [15]. The reference radar system specifies a minimum detectable power of −109.54 dBm over a receiver bandwidth ($\Delta f$) of 1.38 MHz. Applying the NF of 0.87 dB measured at the center frequency to this identical bandwidth condition, the input-referred thermal noise floor ($N_{in})$ of a receiver utilizing the proposed LNA was calculated to be −111.73 dBm ($N_{in}=-174 \mathrm{d}\mathrm{B}\mathrm{m}/\mathrm{H}\mathrm{z}+10lo{g}_{10}(\Delta f)+NF)$. This indicates that the proposed design provides a substantial margin of >2.1 dB over the stringent minimum detectable power requirement, confirming its high suitability and robustness for practical C-band radar front-ends.

Beyond macro-scale radar systems, the proposed LNA offers significant relative advantages for high-precision microwave sensing applications, such as wearable microwave sweat metasensors [16]. In such sensing systems, low-noise amplification is important for improving receiver sensitivity and the signal-to-noise ratio (SNR), particularly when detecting subtle transmission variations associated with physiological changes. The exceptionally low NF of 0.81–1.09 dB and wide operating bandwidth (3.3–8.0 GHz) make the proposed design well suited for broadband physiological sensing applications.

Finally,

Table 2. Performance comparison of LNAs.

Ref.	Technology	Freq. (GHz)	NF (dB)	S (1,1) (dB)	Pdc (mW)	OP1dB (dBm)	Gain (dB)	Gain Flatness (dB)	Area (mm2)	IIP3 (dBm)	K-Factor	FoM
[17]	65-ոm CMOS	0.4–10.6	3.5–4.2	<−11.0	12.0	N/A	10.4	±0.9	0.076 *	−3.2	N/A	17.53
[18]	0.13 µm Bulk CMOS	3.3–10.1	2.08–3.7	<−11.5	10.2	N/A	16.1	±1.75	0.883	2.7	N/A	32.91
[19]	0.15 µm GaAs pHEMT	1.0–12.5	1.51–2.4	<−8.0	87.5	12.8	23.6	±1.65	0.75	N/A	>1.6	37.2
[20]	0.15 µm GaAs pHEMT	3.0–12.0	2.5–4.3	<−10.0	270.0	15.5	18.5	±1.0	3.0	8.5	>6.0	9.63
[21]	0.15 µm GaAs pHEMT	4.0–8.5	<1.76	<−11.5	263.5	13.0	27.1	±0.6	6.4	N/A	>2.5	24.87
[22]	0.15 µm GaAs pHEMT	3.3–11.3	1.4–5.0	<−4.0	85.0	N/A	28.3	±1.5	6.0	N/A	N/A	44.47
[23]	0.15 µm GaAs pHEMT	3.0–15.0	1.5–2.6	<−6.0	200.0	10.0	31.0	±3.5	2.0	−12.0	N/A	45.25
[24]	0.15 µm GaAs pHEMT	0.2–20.0	1.29–1.86	<−12.0	400.0	17.0	15.6	±0.6	1.5	N/A	N/A	14.3
This Work	0.15 µm GaAs pHEMT	3.3–8.0	0.81–1.09	<−10.0	69.3	11.5	23.9	±1.9	1.98	−1.4	>1.4	38.19

* Core area only.

summarizes the performance comparison with recent state-of-the-art wideband LNAs [17,18,19,20,21,22,23,24], including works employing inductive source degeneration and feedback techniques [19,21,22,23] in similar frequency ranges. Compared with these previously reported designs, the proposed LNA achieves a favorable balance between ultra-low noise performance and wideband operation. Demonstrating highly competitive overall RF performance in terms of NF, gain, linearity, stability, and FoM, the proposed architecture confirms its suitability for both high-fidelity microwave sensing systems and advanced radar applications.

6. Conclusions

In this paper, a two-stage LNA was designed and measured using 0.15 µm GaAs pHEMT technology. By employing RC feedback and inductive source degeneration techniques, wideband impedance matching and gain flatness were achieved over the 3.3–8.0 GHz frequency range. These design approaches effectively reduce the NF while enhancing overall circuit stability. In the first-stage design, circular inductors were adopted to achieve a high Q-factor. This configuration effectively reduces input-side losses and plays a key role in optimizing the overall noise performance of the system. The proposed LNA simultaneously supports C-band and a part of S-band. Owing to its low noise, high gain, and wideband characteristics, the proposed design is suitable for integrating multiple radar and communication systems into a single RF front-end.