1. Introduction
Fault diagnosis is a critical challenge in electrical and electronic engineering. A well-designed diagnostic process enhances circuit performance, minimizes failure risk, shortens maintenance time, and improves operational safety. Despite representing only about 20% of electronic systems, analog circuits are responsible for more than 80% of observed faults [
1,
2,
3,
4,
5] due to their diversity, wide signal ranges, susceptibility to noise, temperature variations, parameter tolerances, measurement uncertainties, limited test access, and the existence of ambiguity groups. The factors highlight the need for effective diagnostic methodologies, which is reflected in the growing research output.
Analog circuits may exhibit single (most common) or multiple faults. Faults are typically divided into hard (catastrophic) faults, usually resulting from opens or shorts that modify circuit topology, and soft (parametric) faults, where component values deviate from allowable tolerances [
1,
6]. Incipient faults constitute a special case of soft faults, causing only slight parameter drifts yet degrading performance (see, e.g., [
2,
7,
8,
9]). Faults may also be permanent or intermittent [
6,
10,
11].
The development of reliable diagnostic methods requires proper selection of measurement nodes, test frequencies, excitation signals, and amplitudes, collectively known as test point selection [
12,
13,
14]. Measurement strategies include DC and AC tests and time-domain measurements. Another important concept is testability, which provides theoretical limits on the solvability of test equations given a chosen set of measurement points [
6,
15]. Restricted measurement access and ambiguity groups often lead to non-unique solutions of nonlinear test equations [
5].
Diagnostic techniques can be broadly categorized into simulation after test (SAT), typically used to diagnose soft faults, and simulation before test (SBT), primarily applied to hard faults [
5]. Testing objectives range from verifying functional correctness (fault detection) to locating faulty components and estimating parameter values.
A wide range of mathematical tools support diagnostic procedures, including Fourier and wavelet transforms for signal analysis. The rapid growth of artificial intelligence, especially deep learning, has further expanded the range of diagnostic techniques available. However, AI-based approaches usually focus on single hard faults, predefined soft faults (e.g., faults corresponding to ±30% or ±50% of the nominal value) or selected ranges of parameter deviations, limiting their applicability to multiple-fault scenarios [
1,
4,
14,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26]. For multiple fault diagnosis in nonlinear circuits, SAT methods are typically preferred. In most diagnostic SAT procedures, nonlinear test equations are formulated and solved based on measured circuit quantities. Even for linear systems, the equations are nonlinear and may yield multiple solutions [
5]. Significant parameter deviations can prevent convergence of iterative solvers or give virtual solutions. Moreover, different parameter combinations may satisfy the test, complicating diagnosis. The paper [
5] focuses on fault diagnosis in nonlinear circuits and reviews essential concepts from the literature, including testability, test point selection, and SAT/SBT approaches, with particular emphasis on methods applicable to nonlinear circuits. The paper also highlights key challenges in diagnosing nonlinear circuits. Using simple examples, it demonstrates that even single hard faults may be difficult to detect in transistor circuits, and that soft faults and temperature effects can alter the number of operating points.
Piecewise-linear (PWL) approximation simplifies nonlinear characteristics by representing them as several linear segments, each valid over a specific input range. The approach streamlines analysis and simulation and can be applied in circuit modeling and fault diagnosis. In [
27], a symbolic testability method for nonlinear analog circuits was introduced, in which nonlinear elements are replaced with PWL models to derive symbolic network functions and construct a testability matrix whose rank reveals the circuit’s testability. A data-driven method for testability assessment is introduced in [
28]. In this approach, single hard faults are injected into the circuit model and simulated to produce diagnostic data. The resulting responses are then analyzed using a
k-nearest neighbors classifier to quantify testability.
Since the paper focuses on single faults in nonlinear circuits and employs the SBT methodology for their identification, the remainder of the section provides a more detailed discussion of the concepts. The SBT approach simulates predefined faults and stores their quantities or responses in a fault dictionary. Measured circuit quantities or responses are compared with the signatures, and the closest match identifies the likely fault. While effective for single hard faults, the method becomes impractical for multiple soft faults due to the exponential growth of dictionary size. Hochwald’s pioneering work [
6] introduced analog fault dictionaries for detecting and isolating single hard and soft faults using failure histories, selected stimuli, and DC voltage deviations. Since the 1990s, artificial neural networks (ANNs) have been widely used for fault diagnosis [
3,
10,
29,
30]. PWL modeling is also used in SBT methods. Tan [
31] applies ANN-GA optimization with PWL-based circuit analysis via the Katzenelson algorithm, whereas Worsman and Wong [
32,
33] diagnose single faults using large-change sensitivity and PWL models. Another SBT approach is statistical-feature-based techniques that extract kurtosis, entropy, wavelet-based metrics, or supply-current features [
34,
35]. Local spot defect diagnosis in analog circuits using finite-resistor models and parametric characteristic families is explored in [
36]. Other methods include high-order moment fractional transforms [
2], and image-analysis-based multi-fault identification in power converters [
37].
The paper discusses the problem of fault diagnosis in nonlinear analog circuits and presents a comprehensive method for identifying single hard and soft faults in DC circuits. The main achievement of the work, compared to dictionary-based methods known for several decades, is the consideration of multiple equilibrium points during the dictionary creation stage. Therefore, the approach extends classical methods by an important aspect, both theoretically and practically. A second original aspect is the design of the soft fault dictionary, which, unlike standard and artificial intelligence-based approaches, enables not only the identification of the faulty component but also the estimation of its approximate range. For this purpose, a piecewise-linear approximation of parametric characteristics is used, and only simple calculations are performed during the post-test phase. In both dictionaries, a classical Monte Carlo approach is used to account for tolerances. However, to ensure that all equilibrium points are captured, Monte Carlo simulations are preceded by analyses using a method that guarantees the identification of all operating points, previously published with the author’s contribution [
38]. To select tests for hard faults, the concept of adding successive measurement quantities (currents and node voltages) is used to reduce ambiguity. Two separate dictionaries were created: one for soft faults and one for hard faults. After measurements are taken in the circuit under test, the dictionaries are searched to determine fault(s). The paper also discusses several practical challenges and potential risks encountered during the creation of the dictionaries. The proposed method was verified through simulations and experimental measurements conducted on a test bench under various constraints on measurement availability.
Section 2 discusses an outline of the method used to determine all DC solutions in bipolar transistor circuits. In addition, it provides basic information on the stability of equilibrium points and methods for analyzing local stability. Examples are also provided to illustrate how the determined operating points were used in SPICE simulations.
Section 3 contains two subsections describing the proposed methods for creating both dictionaries, guidelines for selecting tests for hard faults, and methods for using the dictionary’s entries during the testing phase. These topics are illustrated via examples.
Section 4 describes an outline of the diagnostic procedure.
Section 5 presents the results of applying the procedure to diagnose single faults in bipolar transistor circuits under laboratory conditions. A description of the challenges and possibilities for extensions, supported by examples, is provided in
Section 6. The overall summary is provided in
Section 7.
2. Method for Finding All DC Solutions
A broad class of electronic circuits has multiple equilibrium points. Some of them are stable, whereas the other are unstable. To determine the stable equilibrium points, all DC solutions of the associated resistive circuit must be found, and then methods must be used to select the stable ones [
38,
39,
40,
41,
42,
43]. At present, there are no methods capable of finding all solutions for nonlinear circuits with arbitrary semiconductor device models and of any size. It follows from the immense computational complexity of methods that guarantee the finding of all operating points.
In recent years, methods that can determine many solutions but do not guarantee finding all have dominated. They are usually based on the concept of homotopy or deflation [
42,
43]. For certain classes of small-sized circuits, algorithms have been developed that guarantee the determination of all DC solutions within an acceptable time. The methods require a specific description, the so-called hybrid description, and piecewise-linear approximations of nonlinear characteristics. The hybrid description is characterized by very high conciseness, since the number of equations typically equals the number of nonlinear elements in semiconductor device models. Based on the models and the piecewise-linear approximation, the combinatorial method, the method of successive contraction, division, and elimination, and linear programming methods were developed. For continuously differentiable characteristics, a time-consuming concept of interval analysis was developed. An effective approach to piecewise-linear analysis of circuits with multiple DC solutions is based on successive contraction, division, and elimination [
41]. However, since the piecewise-linear representation approximates real nonlinearities, the results can be inaccurate, or even the number of solutions can be incorrect. In paper [
38], the idea of successive contraction, division, and elimination was adapted to circuits including bipolar transistors represented by the Gummel-Poon models [
44,
45]. The circuit description includes exponential nonlinearities, and no piecewise-linear approximation is used. A very effective contraction procedure was developed and embedded into the algorithm. An outline of the method of successive contraction, division, and elimination, and of the contraction procedure proposed in [
38], is presented below.
The DC circuit, consisting of
bipolar transistors, linear resistors with positive resistance, and independent voltage and current sources, is considered. The bipolar transistors are represented by the Gummel-Poon nonlinear DC model, which, after applying the current-shift property and the concept of equivalent circuits, takes the form shown in
Figure 1 (details are given in [
38]). The nonlinear part of this model has the following separable description
where
, and
.
To describe a circuit, all branches consisting of combinations of diodes and controlled sources are extracted from the circuit [
38]. In this way, a linear
n-port (
) circuit is created. Using a hybrid circuit description, which in this case takes the form of an admittance representation, the following equation is obtained
where
is a short circuit admittance matrix of the
n-port,
b is a source vector,
is a vector composed of the port voltages (across the extracted branches), and the individual components of the nonlinear function
are linear combinations of the original nonlinear functions, formed as described in [
38].
All solutions to Equation (
7) are sought that belong to a certain hyper-rectangular region
whose boundaries encompass all operating points, and
, for
. For diode-transistor circuits, the bounds can be found using the no-gain property [
41]. The solutions are determined using the concepts of successive contraction, division, and elimination. The initial region is reduced using the contraction method so that the new region contains the same solutions. If the reduced region is not small enough, it is split into two regions, and each region is then reduced. The process continues until the largest region size is less than
. Such regions are referred to as points, and a procedure is used to check whether the region contains a solution to (
7). Applying appropriate criteria during the process eliminates certain regions that do not contain solutions. The convergence rate of the algorithm depends on the effectiveness of the contraction procedure.
To illustrate the procedure of successive contraction, division, and elimination, a circuit containing two nonlinear resistors is considered. It is assumed that the circuit has three solutions:
,
, and
(
Figure 2a).
The aim of the analysis is to determine all solutions belonging to the set
. Using a certain contraction procedure, the initial set is reduced (
Figure 2b). Further reduction of the region is impossible, so it is divided into two parts, one of which is marked with a red line (
Figure 2b) and subjected to further analysis, whilst the other, containing solution
, is pushed onto the stack. Applying the contraction procedure to the region bounded by the red line leads to the region shown in
Figure 2c, which is then divided into two regions, each containing a single solution (
Figure 2d). One of the areas is pushed onto the stack, whilst the other, let us assume it contains the solution
, is subjected to the contraction procedure. Usually, after a few iterations, a region with the longest side smaller than the assumed value is reached. In this case, treating the region as linear, the corresponding linear system is solved, and the solution is checked for consistency with the original equation. If the consistency is confirmed, the solution to the original Equation (
7) is found. Next, the boundaries defining the remaining regions are taken from the stack and processed in the same manner. The algorithm continues until the stack is empty, completing the procedure for finding all solutions.
A key procedure of the method is the contraction algorithm developed in [
38]. The set of
n equations in (
7) is divided into blocks of two equations corresponding to individual transistors. After a few simple transformations, the two equations are expressed as a pair of equations, each of which contains three of the four nonlinear functions (see (
3)–(
6)). Each of the functions is bounded by two parallel lines as shown in
Figure 3.
First, a line passing through the points with coordinates , , and , , respectively, is found. Next, the lower bounding line is determined, which is tangent to the original nonlinear function at the point .
Let
be an arbitrary solution to Equation (
7) belonging to the set
. After certain transformations, the details of which are given in [
38], by repeating the framing procedure for each block of two equations, the following equation is obtained
where
M is a block-diagonal matrix, constructed from
blocks whose elements depend on the coefficients
of the individual framings. The elements of the vector
are not known, but based on the offsets
and
, the boundaries
and
of
can be determined. If the matrix
is non-singular (which, except in very rare cases, is satisfied),
is obtained, where
. The elements of
are unknown, but the boundaries
and
can be found using the relationships
, and
,
. By defining
on the basis of (
9)
is obtained, where
,
. Next, new boundaries on the solutions
}, and
are determined and the set
is formed, containing the same solutions as
.
A limitation of the method, due to its time-consuming nature, is the size of the circuits it can analyze. Given current processor performance in single-threaded applications, the time required to identify all solutions in circuits containing up to 10 bipolar transistors does not exceed 20 s. For example, analyzing the circuit in [
38] with 8 transistors and 11 DC solutions at present takes 1.2 s. The times needed to find all DC solutions in the circuits considered in this paper are below 1 ms. However, as the number of equations (i.e., transistors) increases, the time required grows exponentially, and determining all solutions for a circuit with 15 transistors can take hours. For larger circuits, it is currently necessary to use methods that can find many DC solutions but cannot guarantee finding all operating points.
Some operating points are physically unobservable during normal circuit operation because the corresponding equilibrium points of the dynamic circuit are unstable. Certain measurement techniques exist that enable the identification of many DC operating points and the investigation of regions that are typically unobservable. The methods do not guarantee the identification of all solutions and require the inclusion of additional sources within the circuit (e.g., two-probe sources), which eliminate certain feedback loops and result in a circuit fundamentally different from the original one [
43]. Therefore, an important issue is the development of algorithms to determine potentially stable DC solutions, i.e., the DC solutions corresponding to stable equilibrium points of dynamic circuits resulting from the introduction of positive capacitances and inductances. A DC solution is potentially stable if, upon inserting a certain set of positive, parallel capacitances and series inductances into the circuit, the equilibrium point of the resulting dynamic circuit corresponding to the DC solution is stable, and if the equilibrium point of every dynamic circuit created by adding to the system additional capacitances and inductances whose values are sufficiently small is also stable. The operating point is unstable if it is not potentially stable (see [
39,
40]). In [
40], using the results of degree theory, it was shown that if a circuit has
r operating points (it was previously shown that
r is an odd number), then
of the operating points must be unstable, and therefore physically unobservable. The two best-known methods for determining whether a given equilibrium point is stable or unstable are the first and second Lyapunov methods [
39]. In this paper, a method based on the first Lyapunov method is used. The Lyapunov method involves linearising the circuit around a given equilibrium point and then examining the natural frequencies at that point. If all natural frequencies lie in the open left half-plane, then the equilibrium point is stable. If at least one natural frequency lies in the open right half-plane, then the equilibrium point is unstable [
39]. In [
39], the stability of all operating points was rigorously investigated. The authors provided simple criteria, based solely on the circuit’s steady-state equations, for checking the stability of a given operating point. The authors also demonstrated that, for any physical circuit, it is sufficient to model stray capacitances and inductances at only a few locations to correctly assess the instability of its operating point. For large circuits, using this method is beneficial.
The method described above guarantees the identification of all equilibrium points, although it determines only junction voltages. If, during the construction of the fault dictionaries, method [
38] yields only one solution, there is no need to determine other circuit quantities. However, if there are multiple solutions, the other quantities must be identified to perform a controlled analysis in SPICE [
44,
45]. It is particularly important to determine the node voltages corresponding to each solution. To find the voltages, appropriate equations must be formulated that make the voltages sought dependent on the determined junction voltages. For this purpose, so-called voltage ports must be inserted between the node of interest and a reference node, and a modified hybrid description must be done. Next, using the equations and the solutions determined by the method described above, all solutions can be found in SPICE using the .nodeset directive to set the starting point for the DC analysis.
To illustrate the problem, consider the circuit shown in
Figure 4. Bipolar transistors are represented by the Gummel-Poon model with the following parameters:
,
,
,
,
,
,
,
,
. At the nominal parameter values shown in
Figure 4, the circuit has three equilibrium points: two stable and one unstable. Method [
38] resulted in the following junction voltages
,
, and
, all in volts (in order: the BE and BC junctions for transistor
, and the BE and BC junctions for transistor
).
Next, using the results, the nodal voltage vectors corresponding to the individual solutions were determined,
,
, and
. The order of the elements in the vectors corresponds to the node numbers indicated in
Figure 4. The stability analysis of the solutions shows that the solution with index 3 is unstable. The .nodeset directive provides hints for finding the DC operating point and can be used to direct the circuit to one state or another. By applying the directive three times, the three DC solutions were identified in SPICE.
Now consider the DC model of a two-stage transistor amplifier shown in
Figure 5 [
5].
The nominal values of the parameters are as follows:
,
,
,
,
,
,
, and
. Bipolar transistors are represented by the same Gummel-Poon model as in the previous example. Method [
38] method yields the single solution
corresponding to the node voltage vector
, all in volts.
It should be emphasized once again that both soft and hard faults, even single ones, can alter the number of operating points. Therefore, using method [
38] together with SPICE simulations enables the development of reliable fault dictionaries for nonlinear circuits.
4. Diagnostic Procedure
The section summarizes the results of
Section 2 and
Section 3 and provides a concise overview of the diagnostic process, including how dictionaries are prepared during the pre-test stage and how their contents are used during the post-test stage. A flowchart of the process is shown in
Figure 18.
The first stage of the method involves analyzing the healthy circuit using the method presented in
Section 2. The process involves determining a hybrid description of the nominal circuit, using an appropriate bipolar transistor model. If the circuit has a single operating point, Monte Carlo analyses with parameter variations within the specified tolerance range can be performed immediately in SPICE. In the case of multiple solutions, if the user has a method for determining locally stable solutions, the operating points corresponding to unstable equilibrium points are rejected. To perform a controlled DC analysis in SPICE, for operating points corresponding to stable equilibrium points (or all equilibrium points if the local stability identification procedure is omitted), the node voltages must be specified based on the DC analysis results, namely, the junction voltages. To find the node voltages, appropriate equations are formulated using the hybrid representation by placing so-called voltage ports between the interesting node and a reference node. After determining the node voltages, the .nodeset directive uses them as the starting point, and DC and Monte Carlo analyses are performed. In this case, unlike a circuit with a single operating point, several voltage ranges at the test node and current values measured in the healthy circuit are obtained.
The next stage involves analyzing the nonlinear circuit for selected single hard faults. The process proceeds similarly to the healthy circuit analysis: each Monte Carlo analysis is preceded by determining all operating points using the method described in
Section 2, followed by appropriate modifications to the circuit resulting from the assumed fault type. The result of these steps is a range or several ranges of measured values. Next, if no specific measurement points were defined at the outset, a test selection is performed. The test selection method adds successive measurements to achieve maximum class discriminability. Based on the selected test, the measured quantity ranges are stored.
Next, the fault names (based on the healthy configuration) for which the intervals share a common part are identified. They are grouped into classes designated as A, B, C, etc. For each class, a measurement range is created, the lower limit of which is the minimum of the minimum values of the elements comprising the class, and the upper limit is the maximum of the maximum values. The final step is to create an Excel spreadsheet containing a dictionary for the measurement variant (test). Subsequent columns contain the minimum and maximum values of the measured quantities, followed by a code (e.g., ABA) corresponding to the measurement ranges. The last column lists the identified states.
During the test stage, DC measurements are done for the quantities corresponding to the actual test. The test is carried out at a temperature established during the dictionary development stage, with the achievable measurement accuracy of laboratory measuring instruments.
At the post-test stage, the measurement data is compared with the relevant measurement ranges. The entry in the dictionary whose test measurements fall within the measurement ranges is highlighted. This enables the identification of the fault or the confirmation that the circuit is healthy. Such an organization of the dictionary results in the unambiguous identification of only one signature.
The proposed soft-fault dictionary is based on the determination of parametric characteristics as functions of parameters within predefined ranges. DC analyses of the circuit using the method described in
Section 2 precede SPICE simulations without parameter spreading. For a single operating point across the entire range of parameter variation, DCSweep analyses are performed in tandem with Monte Carlo analysis, and the envelopes of the parametric characteristics for the measured quantities are described by piecewise-linear functions. The approximation is performed by selecting a set of points on the envelopes of the selected measurements. When many operating points are identified, for those corresponding to stable equilibrium points, DCSweep analyses linked to the Monte Carlo analysis are performed, using the node voltages determined as described for hard faults. Additionally, in the SPICE program, the .noreuse configuration option must be set to prevent the automatic saving and restoration of bias point information across different simulation scenarios. The piecewise-linear approximation is performed for each branch of the characteristic in the same way as for parametric characteristics in a single-bias-point circuit. The parameters describing the piecewise-linear characteristics for the selected test (issues related to sub-optimal test selection were highlighted in the previous Section and further discussed in
Section 6) are included in the soft fault dictionary.
The soft fault dictionary has also been created as a collection of Excel spreadsheets. Based on the measured data, the relevant segments are identified, and the parameter values are determined using the inverse function, i.e., by solving a simple equation. The summary sheet displays the results for all parameters for all measurements comprising the test in question. If the common part of the ranges of values for a given parameter across all measured quantities is non-zero, it constitutes the estimated range of the parameter. It should be emphasized that when using a soft fault dictionary, it is possible for the result to be ambiguous, which arises when different parameters satisfy the selected test. Similarly, the estimation of the range for a given measurement may yield one or more intervals (see
Figure 15 and
Figure 16).
5. Examples
The SBT method discussed in the previous sections was implemented in Excel. Two examples of nonlinear DC circuits, shown in
Figure 4 and
Figure 5 were selected to illustrate the efficiency of the method. Simulations and laboratory tests of several dozen single soft and hard fault cases were performed. Faults with different deviations from the nominal value of the parameter were considered. Bipolar transistors were represented by the Gummel-Poon model with the parameters given in
Section 2. The model parameters were fitted to the transistors of a general-purpose high-current NPN transistor array, the CA3083, used in the laboratory. The tested circuits were built on a typical solderless breadboard using a CA3083 and 1% tolerance resistors. Seven-decade programmable resistor boards were used to set the actual resistance values. The equipment necessary to take measurements consisted of two DMM 34401A (Hewlett-Packard Company, Loveland, CO, USA; Keysight Technologies, Inc., Santa Rosa, California, USA), and a Motech LPS-305 Programmable Linear Power Supply (Motech Industries Inc., Taipei Hsien, Taiwan) (see
Figure 19). The measurements were made at ambient temperature T = (
). The standard type B uncertainty was calculated based on the accuracy specifications for the DMM 34401A, assuming a rectangular (uniform) probability distribution and applying the instrument’s 1-year accuracy assumptions. The calculated measurement uncertainties are below 1 mV and 10
A. To ensure robustness against type B measurement errors, measurements with an accuracy of thousandths of a volt and hundredths of a milliampere are used.
In the circuit shown in
Figure 4, a hard-fault dictionary was created containing 14 single hard faults (including two faults leading to three equilibrium points) and the healthy circuit (with three equilibrium points). The names of selected hard faults (states) are shown in
Figure 6. A soft-fault diagnosis dictionary was created, accounting for potential single faults in resistors
–
, In the circuit shown in
Figure 5, a dictionary was created covering 26 single hard faults and the healthy circuit (see
Figure 7), as well as a dictionary for soft faults (resistors
–
). The results of 1000 Monte Carlo simulations for the healthy circuits shown in
Figure 4 and
Figure 5, assuming a 2% resistance tolerance, are summarized in
Table 1. Analysis of the data in
Table 1 indicates that in
Figure 4 measurements of the current drawn from source V1 (IV1) and the voltages at nodes 2 to 6 (V2–V6) can be used, whilst in the circuit shown in
Figure 5, measurements of the current drawn from source V1 (IV1) and the voltage at nodes 2 to 7 (V2–V7) can be utilized. The voltages at the remaining nodes are constant (determined by independent voltage sources). In the examples, results obtained using these measurements will be referred to as full access (FA).
5.1. Diagnosis of Single Faults in Circuit with Multiple Equilibrium Points
The section presents the results of diagnosing single faults in the circuit shown in
Figure 4. For nominal resistance values and healthy transistors, the circuit has three equilibrium points. Two of them are stable. There are also three operating points for some hard faults. The circuit was assembled in the laboratory, and all hard faults included in the fault dictionary were introduced sequentially. It should be emphasized, as shown in
Figure 6, that in addition to the three signatures for the healthy circuit, the dictionary contains three signatures for short circuits in resistors
and
. As previously mentioned, the stability analysis of the solutions can be performed during the pretest stage, and the signatures corresponding to unstable solutions can be removed from the fault dictionary. There are the states NOM_1, R5s_2, and R6s_2. 14 potential single hard faults are considered, although the number of states is higher (due to the three operating points for the aforementioned states) and equals 21. According to the analysis presented in
Section 3, with FA, there are 17 signatures in the fault dictionary, and with the measurement IV1 + V3 + V6, there are 16 classes. The results mean that certain states are indistinguishable. For FA there are states belonging to the sets {NOM_1, R6s_2}, {NOM_2, BET2_s, R5s_3}, and {NOM_3, R6s_1}. The first set contains two states corresponding to unstable solutions. For IV1 + V3 + V6 measurement, there indistinguishable are elements in the sets {NOM_1, R6s_2}, {NOM_2, BET2_s, R5s_3, R4s}, and {NOM_3, R6s_1}.
Table 2 presents the measurement data and the results of the diagnostic process for the test IV1 + V3 + V6. For hard faults corresponding to two stable equilibrium points, measurements were recorded for both of them. For FA, the diagnostic process was performed via fault simulation, assuming a certain resistance spread within the tolerance limits. The results confirmed the correctness of the fault dictionary’s design and consistently identified a signature corresponding to the fault, although the circuit-state result is not always unique.
In
Section 3, the soft fault dictionary is formulated in detail for circuits with a single equilibrium point. Now, the extension to circuits with multiple equilibrium points is proposed. The approach usually requires the description of multi-branch parametric characteristics determined with a spread of parameters within tolerance limits. In general, when there are three or more equilibrium points for a given parameter value, the characteristics may be multi-branched and ambiguous. An important aspect is also identifying segments corresponding to unstable solutions. Furthermore, Monte Carlo analyses in SPICE using the .nodeset directive often omit parts of the characteristic. Therefore, the best approach is to perform such analyses using software that guarantees the identification of all DC solutions. Since there are thousands of such characteristics for a single parameter in the dictionary, using the method described in
Section 2 directly is time-consuming. Therefore, to construct the soft fault dictionary, a method that guarantees the identification of all solutions was used in combination with SPICE simulations.
To examine the problem of piecewise-linear approximation more closely, we will consider the parametric characteristics shown in
Figure 12. Within the range from 1 to 20 k
of parameter
(around the nominal value of 8 k
), the SPICE characteristics exhibit a hysteresis loop. The result indicates the presence of multiple equilibrium points. For the nominal value of
, three solutions are determined: two stable ones, for which V5 is 3.91 V and 2.83 V, and one unstable, V5 = 3.5 V. By setting the starting points with the .nodeset directive and performing parametric analyses above and below the value
= 8 k
, a branch of the characteristic with a negative slope passing through the 3.5 V point is found. The branch corresponds to the unstable solutions. Next, 1000 random draws of healthy parameters within the tolerance limits are performed. Unstable solutions are discarded, and the family of characteristics is framed. The result of the steps is shown in
Figure 20 (blue lines). Additionally, three bands corresponding to the equilibrium points of the healthy circuit, accounting for tolerances, are plotted. The orange band corresponds to an unstable solution. To add entries to the soft fault dictionary, the two blue branches shown in
Figure 20 are framed using piecewise-linear characteristics.
Using the described procedure, multi-branch parametric characteristics were obtained, defining the current drawn from source V1 and the node voltages as functions of resistors
to
, over a range of 100
to 20 k
for all parameters. It was observed that for all these parameters, there are ranges of values for which the circuit has three solutions. This results in a two-branch parametric characteristic, which is approximated by a piecewise-linear function. The result of this approximation, which expresses the voltage at node 5, is shown in
Figure 21. Selecting the optimal test, even for such a small number of parameters, is an extremely complex issue that has not yet been addressed in the literature. Therefore, it was assumed a priori that the dictionary would be constructed based on measuring the current IV1 and the voltages at nodes 3 and 5 (V3 and V5). Measurement at the second node provides little diagnostic information, as significant changes in this signal occur only for two branches when two parameters (
and
) are considered. For the voltage at node 6, many branches with different parameter values lie within a very narrow voltage range, leading to numerous ambiguities. A similar phenomenon, although less pronounced, occurs at node 4. A soft fault dictionary was constructed by extending the concept described for single-operating-point circuits. For this purpose, an item is created in the dictionary for each branch (e.g.,
and
are two branches corresponding to stable solutions when the
parameter is varied).
The results of some diagnostic tests for several single soft faults are summarised in
Table 3. An analysis of the results shows that when the fault occurs in a circuit with multiple equilibrium points, the solutions corresponding to both stable equilibrium points include the assumed fault but yield different numbers of identified parameters and parameter ranges. This constitutes the potential to eliminate virtual solutions, taking into account the test involving forced measurement at both stable equilibrium points. For example, for the fault
, considering the solutions corresponding to measurements at both stable equilibrium points, a unique diagnostic result is obtained,
. A similar procedure yields unique results for faults
10,000
(
[9845, 10,124]
) and
(
). In the case of fault
, an ambiguous result is obtained:
and
.
5.2. Diagnosis of Single Faults in Circuit with Single Equilibrium Point
The section presents the results of diagnostics of single hard and soft faults in the circuit shown in
Figure 5. At nominal resistance values and healthy transistors, the circuit has a single equilibrium point. For all considered single faults, the circuit also has a single operating point. The circuit was assembled in the laboratory, and selected hard and soft faults contained in the fault dictionary were considered. The possibility of 26 hard faults occurring was assumed, and a fault dictionary was constructed for the faults as well as for the healthy circuit. In accordance with the analysis presented earlier, for FA, there are 25 signatures (classes) in the fault dictionary. For the measurements IV1 + V2 + V7 and IV1 + V2 + V3, there are 21 and 24 signatures, respectively (see
Figure 9). The results indicate that some states are indistinguishable. In the case of FA, there are states in the sets {NOM, R4s}, {ET1o, BT1o}. In the case of the IV1 + V2 + V3, the indistinguishable are elements in the sets {NOM, R4s}, {ET1o, BT1o}, and {ET2o, R6o}, whereas at IV1 + V2 + V7 measurement, there are elements in the sets {NOM, R4s}, {BT1o, CT1o, ET1o, R4o, BET1s}, and {ET2o, R6o}.
Table 4 presents measurement data collected in the laboratory and the results of the diagnostic process for the test IV1 + V2 + V3, whilst
Table 5 presents measurement data and the results of the diagnostic process for the test IV1 + V2 + V7. In both tables, the final column contains the diagnostic results for FA. The results presented in the tables confirmed the validity of the fault dictionary design. At the same time, an examination of the tables shows that different measurement tests are generally preferred for identifying hard and soft faults. The IV1 + V2 + V3 test effectively identifies hard faults, but it leads to many ambiguities for soft faults. On the other hand, the IV1 + V2 + V7 test for the considered single soft faults yields more unique results, similar to those obtained at FA. Optimally selecting a test for soft faults is an extremely complex optimization process due to the specific characteristics of nonlinear circuits, particularly changes in sensitivity values. The problem is even more difficult when the parametric characteristics are multi-branched. Both issues are briefly discussed in
Section 6.
5.3. Final Remarks
In the hard-fault dictionaries considered for both circuits across all measurement variants, certain classes correspond to two or more circuit states, including the healthy circuit and some fault types. For example, for the circuit with multiple equilibrium points at FA, the diagnostic procedure distinguishes between 18 classes. Fifteen of these correspond to unique fault states, whilst the remaining three classes each encompass two physical states: the healthy state and one specific fault. Consequently, performance evaluation and the confusion matrix are carried out at the decision-class level. Diagnostic accuracy, defined as the percentage of correctly classified test cases over all tested faults, was computed using the main diagonal of the confusion matrix constructed for the decision classes. Since all test cases were correctly assigned to their corresponding diagnostic classes, the diagnostic accuracy was 100%. The false-positive rate was evaluated separately for each diagnostic class using a one-vs-all scheme. As no misclassifications were observed, the false-positive count for all classes was zero, yielding a false-positive rate of zero for each class and a macro-averaged false-positive rate of zero. Identical results for diagnostic accuracy and the false-positive rate were obtained for the other hard-fault dictionaries.
The magnitude of the estimation error for soft faults is determined by many factors. The most important factor influencing the magnitude of the error is the diagnostic test selected. The same measurement may yield a very precise estimate of one parameter and a very inaccurate estimate of another. Another measurement may yield the opposite result. Therefore, as noted earlier, selecting a suboptimal test is a major research challenge. Another important factor is the number of considered parameters and the assumed tolerance of intact elements. In combination with local sensitivity (at a given value of the parameter under consideration during the parametric analysis), these factors determine the width of the bands obtained from the Monte Carlo analysis. An additional factor influencing the result is the shape of the parametric characteristic, which arises from changes in sensitivity: flat sections, where sensitivity is close to zero, yield wide ranges of values for the estimated parameter. The average relative error, expressed as a percentage and calculated as the width of the estimated range relative to the assumed fault value for the tests performed, is roughly 12%. The minimum error is 2.8%. It is worth noting that in the vast majority of cases, the average of the lower and upper limits of the estimate is close to the assumed value. The accuracy of the results can be improved by including tests at different supply voltages during all stages of the diagnostic process. In nonlinear circuits, changes in the supply voltage alter the quantities that determine the operating points, and in some cases also the number of equilibrium points. This allows additional diagnostic information to be obtained.
6. Discussion
DC analysis, in which the operating points of nonlinear devices are specified, is a key circuit analysis that precedes nearly all other analyses. In diagnosing nonlinear circuits, effective methods for detecting faults in elements that determine operating points are also of fundamental importance. The proposed SBT method can be successfully applied to the diagnosis of single faults in nonlinear circuits containing bipolar transistors, including, uniquely, circuits with multiple equilibrium points. The restriction to the bipolar circuit class results from the method used to determine all operating points. To the author’s knowledge, the method described in
Section 2 is the only method that enables such a DC analysis using the Gummel-Poon model, commonly employed in simulators, while preserving the original nonlinearities (rather than a piecewise-linear analysis). Due to the time-consuming nature of the analysis, the method applies only to circuits containing up to a dozen bipolar transistors. To build a fault dictionary for a larger circuit with bipolar transistors, other methods that do not guarantee finding all DC solutions must be used. For circuits containing operational amplifiers operating in the linear and saturation regions (e.g., flip-flops or line receivers), the dictionary-building concept is valid. However, to determine all solutions, it is necessary to use one of the piecewise-linear methods employing a three-segment approximation of the characteristic of each amplifier modeled by a macro-model. For circuits containing unipolar transistors, particularly short-channel MOS transistors, no methods are known that guarantee the determination of all solutions. In such cases, to apply the proposed concept, one of the few methods for determining multiple solutions must be used, e.g., the deflation method [
42] or the homotopy method.
To illustrate the possibility of extending the diagnostic concept described in the paper to CMOS circuits, a Schmitt trigger implemented in CMOS technology, shown in
Figure 12, is considered. Using the BSIM 4.6 model for 50 nm technology and the nominal parameters shown in the figure, the circuit has three equilibrium points, two of which are stable. For the solutions determined by the method described in [
42], the current drawn from source V1 and the voltages at nodes 2, 3, and 4 are:
,
,
,
and
,
,
,
. Single hard faults were introduced into this circuit via simulation. In this case, the faults were modeled using a
resistor for a short circuit (
) and a
resistor for an open circuit (
). There are the standard values assumed in many papers. The assumed faults are marked in red in
Figure 22. In CMOS circuits, the effects of transistor manufacturing variations are usually modeled as global (uniform across the chip) variations in parameters such as transistor dimensions, gate oxide thickness, and threshold voltage. Typical deviations in these parameters can reach up to 10%, depending on the technology. Taking such variations into account, Monte Carlo analyses can be performed to determine the ranges of variation in measured quantities for selected hard faults. The identification of soft faults in this class of circuits, on the other hand, may involve determining the values of the aforementioned global technological parameters, local changes of the parameters, or values of local spot faults.
In the initial research aimed at generalizing the method to this class of circuits, and in the absence of laboratory verification, all tests were conducted via simulation. The most important aspect that received focus was the verification of the method proposed by the author in [
42] for hard faults. The method is a key tool, since, as previously mentioned, it does not guarantee the identification of all solutions. However, for CMOS circuits fabricated using nanotechnology, no method exists that can find all DC solutions. On the other hand, the method [
42] allows for the analysis of large circuits fabricated in any technology (provided, of course, that appropriate models are used), since all simulations, controlled by an external analysis program, are performed in SPICE. For all assumed S- and O- type faults, one or more solutions were determined using the method, confirming its usefulness for generating diagnostic dictionaries. At this preliminary stage, Monte Carlo analyses were omitted, as their execution is a standard SPICE analysis that, starting from the result of applying the method [
42], can determine appropriate intervals covering the measured quantities for a given fault.
Table 6 presents the results of a simulation of the circuit shown in
Figure 22 after introducing single hard faults. Based on these results, it is possible to construct a hard-fault dictionary using the procedure described for bipolar circuits.
Another important, unresolved question is the selection of a test for the soft fault dictionary. The following example illustrates the complexity of the problem in nonlinear circuits. The circuit shown in
Figure 5 is considered, and the voltage characteristic at node 4 (V4) is examined as a function of
. The characteristic is non-monotonic, just like the other characteristic shown in
Figure 11. The non-monotonicity of the characteristic results from a change in the sign of the voltage sensitivity to the parameter. The sensitivity of the voltage at node 4 to the resistances
and
was investigated in the range from 2 to 4 k
of
, within which the characteristic reaches an extremum (minimum), indicating that the derivative, i.e., the sensitivity, is zero. In the range of
between 2000
and 2469
, the sensitivities V4 to
and
have opposite signs and different absolute values, which allows their faults to be distinguished when measuring voltage at node 4. For example, at
equals 2200
, the sensitivity to
is
and to
equals
. At resistance
, the sensitivity to
is close to zero (
), while to
equals
. Taking
= 2470
, the sensitivity to
changes sign and equals
(to
is
). Assuming
greater than 2700
, both sensitivities have the same signs and magnitudes (e.g., for
= 3000
, the sensitivities are
). Such a result indicates that when measuring the voltage at node 4, faults in
and
become indistinguishable. Therefore, evaluating the test for soft faults solely based on sensitivity analysis of the nominal circuit may, in some cases, lead to erroneous conclusions. For this reason, diagnostic methods based on linearization near the operating point may be applied to small parameter deviations (e.g., 10–20%), for which a constant sensitivity can be assumed.
The obtained results confirm the usefulness of the proposed method for diagnosing analog circuits. The main advantage of the method is the ability to consider multiple operating points in both healthy and faulty circuits when developing the dictionaries. The findings have enabled extending the established concept of DC circuit diagnostics using a fault dictionary, thereby making it more reliable. Both hard and soft faults can lead to a situation in which a healthy circuit has a single solution, whereas a fault results in several solutions, whilst the opposite situation may also arise. An additional advantage of the method is the ability to identify the range of values for a single soft fault, also in circuits with multiple equilibrium points.
A fundamental drawback of the approach, stemming from the lack of effective methods for determining all DC solutions, is its limited applicability to small-sized bipolar circuits. For other classes of circuits and circuits with more than a dozen transistors, it is necessary to use methods that do not guarantee the determination of all equilibrium points. Another significant limitation is the method used to select tests for soft faults. Due to changes in the sign and magnitude of sensitivity to parameter variations in nonlinear circuits, the test selection poses a significant and original research challenge. A further challenge is to improve diagnostic accuracy while reducing the number of measurement points. It seems that measuring quantities in nonlinear circuits at different supply voltages or under varying load conditions may be a solution. Furthermore, the effective determination of multi-branch parametric characteristics in circuits with multiple equilibrium points is a crucial element, and solving this problem can significantly speed up the before-test phase.
A final aspect not addressed in this work is the influence of ambient temperature and self-heating on the effectiveness of the diagnostic process, particularly in high-power-dissipating circuits. As demonstrated in [
5], temperature variations, including self-heating, can alter the number of operating points. Thus, the methods for determining all or many DC solutions are also important in this aspect. The problem remains unresolved even at the stage of analyzing nonlinear circuits with multiple equilibrium points. There are a few reports in the literature that allow equilibrium points to be determined whilst accounting for self-heating, but these rely on simplified models and the assumption that the entire circuit is on a single chip. Therefore, the examples presented in this paper refer to low-power circuits, where self-heating effects are not as significant. Testing at different ambient temperatures can be incorporated by creating dictionaries for different temperatures. Creating a single dictionary for a wide temperature range is not an appropriate solution, as it leads to large Monte Carlo bands and reduces the number of recognized classes.
The proposed methodology can be extended to the diagnosis of multiple hard faults. However, considering all possible pairs, triplets, and so on increases the dictionary size dramatically. For this reason, as well as the fact that multiple faults are much less likely, any extension could focus on a few selected multiple faults. As shown in the paper [
5], multiple hard faults increase the probability of multiple equilibrium points, highlighting the benefits of the DC analysis method, which guarantees the determination of all operating points. In the case of multiple soft faults, the standard approach is to use SAT methods because there are an infinite number of parameter value combinations. Theoretically, it would be possible to determine multidimensional surfaces bounding from below and above the variations of the measured quantities as a function of the parameters, and to describe these surfaces using an
n-dimensional generalized piecewise-linear approximation (so-called section-wise piecewise-linear functions). However, in circuits with multiple operating points, these surfaces are extremely sophisticated, typically consisting of many separate parts, and therefore their description and subsequent use in the post-test phase would be extremely complex.
Some of the above issues will be the subject of further research.