A Scalable Ultra-Compact 1.2 kV/100 A SiC 3D Packaged Half-Bridge Building Block^†

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

This manuscript presents a scalable and ultra-compact 1.2 kV / 100 A PCB-embedded SiC half-bridge module with notable improvements in parasitic inductance, module size, thermal performance, and parallel current sharing. The die-integrated PCB structure, supported by Q3D extraction, electro-thermal simulation, and DPT measurements, is well executed. Overall, the paper is of good quality, and I recommend minor revision before acceptance.

My comments are as follows:

1. The authors provide Q3D-extracted parasitic parameters, but actual PCB manufacturing involves variations. It would be helpful to discuss how ±10% tolerance in layer spacing or copper thickness affects the parasitic inductance and resistance.

2. The manuscript lacks discussion on long-term reliability. Please comment on potential mechanical or thermal cycling reliability concerns.

3. Since the module targets fast-switching SiC applications, some discussion on EMI behavior or dv/dt-related effects would strengthen the work.

4. SiC MOSFETs typically operate at 150–200 °C. Please discuss whether the proposed package structure has been evaluated (or at least considered) for reliability at elevated temperatures such as 175 °C continuous operation.

Author Response

Please see the attachment.

Fig.6 had been changed

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

To fully exploit the high-speed potential of SiC MOSFETs, new packaging solutions must minimize parasitic inductance and enable scalable power expansion. This work addresses this need with a novel die-integrated PCB half-bridge module.  The optimized layout reduces power loop inductance to 2.3 nH and gate loop inductance to 3.8 nH, drastically cutting switching losses and voltage overshoot. Crucially, the symmetric architecture guarantees balanced parasitics, allowing direct module paralleling without external balancing networks. Verified by simulation and experimental testing, this packaging concept offers a manufacturing-friendly path to compact, high-performance power conversion systems.Generally, it is a good piece of work. Some suggestions for further improvement:

1. There is a critical error in the document structure. Section 7 is titled "Dynamic Characteristics," but the subsequent section is labeled "4. Discussion." This should be corrected to "8. Discussion" or "7. Discussion," and the content should be reviewed for continuity. The DPT results are currently presented in the (mislabeled) Section 7,
2. Some figures are referenced before they appear in the text (e.g., Fig. 15 is mentioned in Section 5, but the description of the copper layout would benefit from being placed closer to the initial structural explanation in Section 2). So please ensure all figures are cited in sequential order.
3. Switching Loss Analysis: The DPT waveforms (Fig. 21, 22) show excellent performance with low overshoot. However, the paper would be significantly strengthened by including a switching loss analysis

Also, there is no details on the switching waveforms of turn-on or turn-off, figure 22 is not details, zoom in please

4. It seems that the cooling is singl-side ,please make some comments why
5. A primary concern for any embedded package is the coefficient of thermal expansion (CTE) mismatch between the large SiC die, the PCB dielectric , and copper.It is good to have no bonding wires but some long-term reliability can be discussed, see and cite

https://ieeexplore.ieee.org/abstract/document/10753080

6. figure quality needs improvement. Fig. 20,16
7. 10 and 11, fonts too small to see

Author Response

Please see the attachment.

Figures and tables be improved.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

Comments and Suggestions for Authors

Many thanks for all the modificatins. I have no further comments to make, except that please check the typos thourgh the paper in the final version. Congradulations on the nice work!

Author Response

Thank you for your review.