Novel Low-Power CNFET-GAAFET Based Ternary 9T SRAM Design for Computing-in-Memory Systems

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

This manuscript addresses a critical need for energy-efficient computing-in-memory architectures by proposing a sense-amplifier embedded  ternary 9T SRAM cell, leveraging CNFET and GAAFET technologies. However, several aspects need to be addressed to improved this manuscript.

1. The three logic states (0, 1, 2) are mentioned, but their corresponding voltage levels are not defined.
2. Table 1 lists "Input Value" as -1, 0, +1, but the manuscript alternately refers to ternary states as 0/1/2. This mismatch confuses the logic mapping between voltage levels and ternary values.
3. The core advantage of CIMis parallel array-level computation, but the manuscript only tests single-cell XNOR operation without array-level performance or scalability analysis.
4. CNFET/GAAFET model parameters are not provided, such asCNT diameter, chirality, density.
5. Power is reported in "µW" but without specifying simulation time window, input pattern repetition, or whether leakage power. It is important parameters.

Author Response

Dear [Editor/Reviewer],

Thank you for your valuable feedback on our manuscript. We have carefully addressed all comments, and the detailed point-by-point responses are provided in the attached Document file.

Please refer to the attached document for our full clarifications and revisions.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The paper presents a low-power ternary 9-transistor (9T) SRAM design for computing-in-memory (CIM) systems, implemented using emerging transistor technologies. The proposed sense-amplifier embedded (SE) 9T SRAM cell supports ternary logic (three states) to improve storage density and computational efficiency over conventional binary SRAM. Here are some points and suggestions to improve the paper quality:

1. The paper mentions fabrication challenges for CNFET and GAAFET technologies. Could the authors elaborate on how device variability, defects, and yield issues might impact the performance and reliability of the proposed ternary SRAM cells in large-scale integration?

2. How does the proposed 9T ternary SRAM cell compare with prior ternary SRAM architectures in terms of area, stability, power, and speed? Are there trade-offs or limitations introduced by the sense-amplifier embedding or PTL-based ternary XNOR logic?

3. The design separates read and write paths to minimize read disturb. Is there experimental or simulation data quantifying read disturb rates, retention times, or error rates under typical operating conditions?

4. How does the proposed approach compare against state-of-the-art analog in-memory computing (IMC) technologies, such as RRAM and PCM-based designs, in terms of density, linearity, and scalability for multiply-accumulate (MAC) operations? It is recommended to compare the achieved results with the works in [1] and [2].

[1] 10.1109/OJSSCS.2024.3432468;

[2] 10.3390/electronics10091063.

Author Response

Dear [Editor/Reviewer],

Thank you for your valuable feedback on our manuscript. We have carefully addressed all comments, and the detailed point-by-point responses are provided in the attached Document file.

Please refer to the attached document for our full clarifications and revisions.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

Authors of this manuscript propose a CNFET- and GAAFET-based design of a SE 9-transistor ternary SRAM that can reduce the power consumption —from 109.2 W in FinFET to 26.73 W in GAAFET —and an ultra-low power of only 0.0004 W in CNFET.

Although that authors are dealing with real active research areas like CIM, ternary logic, and CNFET/GAAFET, there are a lot of issues (most of them are major) that needs to be addressed before this manuscript can be published.

My main concern is that numerical results seem like physically imposible

As stated at table 3, the power consumption of FinFET is 109.2 µW, of GAAFET is 26.73 µW and CNFET is 0.0004 µW. So CNFET consumes 400 pW, which is far below specs and realistic dynamic power for any SRAM operation at ns-scale switching.  Authors are no providing any simulation parameters to justify such values.

Please also note that in abstract those consumption numbers are mentioned as W which is obviously a mistake and an inconsistency

The total delay for FinFET is given as 0.01108 ns (11 ps), which contradicts with earlier tables showing operation delays of ≈1–3 ps. This arithmetic inconsistency indicates either calculation error or misinterpretation of HSPICE results.

Manuscript is well written, including clear circuit diagrams and waveforms but the numbers that are presented in this research paper can’t be correct. It is physically impossible while at the same time there are several inconsistencies

Author Response

Dear Reviewer/Editor,

Thank you for your detailed and valuable feedback on our manuscript. We have prepared a point-by-point response addressing all comments.
Please refer to the attached document for the complete set of answers and corresponding revisions made in the manuscript.

Author Response File: Author Response.pdf

Reviewer 4 Report

Comments and Suggestions for Authors

Dear Authors,

Thank you for the submission of your manuscript titled “Novel Low Power CNFET GAAFET based Ternary 9T SRAM Design for Computing in Memory Systems.” The topic is interesting and relevant to current research in in memory computing and emerging transistor technologies. The idea of evaluating ternary SRAM using CNFET and GAAFET devices has potential. I appreciate the effort behind this work.

After carefully reviewing the manuscript, I would like to offer several suggestions that may help improve clarity, presentation, and scientific depth.

1. The introduction can be strengthened to better explain what specific research gap is being addressed. It is not very clear how this 9T ternary architecture is different from the existing ternary SRAM or XNOR SRAM structures in past work. Highlighting the unique contributions will make the paper stronger.
2. The process of modeling, simulation setup, and device parameters needs more detail. It would help readers if you explain the supply voltage, technology node, transistor sizing, channel length, threshold voltage assumptions, and any simulation models used. Without this information, results are difficult to validate or reproduce.
3. The fabrication discussion is useful but remains general. It may help to connect the fabrication limitations to the proposed design and explain whether these limitations affect large scale SRAM implementation.
4. Some figure captions are unclear or do not match the information shown. For example, Fig. 7 explanation is confusing. Please ensure that captions clearly describe what the figure presents and what readers should understand from it.
5. The ternary logic based XNOR operation is interesting. However, the explanation of the full functionality of the ternary truth table is not very clear. A clearer logical flow would make Section 3 easier to understand.
6. The power and delay values are promising. However, the interpretation needs to be deeper. It will help if you explain the physical reason behind the large power reduction in CNFET or the much lower delay in GAAFET. A short explanation based on device physics would support the conclusions.
7. The results would be stronger if compared with other published ternary SRAM papers, not only the previous 10T SRAM work. This will allow the reader to see where the presented design stands in the broader research landscape.
8. The conclusion is readable but may overstate the results. The paper does not provide experimental hybrid CNFET GAAFET design, yet the statement suggests it is hybrid. It may be better to describe CNFET and GAAFET separately and clearly state that future work may explore hybrid implementation.
9. The manuscript is understandable, but improvements in sentence flow, simple grammar correction, and clearer expression will benefit readability. A short proofreading pass will improve presentation.

Overall, the manuscript has potential and addresses an interesting application area. With additional detail in the methodology, clearer explanation of ternary operation, improved discussion of the results, and small corrections to figures and writing, the paper can become stronger.

Comments on the Quality of English Language

The overall English in the manuscript is understandable, however it would benefit from minor improvements in sentence clarity and structure. In several places the explanation flow is slightly difficult to follow, especially where technical terms are introduced quickly without transition. A careful proofreading to improve grammar, simplify sentence construction, and ensure consistent terminology will help improve readability. The comments are not major, and they can be addressed without changing the technical content.

Author Response

Dear Reviewer/Editor,

Thank you for your detailed and valuable feedback on our manuscript. We have prepared a point-by-point response addressing all comments.
Please refer to the attached document for the complete set of answers and corresponding revisions made in the manuscript.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

It can be accepted in this form.

Author Response

We thank the reviewer for the positive assessment. We have revised the manuscript to improve clarity and English language throughout, addressing the noted sections. We appreciate the helpful feedback.

Sincerely,
The Authors

Reviewer 2 Report

Comments and Suggestions for Authors

The Authors have carefully addressed all the raised points. The paper can thus be accepted in the present form.

Author Response

We thank the reviewer for the positive assessment. We have revised the manuscript to improve clarity and English language throughout, addressing the noted sections. We appreciate the helpful feedback.

Sincerely,
The Authors

Reviewer 4 Report

Comments and Suggestions for Authors

Dear Authors,

Thank you for submitting the revised version of your manuscript. I appreciate the effort made to carefully address the comments raised during the first round of review. The revised manuscript shows clear improvement in terms of technical clarity, methodology description, and overall structure. The topic remains timely and relevant, and the results are now presented in a more transparent and understandable manner.

The following minor comments are provided to further improve the quality and clarity of the manuscript before final acceptance.

1. The introduction now provides a clearer background and motivation for ternary SRAM and computing in memory systems. However, the novelty statement could still be slightly refined. A short and explicit sentence summarizing the key contributions compared to prior XNOR SRAM designs would help readers quickly understand the value of this work.
2. The description of the simulation setup and device parameters has been significantly improved. This is appreciated. As a minor enhancement, please ensure that all key operating conditions such as the supply voltage and any output loading assumptions are clearly stated in one place to improve reproducibility.
3. Most figures and tables are clearer than before. However, a few figure captions could still be simplified and made more consistent to avoid confusion, especially where original and revised designs are discussed. Please also check for any remaining placeholder labels or formatting inconsistencies.
4. The explanation of the ternary XNOR operation is improved and easier to follow. As a small refinement, the logic table could be made more reader friendly by briefly clarifying the notation used for the zero states to avoid ambiguity for non specialist readers.
5. The results are clearly presented and support the conclusions. The discussion explaining why CNFET achieves ultra low power and why GAAFET offers better delay performance is appropriate. You may further strengthen this section by briefly linking these trends more explicitly to device level characteristics.
6. The conclusion is well written and consistent with the presented results. As a minor suggestion, please ensure that references to hybrid CNFET and GAAFET implementation are clearly framed as potential or future work, rather than something already demonstrated in this study.
7. The overall English has improved. A final proofreading pass is recommended to correct minor grammatical issues and improve sentence flow in a few places. This will further enhance readability and presentation quality.

 

Overall, the revised manuscript addresses the major technical concerns raised earlier. The remaining points are minor and mostly related to clarity and presentation.

Comments on the Quality of English Language

The quality of English in the revised manuscript has improved compared to the earlier version and the text is generally clear and understandable. Minor issues related to sentence flow, wording, and consistency still remain in a few sections, particularly in figure captions and the discussion. A final careful proofreading will help improve clarity and ensure a smooth reading experience.

Author Response

We sincerely thank the reviewer for the positive evaluation of the revised manuscript and for the detailed and constructive minor comments. We are pleased that the revisions have improved the technical clarity, methodology description, and overall presentation.

In response to the reviewer’s suggestions, we have:

• Refined the novelty statement in the Introduction with a concise sentence clearly highlighting the key contributions relative to prior XNOR SRAM designs.

• Consolidated all key simulation parameters and operating conditions (including supply voltage and loading assumptions) into a single, clearly identified section to improve reproducibility.

• Simplified and standardized figure captions, corrected minor formatting inconsistencies, and verified that no placeholder labels remain.

• Clarified the notation used in the ternary logic table to make it more accessible to non-specialist readers.

• Strengthened the discussion by explicitly linking the observed power and delay trends to relevant device-level characteristics.

• Revised the conclusion to clearly frame hybrid CNFET–GAAFET implementations as future work or ongoing research directions, rather than results already demonstrated.

• Performed a final proofreading pass to address remaining minor language and flow issues, particularly in figure captions and discussion sections.

We appreciate the reviewer’s thoughtful feedback and believe these final refinements further enhance the clarity and quality of the manuscript.

Sincerely,
The Authors