An Efficient Multi-Output LUT Mapping Technique for Field-Programmable Gate Arrays

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The provided manuscript is well-structured and presented. The authors propose the technique for mapping of logical elements with multiple outputs. The proposed methods are explanad clear.
But it is necessary to consider following recommendations of improvement.

1. It is not clear is really Figures 2 (a) and (b) represent single-output and dual-output configurations. Some clarification is required because currently both representing single-output scheme. The dashed line in Figure 2 (a) divides inputs by groups 1-5 and 2-6, but it is not agree with the circuitry representation in Figure 1 (b), where the range 2-6 belongs to both and the input 1 determines which of subLUT outputs would be connected to the primary out (D6). The same in Figure 4 and 5 (a). Are the nodes associated with the specific inputs of the LUT? Please clarify it. It can be highlighted in the INtroduction section with specifying detailed the basic LUT structure with 6 inputs including side-fanout lines. It will simplify the understanding of the proposed algorithms with nodes mapping in next section.

2. It is possible to help readers by adding of structure of all sections in the article after the last paragraph at the end of Introduction section.

3. The current version of Conclusions section looks like a brief draft. The detailed information should be provided here instead of 'Several high-efficiency algorithms'. Please extend Conclusions section with highlighting all results of the work. 

4. Also, the Discussion section can be added before the Conclusions sectioin. It is reasonable to discusse here the drawbacks of known LUT spliting algorithms and the details of the obtained comparison of resources, including the Appendix A. It will help readers to understand the place of your work within the rest theoretical studies.

5. Please also consider following recommendations.
- Please represent formulas (lines 99 and 102) as numerated formulas according to MDPI template.
- The reference to figure in text should be before the figure, same for tables and listings. Please consider moving of Figure 3 to section 2.
- Please ensure the explanation for all abbreviations before the first use (ASIC, CPU) even if it is provided in the Abbreviations section. It should be done once, there are repeated definitions in the text (LUTs).
- Please consider the possibility of extending the keywords to make it more relevant for the search results. CLB, Ultrascale+, VTR and ABC tools can be added.
- The Algorithms 1, 2, 3 can be represented with the use of Listing 1, 2, 3 and with mentioning in the comment text the details.
- Please add one line before Table 1 and Table 2 or use the Paragraph options from MDPI template for the text before the table.
- Please use the specified MDPI contribution attributes in section Author Contributions.
- It is practically reasonable to extend the analysis part with referencing to latest publications with description of FPGA synthesis tools.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

1. Can the authors improve the abstract and the introduction by giving more advantages of using dual output than just the area reduction advantage.
2. Can the authors add more detail as to the programming language or languages that can be used to program the algorithm in method.
3. The authors have indicated that an intel i9CPU with 32 GB RAM can be used to run the program is it possible to use other processors can they give a range in method.
4. Maybe another graph to compare the advantages of dual output to single output can be given such as speed of resultant processing in results
5. The number of references could be increased to 30.

Comments for author File: Comments.pdf

Author Response

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Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors The paper is well written and addresses an important topic in FPGA logic mapping.
Consider adding a brief discussion on the runtime complexity / mapping time of the proposed algorithms. While the primary focus is on LUT count reduction, a reader may wonder about the computational cost. If the runtime overhead is minimal (or comparable to ABC), mentioning this would add practical value of your work. Or if there is a runtime trade-off, it would be good to for the reader to know.
There are a couple of oddities that can be easily fixed: The section title “1. Backgrounds” -> “Background” (singular). Phrases like “fewer input numbers” -> “fewer inputs” for clarity.
In Section 4 where you compare two FPGA architectures, you noted that the Stratix architecture achieved 59% dual-output LUT usage versus 32% in UltraScale+, why can Stratix benefit more from it? Is it because Stratix offers more flexibility? A short explanation of this would reinforce the point that architecture features influence the mapping outcome.
It'd also be good to briefly comment about the limitations of your approach. Are there cases where the dual-output mapping provides little benefit? While your results show consistent improvements, stating the assumptions or limits of your technique (even saying that it targets dual-output LUT architectures and assumes sufficient available LUT inputs) can make the paper more complete.
The work would also benefit from a short discussion of future directions, e.g., could the interconnection-based mapping concept be extended to even larger LUT structures? This is optional, but could be a nice ending to the paper.
Overall, only minor revisions are needed, since the approach and results are good.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf