Wafer-Level Amplitude Equalizer Based on an Integrated Passive Device Process with Two Resonance Points for Wavy In-Band Transmission

Abstract

Amplitude equalizers play an important role in microwave transmission systems, and their performance can directly improve the signal transmission quality. Nowadays, the miniaturized equalizer is in good need of a highly integrated radio frequency (RF) front end. In this paper, a wafer-level amplitude equalizer based on an integrated passive device (IPD) process is proposed. Moreover, the equalizer circuit containing two resonance points within the transmission frequency band is also proposed. The amplitude equalizer operates at the center frequency of 3.88 GHz, with two resonance points of 2.9 GHz and 5.2 GHz; the minimum insertion loss is 1.17 dB, the maximum attenuation is 4 dB, and the in-band voltage standing wave ratio (VSWR) is less than 1.6:1. All the measured results are in good agreement with the designed results. The size of the proposed equalizer is 0.8 mm × 0.65 mm × 0.1 mm (0.011λ × 0.008λ × 0.001λ), which shows great potential in the miniaturization application of the RF microsystem. Furthermore, the new equalizer circuit with two resonance points is especially suitable for wavy in-band transmission.

1. Introduction

Due to the dispersion effects of microwave transmission, as well as the inherent characteristics of the active components (i.e., amplifiers and mixers), gain fluctuations inevitably occur within the operating frequency bands, which may have a serious impact on the quality of signal transmission. Therefore, the in-band flatness has become an important parameter for the design of microwave circuit systems [1,2,3]. To improve the in-band flatness, the equalizer was first proposed by F. E. Terman in the 1940s [4]. D. J. Mellor derived the topology prototype for the matched microstrip equalizer in 1977, which led to significant improvements in the performance and size of the equalizers [5]. Subsequently, waveguide and coaxial implemented equalizers, microstrip equalizers, substrate-integrated waveguide (SIW) equalizers, and semi-lumped equalizers were proposed [6,7,8,9,10]. However, with the development of high-precision microwave communication, microwave measurement equipment, bio-medical detection, and other applications, the amplitude equalizer requirements of in-band flatness and miniaturization are becoming increasingly high [11,12,13], and the traditional design methods may not meet the demands.

Nowadays, miniature passive devices are fabricated on rigid or flexible substrates for specific applications [14,15,16]. Among them, passive devices based on the integrated passive device (IPD) process can be fabricated on wafers (such as silicon, GaAs) used in semiconductor processes and can be compatible with the complementary metal oxide semiconductor (CMOS) process for wafer-level production [17,18]. Furthermore, IPD processes have the advantage of high processing line accuracy and consistency compared with processes on ceramics or printed circuit boards (PCBs). RF passive devices such as filters, power dividers, and baluns are designed and fabricated based on the IPD process, which shows great potential for hybrid integration and applications in RF microsystems [19,20,21,22,23]. Moreover, traditional equalizer circuits always have one resonance point and can only adjust the microwave system in-band flatness with a single slope. However, the in-band transmission gain is always wavy, adjustment with a single slope is difficult to meet the requirement, and the cascade of multiple equalizers greatly increases the circuit size [4,24]. Therefore, equalizers with multiple slope adjustment capabilities are needed, which means that the equalizer with multiple resonance points needs to be designed and fabricated.

In this paper, a wafer-level amplitude equalizer based on the IPD process is proposed. First, an equalizer circuit topology with two resonance points is proposed, integrating a bridged-T attenuator circuit and a frequency selection circuit. Then, the wafer-level equalizer is designed and fabricated based on the GaAs-IPD process with a compact size of 0.8 mm × 0.65 mm × 0.1 mm (0.011λ × 0.008λ × 0.001λ). The equalizer operates at the center frequency of 3.88 GHz, with two resonance points of 2.9 GHz and 5.2 GHz; the minimum insertion loss is 1.17 dB, the maximum attenuation is 4 dB, and the in-band voltage standing wave ratio (VSWR) is less than 1.6:1. All the measured results are in good agreement with the designed results. Thus shows great potential in the miniaturization application of RF microsystems. Furthermore, the equalizer with two resonance points is especially suitable for wavy in-band transmission.

2. Circuit Design and Fabrication Process

The proposed equalizer circuit in this work consists of an attenuator circuit and a frequency selection circuit. The circuit topology of the proposed equalizer is shown in Figure 1. The attenuator circuit determines the maximum attenuation of the equalizer. Among the existing attenuator circuits, the bridged-T attenuator circuit has the advantages of simple structure, good impedance matching, and flexible design [6,10]. The structure of the bridged-T attenuator is shown in unit ① in Figure 1.

The two series resistors R₀ are equal to the source/load impedance (Z₀) of 50 ohm. And, resistance R₁ and R₂ can be calculated as follows:

$$R_1={{\rm Z}}_0({10}^{{\displaystyle \frac{A}{20}}}-1)$$

(1)

$$R_2=Z_0({\displaystyle \frac{1}{{10}^{\frac{A}{20}}-1}})$$

(2)

where A represents the expected attenuation value of the bridged-T attenuator. The attenuation can be adjusted by changing the value of R₁ and R₂ [10].

The working band of the equalizer can be determined by the frequency selection circuit. In this paper, unit ② and unit ③ in Figure 1 constitute the frequency selection circuit, and the circuit topology of the equalizer with two resonance points is proposed. As shown in unit ② in Figure 1, two resonance points can be obtained within the band by a series connection of a parallel resonance circuit and a series resonance circuit. In detail, the parallel resonance circuit and the series resonance circuit in unit ② can each produce one resonance point. The resonance point frequency (f) of each resonance circuit can be obtained by the following equation:

$$f={\displaystyle \frac{1}{2\pi \sqrt{LC}}}$$

(3)

where L and C represent the inductance and capacitance of the resonance circuit, respectively. The center frequency (f₀) of the equalizer can be obtained by the equation shown as follows:

$$f_0=\sqrt{f_{\mathrm{s}}{f}_{\mathrm{p}}}$$

(4)

where f_s and f_p represent the resonance point frequency of the series resonance circuit and parallel resonance circuit. Furthermore, the unit ③ circuit is added to improve the impedance matching of the equalizer and constitutes the selection circuit with unit ②.

The IPD process has the advantage of compatibility with the semiconductor processes. The GaAs semiconductor process, as a mainstream semiconductor process, is widely used in the manufacture of RF amplifiers and mixers and has the characteristics of low cost and simple processing. Therefore, this work selects the IPD process based on the GaAs wafer and tapes out the chips to the GaAs process foundry. Figure 2 shows the multi-layer structures of the IPD process on the GaAs wafer. A series of layers such as gold layers (i.e., M₀, M₁, and M₂), Si₃N₄ layers (i.e., N₁, N₂, N₃, and VM), and polyimide layers (i.e., PV) can be fabricated and used for forming a MIM (metal–insulator–metal) capacitor, a high-Q value spiral inductor, and a thin-film resistor; then, the circuit shown in Figure 2a can be constructed. The function and thickness of layers, the structural relationship between the layers, and the process steps are similar to the descriptions mentioned in the previous work [19]. The back gold layer (M₀) with a thickness of 2 μm is electroplated on the bottom surface of the GaAs wafer, which is used as the equivalent ground of the device. The SiN adhesion layer (N₁) with a thickness of 0.16 μm is grown on the surface of the GaAs wafer. And, the TaN thin-film resistor layer is deposited by sputtering deposition. Next, the first metal layer (M₁) is patterned and grown with a thickness of 1 μm, which is used for the inductor connecting line and the lower electrode plate of the MIM capacitor. The SiN dielectric layer (N₂) with a thickness of 0.4 μm is grown, and the second metal (M₂) is electroplated with a thickness of 4 μm, which is used for the planar spiral inductor and the upper electrode plate of the MIM capacitor. Next, the third SiN passivation layer (N₃) with a thickness of 5 μm is grown, which aims to protect the circuit. After the circuit structure was completed on the GaAs wafer, the wafer was divided into multiple independent chips by dicing process.

3. Results and Discussion

In this work, the required maximum attenuation of the amplitude equalizer is 4 dB, and the equalizer operates at the center frequency of 3.88 GHz, with two resonance points of 2.9 GHz and 5.2 GHz. According to Equations (1) and (2), the resistance R₁ and R₂ can be obtained as shown in

Table 1. Components’ values of the proposed amplitude equalizer.

Component	Value	Component	Value
Ls	2.654 nH	Cs	0.597 pF
Lp	0.663 nH	Cp	2.389 pF
R0	50.0 Ω	R2	85.6 Ω
R1	29.2 Ω

. Based on the derivation of Equations (3) and (4), the chip size of IPD circuit models (i.e., inductor and capacitor) and simple design are also considered, the component values are set as the same value in units ② and ③, and the models of inductors and capacitors are selected as the value in Table 1.

Based on the IPD process, the electromagnetic field model of the equalizer is designed with FEM software HFSS (Ansys Electronics Desktop 2020 R2). The layout of the inductor, capacitor, resistor, and ground–signal–ground (GSG) pads are marked in Figure 3a. Figure 3b shows the fabricated equalizer, and its physical size is only 0.8 mm × 0.65 mm × 0.1 mm. Then, the equalizer is measured using a vector network analyzer (Keysight N5247A, Santa Rosa, CA, USA) with on-wafer GSG probes (Cascade ACP), as shown in Figure 4.

The measured results of S-parameters are shown in Figure 5a with a solid line and show that the maximum attenuation of the amplitude equalizer is ~4 dB; the equalizer operates at the center frequency of 3.88 GHz, with two resonance points of ~2.9 GHz and ~5.2 GHz. The minimum insertion loss is 1.17 dB, and the in-band return loss is greater than 15 dB. Moreover, the VSWR is less than 1.6:1, as shown in Figure 5b, which means that the equalizer has good matching with source/load impedance. The simulated results are shown with a dashed line. In summary, all the measured results are in good agreement with the designed results, and slight deviation is mainly due to the error brought by the test environment. Therefore, the feasibility of the proposed circuit and the accuracy of the IPD process design method are verified.

Table 2. Performance summary of the proposed amplitude equalizers.

Reference	Process	Design Method	Wafer -Level	Integration Form	Return Loss (dB)	Resonance Point	Size (mm2)	Operating Frequency (GHz)
[6]	SiGe BiCMOS	Microstrip lumped	Yes	On chip	≤−10	One	0.429	0.2–1.85
[7]	Al2O3 ceramic	Coplanar waveguide	No	Monolithic	≤−11	One	30.4	6–9
[8]	Al2O3 ceramic	Dual-mode SIW	No	Monolithic	/	Two	186.2	13–13.5
[9]	PCB	Microstrip Semi-lumped	No	Monolithic	/	One	525	2–3
[10]	GaAs IPD	Microstrip lumped	Yes	On chip	≤−20	One	/	2–20
This work	GaAs IPD	Microstrip lumped	Yes	Monolithic	≤−15	Two	0.52	1–7

shows a list of concerned performance parameters of various amplitude equalizers. In reference [6], the equalizer is integrated on a system-on-chip (SOC) chip fabricated by the SiGe BiCMOS process, which also has a compact size of the equalizer by the IPD process. However, the equalizer based on the IPD process has the capability of miniaturization and monolithic integration. This means that the IPD equalizer has better integration flexibility, which is more suitable for hybrid integration and application in RF microsystems. The amplitude equalizers designed by coplanar waveguide and SIW methods and fabricated on Al₂O₃ ceramic are presented in [7,8], which have the capability of monolithic integration and larger layout size. Although the equalizer designed by the dual-mode SIW method also has two resonance points, it increases the difficulty of design and device size compared with the method proposed in this work. The equalizer in [9] is designed by the semi-lumped microstrip method and fabricated by the PCB process on a microwave board, which has a great improvement when compared to the equalizers designed with the distributed microstrip method. However, it is still larger in size compared to the equalizer proposed in this work. Compared to the equalizer in [10], the proposed equalizer is monolithic and improves the circuit topology with two resonance points, which means better adjustment capability. In summary, the proposed amplitude equalizer in this paper has obvious advantages in circuit topology, layout size, integration flexibility, and adjustment capability.

4. Conclusions

This paper proposed a wafer-level amplitude equalizer based on the GaAs-IPD process. A circuit topology of the equalizer with two resonance points is also proposed. The wafer-level amplitude equalizer with two resonance points is designed and fabricated based on the IPD process. The measured results show good agreement with the design parameters. Wafer-level amplitude equalizers with compact size show great potential in the miniaturization application of the RF microsystem. Furthermore, the equalizing effect with two resonance points may have good applications in the adjustment of wavy in-band transmission of microwave systems. However, only two resonance points can be obtained by the proposed circuit topology, including the series connection of a parallel resonance circuit and a series resonance circuit in frequency selection circuit, and circuit topologies of equalizers with multiple resonance points need to be studied in the future.