Design and Process Implementation of Silicon-Based Carrier for 100 G/200 G Electro-Absorption Modulated Laser Chips

Abstract

This paper presents a highly stable and integrated silicon-based carrier with broad application prospects. Traditional 800 G optical modules employ architectures based on aluminum nitride (AlN) carriers with externally mounted capacitors. However, such AlN-based architectures suffer from issues including high process complexity, elevated costs, poor environmental temperature adaptability, and difficulties in systematic crosstalk optimization. To address these challenges, this study conducted research on coplanar waveguide (CPW) transmission line structure design and optimization, high-density capacitor design and process implementation, and multi-channel crosstalk suppression. Based on these investigations, a silicon-based integrated carrier was designed and fabricated, incorporating resistors, capacitors, high-speed signal lines, and preformed AuSn structures. Test results demonstrate that the CPW transmission line structures fabricated on the silicon carrier exhibit excellent radio frequency performance with transmission losses below 1 dB within 67 GHz. The developed high-density capacitor structure achieves a remarkable capacitance density of 26.83 nF/mm² and withstands voltages exceeding 24 V at 1 μA current, reaching state-of-the-art levels. This paper also proposes crosstalk reduction solutions including increased channel spacing, the addition of wave-absorbing materials, and the implementation of metal barriers. Experimental results confirm that the developed integrated carrier demonstrates outstanding performance and reliability in high-frequency communications and optoelectronic devices.

1. Introduction

With the explosive growth in demand for high-speed optical modules driven by artificial intelligence [1,2,3] and data centers, 800 G and 1.6 T optical modules are becoming mainstream. Traditional 800 G optical modules [4,5] use AlN ceramic substrates to mount EML (Electro-absorption Modulated Laser) chips, capacitors, and other discrete components. Compared to CPW transmission lines based on AlN substrates, CPW transmission lines based on Si substrates offer significant advantages: Transmission loss-CPW transmission lines based on Si substrates exhibit a transmission loss of less than 1 dB within 67 GHz, demonstrating excellent high-frequency performance. In contrast, CPW transmission lines on AlN substrates show inferior loss control in the low-frequency range (e.g., within 67 GHz). Return loss-CPW transmission lines based on Si substrates have a return loss of less than −12.41 dB within 50 GHz, outperforming CPW transmission lines on AlN substrates. Integration and cost-CPW transmission lines based on Si substrates address issues such as high process complexity and high costs associated with traditional AlN substrates in optical modules. By directly integrating passive components like resistors and capacitors on the silicon substrate and pre-depositing AuSn bonding areas, they enable chip-on-carrier (COC) packaging for EML chips, significantly reducing packaging costs and improving integration [6] and meeting the transmission requirements of single-wavelength 100 G/200 G.

2. Theoretical Framework

High-speed silicon-based integrated carriers are critical components for optoelectronic device packaging (e.g., EML lasers), requiring low loss, high reliability, and miniaturization. Compared to traditional AlN ceramic substrates, silicon substrates offer superior scalability, enabling the direct integration of passive components (e.g., resistors, capacitors) and supporting high-density circuit design. Key design elements include the following:

2.1. Low-Loss Coplanar Waveguide (CPW) Transmission

Based on the material parameters of the silicon substrate (relative permittivity ε_r = 11.9), a 55 GHz high-frequency RF structure for EML packaging was designed [7,8,9]. A backless CPW transmission structure was selected, and a transmission line model was established according to the actual silicon substrate structure. The CPW transmission line loss reflects the laser’s data transmission capability [10]. By optimizing physical parameters (Figure 1), a transmission line structure meeting design requirements was achieved. Subsequently, bonding pads for chips and PCBs were added, and their S-parameter characteristics were calculated to ensure compliance. Finally, a complete transmission model (EML + integrated carrier + PCB) was established, optimizing pad positions and bonding methods to achieve excellent transmission characteristics. The final design (

Table 1. CPW transmission line model parameters.

Elect length	4.034 λ
Elect length	1452.2 degrees
Elect length	24.186 mm (air line euiv.)
Delay	80.676 ps
1.0 Wavelength	2.479 mm
Vp	0.413 fraction of c
εeff	5.85
Shape factor	0.500
Dielectric: εr	11.8
Frequency	50 GHz
Length units	mm
Material	Silicon (single crystal)

for basic model parameters and

Table 2. Material physical parameters.

Parameter	Relative Permittivity	Relative Permeability	Bulk Conductivity	Dielectric Loss Tangent
Aluminum	1	1	38 × 106 siemens/m	0
Silicon Substrate	11.9	1	0	0
Polysilicon	11.9	1	61 × 106 siemens/m	0
SiO2	4	1	0	0
Aluminum	1	1	38 × 106 siemens/m	0

for physical parameters.) ensures a transmission loss of ≤1.2 dB and a return loss of ≤−12.41 dB within 50 GHz.

2.2. Multi-Channel Crosstalk Suppression

To intuitively investigate multi-channel crosstalk issues, a dual-channel structural model was established. This model visually demonstrates the isolation strength between signals during simultaneous dual-channel transmission, thereby revealing crosstalk problems through isolation metrics [11]. By optimizing the dual-channel model-such as adding channel barriers, absorbing materials, etc. The isolation between channels can be directly evaluated. Subsequent process optimizations in multi-channel models will further suppress crosstalk based on these improvements.

• Dual-Channel Model (Figure 2).

(1) Silicon Substrate: An accurate RF transmission structure model is established. RF matching pads use 50 Ω resistors in series with 10 nF capacitors to centralized ports, with a single GND gold wire bonded to the PCB. (2) EML Chip: Modeled with InP material at a 1:1 scale, RF pad diameter: 60 μm. (3) PCB: A double-layer board model (thickness: 5 mil, material: Rogers RO4350, ε_r: 3.66) with 3 mm channel spacing. The isolation simulation curve shows a worst-case isolation of −6.6 dB at 26.23 GHz.

2.

Adding Metal Barriers Between Channels (Figure 3):

The model remained unchanged except for adding copper barriers (thickness: 0.3 mm, height: 0.3 mm above air gap) between channels. The isolation simulation curve (Figure 3) shows a worst-case isolation of −19.17 dB at 26.67 GHz.

3.

Adding Absorbing Material Cover (Figure 4):

The model remained unchanged except for adding an absorbing material cavity (thickness: 0.3 mm, ε_r = 25, μ_r = 1.05, electrical loss tangent = 0.5, magnetic loss tangent = 1) above the Si substrate. The isolation simulation curve (Figure 4) shows a worst-case isolation of −29.54 dB at 29.52 GHz.

4.

Adding Bonding Gold Wires (Figure 5):

The model remained unchanged except for increasing the number of ground gold wires from one to two between the Si substrate and PCB. The isolation simulation curve (Figure 5) shows a worst-case isolation of −9.35 dB at 27.5 GHz.

5.

Increasing Channel Spacing (Figure 6):

The model remained unchanged except for increasing the channel spacing from 3 mm to 6 mm. The isolation simulation curve (Figure 6) shows a worst-case isolation of −14.72 dB at 24.68 GHz.

2.3. High-Density Capacitor Design

The capacitance formula for low-resistivity silicon-based capacitors is expressed as [12]

$$\mathrm{C}={\displaystyle \frac{{\mathrm{\epsilon }}_0{\mathrm{\epsilon }}_{\mathrm{r}}\mathrm{S}}{\mathrm{d}}}$$

(1)

where ε₀ is the vacuum permittivity, ε_r is the relative permittivity of the dielectric layer, S is the electrode area, and d is the dielectric thickness. High-density capacitors are achieved by increasing electrode area, reducing dielectric thickness, and using high-permittivity materials.

Silicon-based high-density capacitors are fabricated using MEMS bulk silicon processes. By etching high-aspect-ratio microstructures [13] on the silicon surface, the effective electrode area is significantly increased, achieving high capacitance density. High-quality dielectric growth ensures low leakage current and high breakdown strength. These capacitors exhibit high capacitance density, high breakdown voltage, low-temperature drift, and scalability.

3. Experiments

3.1. CPW Transmission Line Optimization

Based on the CPW structural parameters and material properties, a transmission structure is modeled [14,15]. After optimizing physical parameters, the simulated transmission loss is ≤0.3 dB and the return loss is ≤−20 dB within 50 GHz (Figure 7), meeting design requirements.

Bonding pads for chips and PCBs are added (Figure 8), resulting in a transmission loss of ≤0.7 dB and a return loss of ≤−12 dB within 50 GHz.

A full simulation model incorporating PCB and EML chip structures (Figure 9) achieves a transmission loss of ≤1.2 dB and a return loss of ≤−12.41 dB within 50 GHz.

3.2. High-Density Capacitor Process Optimization

• Dielectric Material Optimization

A SiO₂/Si₃N₄/SiO₂ (ONO) composite dielectric (Figure 10) is deposited via LPCVD (500-1500-500 Å thickness). This achieves ε_r ≈ 7.5, leakage current < 1 μA, and breakdown voltage improvement from 7–8 V to 23–24 V.

2.

Three-Dimensional Electrode Design

Deep trench etching (aspect ratio 21.4:1) creates high-surface-area silicon pores (Figure 11). MATLAB (R2023b) simulations optimize electrode spacing (0.5 μm), increasing surface area by 262 times. The final capacitance density is 26.83 nF/mm².

3.

Etching Process Improvement

STS ICP etcher optimizes SF₆/C₄F₈ gas ratio and RF power. A low-frequency source (380 kHz) eliminates “notching” and “scalloping” effects. Over-etching is reduced, and sidewall smoothness is enhanced (Figure 12).

4.

Polysilicon Filling Optimization

LPCVD-deposited doped polysilicon (>10²⁰ atoms/cm³) with 1.6 μm thickness and high-temperature annealing (900–1000 °C) reduces wafer warpage from 302 μm to 3.4 μm and resistivity to 4.6 Ω/block. Cross-sectional SEM (Figure 13) shows uniform polysilicon coverage.

5.

High-Speed Silicon Carrier Performance Testing

Firstly, the prepared AuSn was subjected to melting and eutectic evaluation, with the melting and push–pull force results shown in the figure above. After melting at 360 °C, the surface of AuSn was smooth and free of particles, indicating that the prepared AuSn exhibited good performance and a normal melting point. As shown in Figure 14, after melting, a chip was attached to it, and a push–pull force test was conducted. The results showed that fracture occurred at a force of 505 g, at the center of the chip rather than at the interface between AuSn and the chip, indicating that AuSn has good, stable, and strong properties.

The capacitance and resistance of the high-speed Si-based carrier were tested, as shown in

Table 3. High-speed silicon carrier capacitor and resistor test data.

Category	Design Value	Test Mean	Variance
C1	3 nF	2.99 nF	0.001 nF2
C2	10 nF	10.54 nF	0.011 nF2
R	50 Ω	50.53 Ω	0.052 Ω2

. The results are distributed as shown in the table below. The design values for R, C1, and C2, as well as the measured mean values, are within reasonable error ranges, with low variance, indicating excellent process stability.

Transmission line loss testing (Figure 15) shows losses below 0.5 dB within 50 GHz and below 1 dB within 67 GHz, meeting 100 G/200 G requirements.

We conducted the process development of the high-speed Si-based carrier, focusing on the research and development of high-density capacitors. A high-density capacitor with a capacitance density of 26.83 nF/mm² was achieved and successfully integrated onto the Si substrate. Additionally, a 50 Ω polycrystalline silicon resistor strip and AuSn solder were fabricated using polysilicon. By optimizing process parameters [16], the wafer yield was significantly improved. The final high-speed Si-based carrier is shown in the Figure 16 and Figure 17.

We used the silicon integrated carrier in combination with the EML chip and encapsulated it into a COC for optical output characteristics and high-frequency bandwidth testing. The test results showed that the COC exhibited normal optical output (Figure 18), with a −3 dB bandwidth exceeding 40 GHz (Figure 19), meeting the communication requirements for a single wavelength of 100 Gbps. This further validates the feasibility of the silicon integrated carrier in high-speed transmission.

Finally, we analyzed the characteristics of different transmission line widths, different coplanar waveguide gaps, and different dielectric constants of Si materials. The analysis results show that the dielectric constant of Si materials has little impact on transmission characteristics; the transmission line width has a significant impact, with a width of 0.01 mm exhibiting higher loss, while the loss remains around 1 dB within the range of 0.02–0.04 mm (Figure 20); the width of the waveguide gap has a minor impact, generally within 0.6 dB, with a loss within 0.1 dB for gaps of 0.01–0.02 mm, and the highest loss reaching 0.55 dB for a gap as small as 0.005 mm (Figure 21). This further validates that the currently selected transmission line parameters are within a reasonable range (Figure 22).

• Transmission line width: 0.01 mm~0.02 mm~0.03 mm~0.04 mm

Figure 20. Transmission characteristic curve.

Figure 20. Transmission characteristic curve.

2.

Coplanar waveguide gap: 0.005 mm~0.01 mm~0.015 mm~0.02 mm

Figure 21. Transmission characteristic curve.

Figure 21. Transmission characteristic curve.

3.

Dielectric constant of Si material: 11.0~11.9~13.0

Figure 22. Transmission characteristic curve.

Figure 22. Transmission characteristic curve.

4. Discussion and Analysis

• CPW Transmission Line Performance and High-Frequency Loss Mechanisms

This study achieved exceptional performance with a transmission loss of ≤1.2 dB within 50 GHz by optimizing the CPW transmission line structure and bonding pad layout, representing a 40% reduction compared to the typical loss of ≥2 dB for traditional AlN substrates. Experimental measurements confirmed that the Si-based integrated carrier exhibits a transmission loss < 1 dB up to 67 GHz, significantly enhancing high-frequency signal transmission efficiency. A return loss of ≤−12.41 dB demonstrates effective impedance matching.

2.

Breakthroughs in High-Density Capacitor Processes

A three-dimensional capacitor design using deep trench etching and ONO (SiO₂/Si₃N₄/SiO₂) composite dielectrics achieved a high capacitance density of 26.83 nF/mm², approaching the technical level of Murata (30 nF/mm²). The breakdown voltage was increased to 24 V, and the leakage current was reduced to <1 μA (as shown in Figure 23), significantly outperforming traditional discrete capacitors.

3.

Multi-Channel Crosstalk Suppression and Optical Module Integration Advantages

Through the combined optimization of absorbing materials and metal barriers, the inter-channel isolation improved from −6.6 dB to −29.54 dB, with the deterioration frequency shifting from 26.23 GHz to 29.52 GHz (see

Table 4. Isolation of dual-channel structure model.

No.	Modification	Isolation	Deterioration Frequency
1	Dual-channel model	−6.6 dB	26.23 GHz
2	Added metal barriers	−19.17 dB	26.67 GHz
3	Added absorbing material	−29.54 dB	29.52 GHz
4	Added bonding gold wires	−9.35 dB	27.5 GHz
5	Increased channel spacing	−14.72 dB	24.68 GHz

), far surpassing the isolation performance of traditional AlN substrates. Simulations indicate that the absorbing materials on the silicon-based carrier effectively suppress high-frequency electromagnetic field coupling, while the metal barriers reduce crosstalk by blocking near-field interference.

5. Conclusions and Discussion

This study addresses the high cost and process complexity of traditional AlN substrates by developing a high-speed silicon-based integrated carrier. It is suitable for the optical transmission link section of 400 G/800 G high-speed optical modules in data centers, providing a carrier with matched resistors and capacitors for high-speed EML. Through the optimization of the CPW transmission line structure, a measured transmission loss of <1 dB within 67 GHz was achieved, fulfilling high-frequency signal transmission requirements. The deep trench etching process yielded a capacitance density of 26.83 nF/mm² and a breakdown voltage of 24 V, reaching domestically leading levels. Absorbing materials optimized the isolation to −29.54 dB, making the carrier suitable for multi-channel high-speed systems and significantly enhancing high-frequency performance and integration density. Process optimizations for polycrystalline silicon resistors (error < 1%) and AuSn solder (push strength: 505 g) achieved a >95% yield rate, validating the reliability of the silicon-based carrier.