A 0.81–1.46 ppm/^∘C High-Order Segmented Curvature-Compensation Bandgap Reference with Dynamic Element Matching Offset Cancellation for a Battery Management System

Abstract

A precise high-order segmented curvature-compensation bandgap reference (BGR) with dynamic element matching (DEM) offset cancellation has been developed. The proposed segmented curvature-compensation scheme with a resistive trimming network is used to reduce the errors caused by the nonlinear dependence of the bipolar transistor base-emitter voltage ($V_{\mathit{BE}}$) on temperature. To decrease the std dev ($\sigma$) of the reference voltage ($V_{\mathit{REF}}$), DEM technology is applied in the core BGR to alleviate the current branch mismatch, as well as the current mirror mismatch in the error amplifier. The proposed BGR circuit is designed on a 0.18 $\mathsf{\mu }$m BCD process with an active area of $300\times 375$ $\mathsf{\mu }$m and 61.5 $\mathsf{\mu }$A@5 V current consumption in the bandgap core circuit. The post-simulation results show that the proposed BGR achieves a temperature coefficient (TC) of 0.81–1.46 ppm/°C from −40 °C to 125 °C and a 0.045% $\sigma$/$\mu$ variation on a 3.2768 V $V_{\mathit{REF}}$.

1. Introduction

High-performance battery management systems (BMSs) have become indispensable electronic devices in automotive electronics [1]. To accurately measure the state of charge of a battery over an operating temperature range, a precise reference voltage ($V_{\mathit{REF}}$) with low temperature drift is required [1,2]. For a BMS, a 3.28 V reference voltage with a temperature coefficient (TC) less than 5.5 ppm/°C over a −40 °C to 125 °C temperature range is required to detect a 3 mV battery voltage change, which is still a great challenge in CMOS and BCD processes [1,3]. Moreover, process variations and device mismatches are also the main sources of residual non-proportional-to-absolute-temperature (non-PTAT) errors in the reference voltage after trimming [4], which significantly impacts the achievable precision of the bandgap reference voltage.

To maintain high accuracy in a wide temperature range, higher-order compensation circuits are used to correct the nonlinear dependence of base-emitter voltage ($V_{\mathit{BE}}$) on temperature. The first-order temperature-compensated bipolar junction transistor (BJT)-based bandgap references (BGRs) are typically in the range of 20–100 ppm/°C [5,6,7,8], while the curvature or variation of $V_{\mathit{BE}}$ can be several mV over the temperature range from −40 °C to 125 °C [9]. BGR [1] utilizes the exponential characteristics of the base current and the resistance between the bases of BJT to perform the corrections. To achieve 4.6 ppm/°C TC over a wide temperature range of −40 °C to 130 °C, the curvature of subthreshold-operating MOSFETs is considered to further compensate for high-order temperature effects [1]. A curvature-compensated CMOS BGR circuit with a shared offset-cancellation method for internal amplifiers [10] adopts a multi-section curvature compensation method to alleviate the error from the nonlinear dependence of $V_{\mathit{BE}}$ on temperature. A sub-ranging TC compensation technique for a current reference is proposed [11], which enables second-order TC compensation in a wide temperature range without chip-by-chip trimming or an external reference. It is difficult to ensure the accuracy of the output voltage if the high-order temperature compensation is realized without resistors [12]; therefore, resistive trimming networks are still common. However, the temperature coefficients (TCs) in most of the literature are in the single-digit ppm/°C range since the nonlinear dependence of $V_{\mathit{BE}}$ on temperature is not completely canceled [13]. Thus, achieving a sub-1 ppm/°C TC is still a great challenge in a standard CMOS process.

The primary contributors to the overall offset come from the non-PTAT opamp offset and core device mismatch, as these errors are magnified by the closed-loop gain in a BGR and affect the output. A single-trim BGR with trimming, $\beta$-compensation, and curvature correction can further reduce non-PTAT errors resulting from mismatches with dynamic element matching (DEM) techniques [2]. An auto-zeroing circuit using a shared offset-cancellation method for internal amplifiers [10] can reduce the output inaccuracy within ±4.6 $\mathsf{\mu }$V with a relatively small die area. With the use of chopping to cancel the opamp offset and curvature correction to reduce the temperature dependency of the $V_{\mathit{BE}}$, a CMOS bandgap reference achieves a 3$\sigma$ inaccuracy of ±0.15% from −40 °C to 125 °C [9]. In order to reduce the $\Delta V_{\mathit{BE}}$ mismatch, a DEM technique is introduced in the $V_{\mathit{BE}}$ generation circuit [14]. The feedback coefficient enhancement technique is used to suppress the low-frequency noise and offset voltage [15].

In this article, a high-order segmented curvature compensation bandgap reference with DEM offset-cancellation is presented. In order to reduce the errors caused by the nonlinear dependence of a bipolar transistor $V_{\mathit{BE}}$ on temperature, a segmented curvature compensation scheme with a resistive trimming network is proposed. DEM technology has been applied in the core BGR to alleviate the current branch mismatch, as well as the current mirror mismatch in the error amplifier. The principles of curvature compensation and trimming and the current mismatch are analyzed. The effectiveness of the proposed curvature compensation scheme in reducing TC and DEM technology in output offset cancellation is verified through simulation in a 0.18 $\mathsf{\mu }$m BCD process, achieving a maximum TC of 1.46 ppm/°C and a maximum $\sigma$/$\mu$ variation of 0.049% within −40 °C to 125 °C.

The rest of this paper is organized as follows. The proposed high-order segmented curvature-compensation scheme with resistive trimming network and DEM offset cancellation are discussed in Section 2. In addition, a complete circuit architecture for the proposed BGR design is demonstrated in detail. The simulation results are presented in Section 3 and compared with the state of the art. Finally, the conclusion is drawn in Section 4.

2. Proposed Design and Architecture

2.1. Proposed High-Order Segmented Curvature Compensation

Figure 1 shows the mathematical signal processing diagram illustrating how the final $V_{\mathit{REF}}$ is obtained with correction currents in the proposed high-order segmented curvature-compensation method. The trend of a first-order compensated $V_{\mathit{REF}}$ is illustrated in Figure 1a. To improve the TC over a wide temperature range, the $V_{\mathit{REF}}$ compensation is divided into three temperature segments, defined by the $T_1$ and $T_2$ points, as shown in Figure 1, with each segment being compensated by distinct correction currents. In the high-temperature segment, the $I_{\mathit{PTAT}}^2$ is introduced to perform the correction above the $T_2$ temperature point. The temperature drift curvature can be compensated from Figure 1a–c. In the low-temperature and middle-temperature segments, the $I_{\mathit{curvel}}$ and $I_{\mathit{curvem}}$ are introduced to perform the exponential curvature correction under $T_2$ temperature point. So $I_{\mathit{curvel}}$ mainly provides correction under a $T_1$ temperature point, while $I_{\mathit{curvem}}$ provides fine-tuning correction in the [$T_1$, $T_2$] segment. This leads to the curvature being compensated from Figure 1c–e and finally to Figure 1g. These high-order segmented curvature-correction currents can be converted into voltage through the resistors and further fine-tuned using the proposed trimming network.

Bandgap cores typically use BJT devices to derive the bandgap voltage of silicon [1,2,3,4]. The emitter-base voltage of BJT is commonly used in precision voltage references due to its robust operation over the process [2]. The topology of the BGR with high-order segmented curvature compensation is presented in Figure 2. The bandgap core is based on the high-order curvature-compensated BGR [1], as shown by the black line in Figure 2. However, the main difference is in the first-order compensation, $I_{\mathit{PTAT}}^2$ correction, and trimming modules. Compared with the BGR [1], M₁–M₄ is introduced to generate a PTAT correction current. Q₃–Q₆ and R₂₀ are introduced to generate the $I_{\mathit{PTAT}}^2$ correction current. Furthermore, R_B is divided into R₀ to R₁₅ to implement the proposed trimming scheme.

The proposed BGR includes the bandgap core, base current compensation module, first-order and higher-order curvature compensation modules, trimming module, and offset-cancellation module. The core BGR is implemented with a three-stage cascade configuration. The presence of the inherent output stage circuit enables the BGR to drive the load. Resistors R_C and PMOS capacitors M_C are added for loop stability. The base current compensation method [1] is used to reduce the impact of the BJT base input resistance. The base correction current $I_b$ is generated by the biased base current of the BJT Q₇. Compared with the BGR [1], the resistor between bases of BJT is removed and adjusted using M₆–M₉ instead to control the base current magnitude. Generally, the bandgap core voltage $V_{BG}$ is given by [1]

$$\begin{array}{cc}\hfill V_{BG}& =V_{B{E}_1}+2R_B{I}_{PTAT}=V_{B{E}_1}+2{\displaystyle \frac{R_B}{R_A}}·\Delta V_{BE}\hfill \\ \hfill & =V_{B{E}_1}+2{\displaystyle \frac{R_B}{R_A}}·V_{T}ln\left(N\right)=V_{B{E}_1}+2{\displaystyle \frac{R_B}{R_A}}·{\displaystyle \frac{kT}{q}}ln\left(N\right)\hfill \end{array}$$

(1)

where $I_{\mathit{PTAT}}$ is the current flowing through resistor R_A, $V_{\mathit{BE}}$ is the BJT’s base-emitter voltage, $\Delta V_{\mathit{BE}}=V_{T}ln\left(N\right)$ is the base-emitter voltage difference between Q₁ and Q₂, and N is their emitter area ratio. $V_T=kT/q$ is the thermoelectric coefficient, where k is the Boltzmann constant, T is the absolute temperature, and q is the elementary charge. Based on the above equation, it can be seen that selecting appropriate values for N and $R_A$ can draw the $I_{\mathit{PTAT}}$ current. In this work, the area ratio of Q₁ and Q₂ is set to 8. To enhance the matching of Q₁ and Q₂, the layout places Q₁ at the center and arranges eight equal-sized unit devices for Q₂ in a common centroid configuration with interspersed dummy devices. A relatively temperature-independent reference voltage can be generated by selecting an appropriate $R_B$. However, the $V_{\mathit{BE}}$ of a BJT is not a purely linear function of temperature.

The relationship between $V_{\mathit{BE}}$ and temperature can be expressed as follows [1,2]:

$$V_{BE}\left(T\right)=V_{G0}\left(T_r\right)-\left[V_{G0}\left(T_r\right)-V_{BE}\left(T_r\right)\right]{\displaystyle \frac{T}{T_r}}-(\eta -\xi )V_{T}ln\left({\displaystyle \frac{T}{T_r}}\right)$$

(2)

where $V_{G0}\left(T_r\right)$ is the extrapolated bandgap voltage at a reference temperature $T_r$, $\eta$ is a process-related constant, and $\xi$ is the order of the collector current temperature dependence. $\left[V_{G0}\left(T_r\right)-V_{BE}\left(T_r\right)\right]T/T_r$ is the first-order linear temperature dependence term of $V_{\mathit{BE}}$. And based on Equation (1), selecting the appropriate $R_B$ and $I_{\mathit{PTAT}}$ can eliminate it. $(\eta -\xi )V_T\mathit{ln}\left(T/T_r\right)$ is the high-order nonlinear temperature-dependent term of $V_{\mathit{BE}}$, which requires high-order curvature compensation.

In Figure 2, $I_{\mathit{coarse}}$ is the first-order coarse trimming correction current. $I_{\mathit{fine}}$ is the 1st-order fine-trimming correction current. $I_{\mathit{PTAT}}^2$, $I_{\mathit{curvel}}$, and $I_{\mathit{curvem}}$ are high-order curvature correction currents in the high-, low-, and medium-temperature ranges, respectively. In order to generate the $I_{\mathit{PTAT}}^2$ correction module, it is composed of Q₃–Q₆, R₂₀, and the relationship of $V_{\mathit{BE}}$ between Q₃–Q₆ can be expressed as

$$V_{BE5}+V_{BE6}=V_{BE3}+V_{BE4}$$

(3)

So the current flowing through BJT Q₃ is given by

$$I_{C3}={\displaystyle \frac{I_{C5}{I}_{C6}}{I_{C4}}}={\displaystyle \frac{I_{\mathit{PTAT}}^2}{I_{C4}}}=I_{\mathit{PTAT}}^2{\displaystyle \frac{R_{20}}{V_{BE3}}}$$

(4)

The first-order coarse correction coefficient is ${\alpha }_1=R_{eq,coarse}/R_B$, where $R_{eq,coarse}$ represents the equivalent resistance from the $I_{\mathit{coarse}}$ node to ground. Similarly, the first-order fine correction coefficient is ${\alpha }_2=R_{eq,fine}/R_B$, where $R_{eq,fine}$ represents the equivalent resistance from the $I_{\mathit{fine}}$ node to the ground. And the $I_{\mathit{PTAT}}^2$ correction coefficient is ${\alpha }_3=R_{eq,I_{\mathit{PTAT}}^2}/R_B$, where $R_{eq,I_{\mathit{PTAT}}^2}$ represents the equivalent resistance from the $I_{\mathit{PTAT}}^2$ node to the ground. Regardless of $I_{\mathit{curvel}}$ and $I_{\mathit{curvem}}$, according to Figure 2 and based on Equation (1), the expression for $V_{\mathit{BG}}$ can be rewritten as

$$V_{BG}\left(T\right)=V_{BE}\left(T\right)+I_{PTAT}{R}_B\left(2+{\alpha }_1+{\displaystyle \frac{{\alpha }_2}{2}}\right)+I_{PTAT}^2{\displaystyle \frac{R_{20}}{V_{BE3}}}{R}_B{\displaystyle \frac{{\alpha }_3}{2}}$$

(5)

Based on Equations (2) and (5), there is

$$\begin{array}{cc}\hfill V_{BG}\left(T\right)=& V_{G0}\left(T_r\right)-\left[{\displaystyle \frac{V_{G0}\left(T_r\right)-V_{BE}\left(T_r\right)}{T_r}}-{\displaystyle \frac{k{R}_B}{q{R}_A}}\left(2+{\alpha }_1+{\displaystyle \frac{{\alpha }_2}{2}}\right)ln\left(N\right)\right]T\hfill \\ \hfill & -(\eta -\xi )V_{T}ln\left({\displaystyle \frac{T}{T_r}}\right)+{\left[{\displaystyle \frac{k{R}_B}{q{R}_A}}ln\left(N\right)\right]}^2{\displaystyle \frac{R_{20}}{V_{BE3}}}{R}_B{\displaystyle \frac{{\alpha }_3}{2}}{T}^2\hfill \end{array}$$

(6)

Expanding $\mathit{ln}\left(T/T_r\right)$ using a Taylor series expression, there is

$$\begin{array}{cc}\hfill V_{BG}\left(T\right)& =V_{G0}\left(T_r\right)-\left[{\displaystyle \frac{V_{G0}\left(T_r\right)-V_{BE}\left(T_r\right)}{T_r}}-{\displaystyle \frac{k{R}_B}{q{R}_A}}\left(2+{\alpha }_1+{\displaystyle \frac{{\alpha }_2}{2}}\right)ln\left(N\right)-{\displaystyle \frac{11k}{6q}}(\eta -\xi )\right]T\hfill \\ \hfill & +\left\{{\left[{\displaystyle \frac{k{R}_B}{q{R}_A}}ln\left(N\right)\right]}^2{\displaystyle \frac{R_{20}}{V_{BE3}}}{R}_B{\displaystyle \frac{{\alpha }_3}{2}}-{\displaystyle \frac{3k}{q}}{\displaystyle \frac{1}{T_r}}(\eta -\xi )\right\}{T}^2+{\displaystyle \frac{3k}{2q}}{\displaystyle \frac{1}{T_r^2}}(\eta -\xi )T^3-\dots \hfill \end{array}$$

(7)

Based on the above equation, it can be seen that if the coefficient term of T is zero, $({\alpha }_1+{\alpha }_2/2)R_B$ can be determined. If the coefficient term of $T^2$ is zero, ${\alpha }_3{R}_B$ can be determined. In practical circuit design, further fine-tuning is required to achieve optimal TC.

Although the compensation is effective, the output reference voltage still exhibits a downward parabolic curvature with temperature changes. To improve the TC of $V_{\mathit{REF}}$ in the low to medium temperature range, the exponential curvature compensation method [1] is also implemented in the design, as shown in Figure 2. Compared with the BGR [1], the $I_{\mathit{CO}}=I_{\mathit{curvel}}+I_{\mathit{curvem}}$ in [1] is divided into two current paths, $I_{\mathit{curvel}}$ and $I_{\mathit{curvem}}$, which are used for temperature drift correction under the $T_2$ temperature point. The $I_{\mathit{curvel}}$ correction coefficient is ${\alpha }_4=R_{eq,\mathit{curvel}}/R_B$, where $R_{eq,\mathit{curvel}}$ represents the equivalent resistance from the $I_{\mathit{curvel}}$ node to the ground. Similarly, the $I_{\mathit{curvem}}$ correction coefficient is ${\alpha }_5=R_{eq,\mathit{curvem}}/R_B$, where $R_{eq,\mathit{curvem}}$ represents the equivalent resistance from the $I_{\mathit{curvem}}$ node to the ground. The final expression for the $V_{\mathit{BG}}$ can then be derived as

$$V_{B{G}_{trim}}\left(T\right)=V_{BG}\left(T\right)+I_{\mathit{curvel}}{R}_B{\alpha }_4+I_{\mathit{curvem}}{R}_B{\alpha }_5$$

(8)

From Equation (8), an appropriate resistance node in R_B can be chosen to generate the suitable ${\alpha }_4$ or ${\alpha }_5$. The proposed compensation scheme eliminates the need for fine-tuning the values of $V_{\mathit{M}}$ and $V_{\mathit{L}}$ to construct an $I_{\mathit{CO}}$ that is complementary and opposite in curvature to the $V_{\mathit{REF}}$ [1], making temperature drift correction more accurate and easier to control.

2.2. Trimming Scheme Implementation

Figure 3 shows the implementation of the proposed trimming scheme. The resistor R_B is initially divided into R₀ and a four-bit trimming network, consisting of 15 equal resistors from R₁ to R₁₅. By dividing resistors R₁₄ and R₁₅ into four equal segments, an additional three-bit trimming network is incorporated, resulting in a total seven-bit resistor network. By adjusting the trimming codes TC<6:0>, the first-order correction currents of $I_{\mathit{coarse}}$ and $I_{\mathit{fine}}$ can be injected into various resistor nodes N<21:0> to calibrate the first-order linear temperature coefficients. For curvature compensation trimming, a similar resistor network is employed to create two two-bit trimming networks. By adjusting the trimming codes curvel<1:0> and curvem<1:0>, the high-order correction currents of $I_{\mathit{curvel}}$ and $I_{\mathit{curvem}}$ can be injected into resistor nodes N<3:0> and N<12:9>, respectively, to calibrate the high-order temperature coefficients. All the trimming codes, including TC<6:0>, curvel<1:0> and curvem<1:0>, are generated by two-point temperature measurement. The more measurement points, the better the temperature coefficient that can be achieved.

The resistor divisions are determined based on the worst-case temperature drift and the required trimming range. Running TC simulations at various corners shows that the worst-case temperature drift before trimming occurs at the ss and ff corners. Specifically, the ss corner shows a temperature drift of −20.9 mV, while the ff corner shows a temperature drift of +38.7 mV. Therefore, the trimming range needs to cover at least $38.7+20.9=59.6\mathrm{mV}$. So, the trimming range is set from −65 mV to +65 mV. Given a first-order correction current $I_{\mathit{coarse}}$ of 8 $\mathsf{\mu }$A and the four-bit trimming network, the resistance value for R₁–R₁₅ is ${\displaystyle \frac{130\mathrm{mV}}{15\times 8\mathsf{\mu }\mathrm{A}}}=1.08\mathrm{k}\mathsf{\Omega }$. Furthermore, R₁₄ and R₁₅ are divided into four equal parts for fine-trimming correction: ${\displaystyle \frac{1.08\mathrm{k}\mathsf{\Omega }}{4}}=271\mathsf{\Omega }$. Given a $I_{\mathit{fine}}$ of 4 $\mathsf{\mu }$A, this results in a first-order trimming resolution of ${\displaystyle \frac{1}{2}}\times 8\mathsf{\mu }\mathrm{A}\times 271\mathsf{\Omega }=1.08$ mV.

2.3. DEM Offset Cancellation

The device mismatch of the bandgap core current branch in Figure 2 significantly impacts the output voltage accuracy of the BGR. To analyze this mathematically, assuming A is an ideal operational amplifier, then $V_{\mathit{REF}}$ can be written as

$$\begin{array}{cc}\hfill V_{REF}& =\left(1+{\displaystyle \frac{R_{21}}{R_{22}}}\right)\left(V_{BE1}+2{\displaystyle \frac{R_B}{R_A}}·V_{T}ln{\displaystyle \frac{I_{C1}}{I_{C2}/N}}\right)\hfill \\ \hfill & =\left(1+{\displaystyle \frac{R_{21}}{R_{22}}}\right)\left[V_{BE1}+2{\displaystyle \frac{R_B}{R_A}}{V}_{T}lnN-2{\displaystyle \frac{R_B}{R_A}}{V}_{T}ln\left(1+{\displaystyle \frac{\Delta I}{I}}\right)\right]\hfill \\ \hfill & \approx \left(1+{\displaystyle \frac{R_{21}}{R_{22}}}\right)\left[V_{BE1}+2{\displaystyle \frac{R_B}{R_A}}{V}_{T}lnN-2{\displaystyle \frac{R_B}{R_A}}{V}_T{\displaystyle \frac{\Delta I}{I}}\right]\hfill \end{array}$$

(9)

where I is the current flowing through M₁ and M₂, and $\Delta I$ represents the current mismatch between these two branches. The offset of $V_{\mathit{REF}}$ can be expressed as

$$\begin{array}{cc}\hfill V_{OS,\mathit{REF}}& =2\left(1+{\displaystyle \frac{R_{21}}{R_{22}}}\right){\displaystyle \frac{R_B}{R_A}}{V}_T{\displaystyle \frac{\Delta I}{I}}\hfill \end{array}$$

(10)

According to Equation (10), it can be calculated that a 200 nA mismatch current between the bandgap core current branch results in approximately 15 mV −$V_{\mathit{OS},\mathit{REF}}$. Since the offset drift caused by mismatch between the bandgap core current branch is typically non-PTAT, it is difficult to reduce it with a PTAT trim. Increasing the value of current I can reduce the mismatch between the bandgap core current branch, but it will increase the power consumption relatively more. Therefore, the offset needs to be removed by offset-cancellation techniques [16]. In this work, a dynamic element matching (DEM) technology is employed to reduce non-PTAT errors related to device mismatches, as shown in Figure 4a.

In the timing control, $phase1$ and $phase2$ are two non-overlapping clock phases used to perform the DEM operation. As a result of the DEM operation, the $V_{\mathit{REF}}$ changes with the state of the control signals. In addition, the switches in DEM1 are located in the current branch of the bandgap core. Large MOSFET (50 $\mathsf{\mu }$m/0.5 $\mathsf{\mu }$m) are used for the resistor switches to minimize their on-resistance influence [13]. Within one conversion cycle, the average currents of M₁ and M₂ are maintained at a 1:1 ratio. The intermediate error amplifier in Figure 4b utilizes a cascode structure to achieve high loop gain and high common-mode rejection ratio (CMRR). Furthermore, to reduce the current mirror mismatch in the error amplifier, a DEM2 module, controlled by the same clock, is employed in this amplifier.

The DEM frequency is 1 kHz. Transient simulation shows that due to the parasitic coupling of high-frequency switching, there is a ripple of about 200 $\mathsf{\mu }$V in the output of the BGR, which will be superimposed with the offset on the BGR output. As mentioned in [11], the ripple from two-phase DEM can be removed using a switched-capacitor notch filter, or a discrete-time or continuous-time ripple-reduction loop (RRL), which is not included in this work. Transient simulation shows a static power consumption of 143.68 $\mathsf{\mu }$A without DEM, which increases to 143.73 $\mathsf{\mu }$A with the 1 kHz DEM clock, indicating that the impact of switching devices on power consumption is negligible.

3. Simulation Results

The BGR is designed on a 0.18 $\mathsf{\mu }$m BCD process. The layout is shown in Figure 5, with an active layout area of $300\times 375$ $\mathsf{\mu }$m. The active layout area of DEM offset cancellation is $107\times 37.3$ $\mathsf{\mu }$m, while the layout area of trimming module is $150\times 69.5$ $\mathsf{\mu }$m. Components with a deep n-well layer are chosen, since this can efficiently separate the p-substrate for different circuits and then block the noise from other subsequent circuits [17]. The designed BGR operates with a static current consumption of 144 $\mathsf{\mu }$A, of which 67 $\mathsf{\mu }$A is allocated to the output driving stage. Thus, the core of the proposed BGR only consumes 61.5 $\mathsf{\mu }$A. Unless otherwise specified, all post simulations were conducted at a typical temperature of 27 °C and a power supply voltage of 5.0 V.

Figure 6a shows the simulated $V_{\mathit{REF}}$ variation at different corners before trimming from −40 °C to 125 °C, with an output voltage of 3.2768 V at 27 °C. Figure 6b shows the simulated $V_{\mathit{REF}}$ variation at different corners after first-order trimming. The results demonstrate that the proposed curvature compensation scheme achieves a TC range of 0.81 to 3.48 ppm/°C and is robust against process variations. Figure 6c shows the simulated $V_{\mathit{REF}}$ variation for the ff corner after first-order trimming and curvature trimming. Figure 6d shows the simulated $V_{\mathit{REF}}$ variation across different curvel<1:0> trimming codes for $I_{\mathit{curvel}}$ curvature correction.

Table 1. TC simulation results before/after 1st-order trimming and curvature trimming at different corners.

Corner	Before Trimming (ppm/°C)	After Trimming (ppm/°C)
tt	0.81	0.81
ss	31.05	1.46
ff	40.72	1.06
sf	0.9	0.9
fs	2.81	1.19

lists the TC simulation results of the BGR before/after first-order trimming and curvature trimming at different corners. All the data points are measured after post-simulation. It can be concluded that the range of $V_{\mathit{REF}}$ variation after trimming is between 0.44 mV and 0.79 mV, corresponding to a TC of 0.81–1.46 ppm/°C. We also study the BGR under extreme conditions (e.g., −50 °C or 130 °C) the circuit operates normally and the TC is 1.41 ppm/°C over a wide temperature range of −50 °C to 130 °C.

The first-order compensated $V_{\mathit{REF}}$ versus the $I_{\mathit{PTAT}}^2$ correction voltage at the tt corner and the $I_{\mathit{PTAT}}^2$-compensated $V_{\mathit{REF}}$ versus $I_{\mathit{curvel}}$ correction voltage are plotted as simulated functions of temperature in Figure 7. The correction voltages generated by the $I_{\mathit{PTAT}}^2$ and $I_{\mathit{curvel}}$ are $I_{\mathit{PTAT}}^2\times R_{eq,I_{\mathit{PTAT}}^2}$ and $I_{\mathit{curvel}}\times R_{eq,\mathit{curvel}}$ according to Equation (5). The simulation results show the intersection points of the correction voltage curve and the pre-correction $V_{\mathit{REF}}$ curve around −4 °C and 82 °C at tt corner. The temperature points $T_1$ and $T_2$ are determined by simulation or measurement optimization. First, we perform $I_{\mathit{PTAT}}^2$ correction, which reduces the voltage variation of $V_{\mathit{REF}}$ from 6.6 mV to 1.12 mV and the TC from 46.8 ppm/°C to 7.9 ppm/°C over the temperature range from $T_2$ to 125 °C. Second, the voltage variation of $V_{\mathit{REF}}$ is further reduced from 4.85 mV to 0.81 mV and the TC is improved from 41.1 ppm/°C to 6.9 ppm/°C over the temperature range from −40 °C to $T_1$ by applying $I_{\mathit{curvel}}$ correction. Finally, after applying $I_{\mathit{curvem}}$ correction, $V_{\mathit{REF}}$ achieves a TC of 0.81 ppm/°C across the entire temperature range from −40 °C to 125 °C. These improvements indicate that $I_{\mathit{PTAT}}^2$, $I_{\mathit{curvel}}$ and $I_{\mathit{curvem}}$ primarily contribute to the curvature compensation within the ranges of [$T_2$, 125 °C], [−40 °C, $T_1$], and [$T_1$, $T_2$], respectively. During this correction process, the trimming codes for this batch of the BGR circuit can also be determined.

Figure 8 shows the comparison of Monte Carlo simulation results of 500 sampling points with/without the proposed DEM offset cancellation. It can be seen that the mean ($\mu$) of $V_{\mathit{REF}}$ with DEM offset cancellation is around 3.27683 V, remaining almost unchanged. The std dev ($\sigma$) of $V_{\mathit{REF}}$ decreased from 8.33 mV to 1.46 mV, and the $\sigma$/$\mu$ variation in $V_{\mathit{REF}}$ decreased from 0.25% to 0.045%, an improvement of 82%.

Figure 9 shows the simulated $V_{\mathit{REF}}$ vs. $V_{\mathit{DDA}}$ at different process corners. The simulation results show that when the power supply voltage increases from 4.2 to 6.0 V, the $V_{\mathit{REF}}$ changes by 0.38 mV at the tt corner, corresponding to a line regulation of 0.022%/V. Furthermore, at the worst-case ss corner, the $V_{\mathit{REF}}$ changes by 0.74 mV, corresponding to a line regulation of 0.041%/V. When the load current increases from 0 mA to 1.5 mA, the reference voltage changes by 33.1 $\mathsf{\mu }$V at the tt corner, corresponding to a load regulation of 0.022 mV/mA, while at the worst-case ss corner, the $V_{\mathit{REF}}$ changes by 35.8 $\mathsf{\mu }$V, corresponding to a load regulation of 0.024 mV/mA. The proposed BGR exhibits low and consistent sensitivities at all process corners.

Figure 10 shows the simulated power supply rejection ratio (PSRR) of the proposed BGR with/without DEM offset cancellation over the frequency range from 1 Hz to 100 kHz. At 10 Hz, the PSRR is approximately −78 dB, while at 100 kHz, the PSRR is approximately −54 dB. The PSRR with and without DEM offset-cancellation shows a negligible difference.

Figure 11 shows the current consumption and area of the proposed BGR circuit components. The DEM offset-cancellation module occupies 0.03% of the total current consumption and 4% of the layout area. The curvature-compensation modules consume 10.76% of the total current consumption and 3% of the layout area. Similar to [14,18], the current consumption in this design is 144 $\mathsf{\mu }$A, including the 67 $\mathsf{\mu }$A current consumption of the output stage, which can directly drive a load current ranging from 0 to 1.5 mA. The bandgap core’s current consumption is 61.5 $\mathsf{\mu }$A, which remains within a reasonable range when compared to the other bandgap reference circuits listed in

Table 2. Performance comparison with other state-of-the-art works.

Specification	This Work *	[1]	[2]	[9]	[10]	[14]	[18]
Year	2024	2019	2021	2011	2021	2017	2022
Application	BMS	BMIC	BMS	-	-	BMS	-
Technology	0.18 $\mathsf{\mu }$m BCD	0.18 $\mathsf{\mu }$m	0.18 $\mathsf{\mu }$m	0.16 $\mathsf{\mu }$m	0.13 $\mathsf{\mu }$m	0.8 $\mathsf{\mu }$m BiCMOS	0.18 $\mathsf{\mu }$m
Supply Voltage (V)	5 ± 10%	3.5–5	1.8 ± 10%	1.8 ± 10%	3.3	5.2	2.7–3.3
Reference Voltage (V)	3.2768	3.11	1.1419	1.0875	1.16	3.657	1.2
Reference Type	DC	DC	Switched Cap.	DC	DC	Switched Cap.	DC
Temp. Range (°C)	−40~125	−40~130	−40~125	−40~125	−40~150	−40~110	−10~110
Trimmed TC (ppm/°C)	0.81–1.46	4.6–6.3	3.3–5.5	5–12	5.78–13.5	±3 (3$\sigma$)	5–15
Volt. $\sigma$/$\mu$ (%)	0.045@Room Temp. 0.049@Entire Temp. Range	-	+0.02, −0.12 (3$\sigma$)	±0.15 (3$\sigma$)	0.54	-	-
Line Regulation (%/V)	0.022	0.031	-	-	0.03	-	0.005
Load Regulation (mV/mA)	0.022	-	-	-	-	-	-
Curvature Correction	Yes	Yes	Yes	Yes	Yes	No	Yes
Trimming	Yes	Yes	Yes	Yes	No	Yes	No
Output Stage	Yes	Yes	No	No	No	Yes	Yes
Current Consumption ($\mathsf{\mu }$A)	144	108	17	55	120	750	150
PSRR (dB)	−78@10 HZ	−92*@100 HZ	−76@DC	−74@DC	−82@10 Hz	−127@DC	−80@DC
Area (mm2)	0.1125	0.2225	0.38	0.12	0.08	0.28	0.448

* Post-Simulation results.

. In the output driving stage, methods such as using shared feedback resistors [19] can be explored to enhance the current driving capability while minimizing the overall power consumption.

Table 2 compares the proposed BGR performance with other state-of-the-art works. For BGRs without offset cancellation, such as the design [1], this work can achieve a much smaller $\sigma$/$\mu$ variation. Compared with the design without curvature correction [14], this work achieves a much smaller TC and $\sigma$/$\mu$ variation. Even for those works with curvature compensation [2,9,10,18], this work exhibits the lowest TC, making it suitable for high-precision BMS applications. This demonstrates the effectiveness of the proposed segmented curvature-compensation scheme with the DEM offset cancellation. The design in [1] performs well in terms of temperature drift. However, controlling the correction current index trajectory through $V_M$ and $V_L$ values is challenging. In contrast, the proposed trimming scheme for this BGR circuit makes temperature drift correction more accurate and easier to control. Additionally, the proposed BGR utilizes DEM technology to alleviate the current branch mismatch, as well as the current mirror mismatch in the error amplifier, achieving $\sigma$/$\mu$ values similar to those in [2].

4. Conclusions

A high-order segmented curvature-compensation BGR with DEM offset cancellation is designed on a 0.18 $\mathsf{\mu }$m BCD process. The active layout area is $300\times 375$ $\mathsf{\mu }$m, of which the DEM offset cancellation and trimming module occupy $107\times 37.3$ $\mathsf{\mu }$m and $150\times 69.5$ $\mathsf{\mu }$m, respectively. The proposed segmented curvature compensation scheme with a resistive trimming network can improve the TC performance to 0.81–1.46 ppm/°C over −40 °C to 125 °C. The DEM offset cancellation can improve the $\sigma$/$\mu$ variation in $V_{\mathit{REF}}$ by 82%, decreasing from 0.25% to 0.045%. The line regulation is 0.022%/V from 4.2 V to 6 V, while the load regulation is 0.022 mV/mA from 0 mA to 1.5 mA. The PSRR at 10 Hz frequency is −78 dB. The proposed BGR is highly suitable for integrated high-precision battery monitoring and power supply systems.