Image Classification in Memristor-Based Neural Networks: A Comparative Study of Software and Hardware Models Using RRAM Crossbars

Abstract

Vector–matrix multiplication (VMM), which dominates the computational workload in neural networks, accounts for over 99% of all operations, particularly in Convolutional Neural Networks (CNNs). These operations, consisting of multiply-and-accumulate (MAC) functions, are straightforward but demand massive parallelism, often involving billions of operations per layer. This computational demand negatively affects processing time, energy consumption, and memory bandwidth due to frequent external memory access. To efficiently address these challenges, this paper investigates the implementation of a full neural network for image classification, using TensorFlow as a software baseline, and compares it with a hardware counterpart mapped onto resistive RAM-based crossbar arrays, a practical implementation of the memristor concept. By leveraging the inherent ability of RRAM crossbars to perform VMMs in a single step, we demonstrate how RRAM-based neural networks can achieve efficient in-memory analog computing. To ensure realistic and practical results, the hardware implemented utilizes RRAM memory cells characterized through silicon measurements. Furthermore, the design exclusively considers positive weights and biases to minimize the area overhead, resulting in a lightweight hardware solution. This approach achieves an energy consumption of 190 fJ/MAC operation for the crossbar array, highlighting its efficiency in power-constrained applications despite a drop in the prediction confidence of 27.5% compared to the software approach.

1. Introduction

The traditional von Neumann (VN) computing architecture is reaching critical limitations, particularly regarding energy efficiency and latency [1]. This is particularly true when dealing with the vast amount of data generated by IoT devices, self-driving cars, cloud computing, etc. [2]. This situation, known as the “memory wall”, refers to the growing gap between the speed of a computer’s processing units and the slower access speed of memory, resulting in a critical performance bottleneck [3]. This limitation of modern computing architectures encourages the investigation of different processing paradigms, which are categorized as non-von Neumann (non-VN).

Over the last few years, there has been a lot of activity across research groups proposing efficient hybrid “CMOS-nanodevice” computing hardware architectures such as Artificial Neural Networks (ANNs) [4]. ANNs have demonstrated impressive performances in recognition tasks where classical VN hardware architectures have difficulties classifying or organizing data, a task that the human brain seems to accomplish efficiently. The architecture of ANNs is inspired by biological neural networks. ANNs consist of numerous units that are organized in a specific configuration to facilitate communication among them. These units are commonly known as nodes or neurons. Neurons utilize connection pathways known as synapses to communicate with each other, with each synapse assigned a specific weight that influences the strength of its signal transmission. These weights can either amplify or inhibit the signals transmitted across the network. Consequently, an ANN can be seen as a complex adaptive system, capable of modifying its internal parameters [5].

Emerging Back End Of Line (BEOL) resistive memory devices such as RRAMs [6,7] are considered to be the optimal candidates to emulate synaptic behavior at the nanometer scale, as they offer the ability to modulate their conductance in addition to being easily integrated with CMOS-based neuron circuits [8,9]. Among the different RRAM technologies available, oxide-based RAMs (OxRAMs) have proven to be very effective in implementing some aspects of synaptic plasticity [10,11]. Vector–matrix multiplication (VMM) in the context of RRAM-based ANNs involves performing calculations using the different conductance states of the RRAM cells [12]. In their crossbar architecture, input vectors are represented as voltage signals applied to the rows of the crossbar, while the weight matrix is stored as conductance values in the RRAM cells. When voltages are applied to the rows, the resulting currents through each cell are proportional to the product of the input voltage and the cell’s conductance, enabling the simultaneous computation of weighted sums across multiple columns of the crossbar array. In this context, this work evaluates the ability of a crossbar RRAM array to perform VMM as part of an image processing application. The main contributions of the proposed study are as follows:

• The conductance modulation capability of actual RRAM cells is evaluated at the test chip level through electrical characterization.
• At the software level, an ANN model is defined and trained for image classification, and its model parameters (weights and biases) are generated.
• At the hardware level, the ANN model parameters are mapped to a physical RRAM crossbar array, taking into account the RRAM cell characteristics extracted from silicon measurements.
• The RRAM crossbar array is simulated to demonstrate its ability to perform vector-matrix–multiplication (VMM) directly in the analog domain.

The remainder of this paper is organized as follows: Section 2 details the specifications of the fabricated RRAM cells and evaluates the conductance modulation capabilities of the selected RRAM technology. Section 3 presents the ANN weight mapping methodology used, focusing on a two-layer neural network designed for image classification. Section 4 describes the hardware-level implementation of the neural network using RRAM technology and evaluates its performance. Section 5 discusses the obtained results, and, finally, Section 6 concludes this paper.

2. Background

2.1. Specifications of the Manufactured RRAM Cells

RRAM devices typically operate based on the reversible change in resistance caused by the formation and rupture of conductive filaments (CFs) [13]. From a physical standpoint, when a voltage is applied across the cell (i.e., between the top and bottom electrodes), depending on the voltage polarity, one or more CFs made out of oxygen vacancies are either formed or ruptured. Once CFs are formed inside the metal oxide, bridging the top and bottom electrodes and leading to a low-resistance state (LRS), current can flow through the CFs. Subsequent resistance changes are achieved by rupturing the filaments. Applying a voltage with reversed polarity causes the filaments to break, leading to a high-resistance state (HRS). Figure 1a presents the considered 1T1R RRAM device, where one transistor (W = 0.8 μm and L = 0.5 μm) is connected in series with one resistive element (RRAM). The resistive element, shown in Figure 1b, is incorporated in the Back End Of Line (BEOL) of a 130 nm technology, between metal layers [14]. The stack is deposited using Physical Vapor Deposition (PVD), where a 10 nm Hafnium dioxide (HfO₂) layer is placed on the top of a TiN bottom electrode (BE). A Ti/TiN bilayer stack is then deposited as a top electrode (TE), forming a capacitor-like structure. Figure 1c presents a classical 1T1R I-V hysteresis. Based on this characteristic, the 1T1R cell’s operation can be understood as follows: after an initial electro-Forming (FMG) step [15], the memory element can be switched reversibly between LRS and HRS. Resistive switching corresponds to an abrupt change between an HRS and LRS. The resistance change is triggered by applying specific biases across the 1T1R cell, i.e., V_SET to switch to an LRS after a SET operation and V_RST to switch to an HRS after a RESET (RST) operation.

In the 1T-1R configuration, the transistor controls the amount of current flowing through the cell according to its gate voltage bias. The maximum current allowed by the selected transistor is called the compliance current and is referred to as the I_CC in Figure 1c. The I_CC controls the LRS resistance value in the SET state, as well as the maximal RST current I_reset [16]. The voltage levels used during the different operating steps are presented in

Table 1. Standard RRAM cell operating voltages.

	FMG	RST	SET	READ
WL	2 V	2.5 V	2 V	2.5 V
BL	3.3 V	0 V	1.2 V	0.1 V
SL	0 V	1.2 V	0 V	0 V
Resistance	10 kΩ	240 kΩ	15 kΩ	-
Conductance	100 μS	4.17 μS	66.6 μS	-

, along with the nominal resistance and conductance values. During the read operation, a small read voltage (0.1 V) is typically chosen to not disturb the resistance state of the cell.

2.2. OxRAM Conductance Modulation for Synapse Emulation

The synapse plays a vital role in biological neural networks, yet creating an electronic counterpart is challenging, making it difficult to develop hardware that replicates biological networks [10]. RRAM devices have demonstrated the ability to be used as a synapse within hybrid analog circuits [17,18]. Since an RRAM device’s conductance can be electrically and incrementally increased or decreased, it is a potential candidate for emulating a biological synapse. To modulate the RRAM cell’s conductance values, two different approaches can be considered. The first one is based on controlling the maximum voltage during the RST operation [19] and the second one is based on compliance current modulation during the SET operation [20]. Another technique that involves changing the pulse width of RST and SET voltages can also be considered [21]. In this study, the compliance current modulation approach is used, achieved by changing the compliance current I_CC. Higher I_CC values lower the LRS resistance, while lower I_CC values increase the LRS resistance. In the 1T1R cell, the current involved in the SET operation is controlled by changing the gate transistor voltage V_WL (see Figure 1a). Figure 2a shows the effect of 11 different V_WL voltage levels on a single RRAM cell, with V_WL voltages ranging from 1 V to 2 V with a 0.1 V voltage step. As the V_WL increases, the maximum SET current increases, resulting in 11 distinctive LRS levels. The plot of R_LRS versus V_WL is presented in Figure 2b for increasing V_WL values (the same single cell is considered), with R_LRS being extracted at 0.1 V. A decrease in R_LRS as V_WL increases is clearly visible. The resistance range obtained using this programming technique varies from 87 μS (11.5 kΩ) to 24.7 μS (40.4 kΩ) as V_WL changes from 1 V to 1.8 V, as presented in

Table 2. OxRAM conductance modulation range.

Parameter	Min	Max
VWL	1 V	1.8 V
Resistance	11.5 kΩ	40.4 kΩ
Conductance	87 μS	24.7 μS

. This conductance range will be used to map the weights of neural networks within a crossbar array made of oxide-based RRAMs.

3. Artificial Neural Network Weight Mapping Methodology

In this section, we provide a comprehensive step-by-step overview of implementing an RRAM-based neural network for image classification. The process involves translating the neural network’s parameters, typically weights and biases, from the software domain to an RRAM array. The mapping process consists of three key steps: (i) ANN architecture definition and offline model generation after training using a software-based approach (e.g., Python or MATLAB); (ii) the transfer of the learned weights and biases to the hardware (i.e., RRAM array mapping); and (iii) vector–matrix multiplication execution at the hardware level.

3.1. ANN Architecture Definition and Training

The most studied network architecture in the literature is the fully connected NN [22,23,24,25], where each neuron in a layer is connected to every neuron in the previous layer. In this work, a 2-layer fully connected NN is considered. At the software level, the TensorFlow libraries are used to design and train the 2-layer NN model, along with the custom image dataset presented in Figure 3a. In the context of image classification, an image is represented as a matrix of pixels with the dimensions n × m. We have considered 5 × 4 grayscale images representing digits (0–9), in which the color of the pixels is encoded by one single value: each pixel has a value between 0 (black) and 255 (white). Note that before use, a preprocessing step is needed to convert the images into a format suitable for NN training and inference (pixel values are normalized to a range of 0 to 1). In Figure 3a, each class gathers six different instances of the same digit. Given the small size of the images, a simple feedforward NN with two layers is the target. The input layer is fed 20 inputs encoding the 5 × 4 input pixels. The output layer is made of 10 output neurons and determines the final prediction of the model. The model parameters include 200 synaptic weights and 10 biases. Note that 150 epochs are used to train the model.

In TensorFlow, when generating a neural network (NN) model during training, there are multiple options for setting up the model’s parameters (weights and biases) based on different requirements, including polarity and ranges [25]. A specific case is considered in this study, where the model is generated using only positive weights. This approach simplifies the hardware mapping process, as negative values cannot be represented directly with RRAM cells [26]. This model, providing only positive parameters, is used in the rest of this paper. It has been generated at the software level by setting specific constraints during training.

3.2. Hardware Mapping of the ANN Model Parameters

Figure 4 describes how the neural network model presented in Figure 4a can be mapped to the passive crossbar array shown in Figure 4b. In a passive crossbar array, each cell in the array consists of a single resistive element (1R) at each cross-point. The cells in a row are organized by connecting their top electrodes to input neurons I_x (with x ranging from 1 to 20), while the cells in a column are organized by connecting their bottom electrodes to the output neurons O_x (with x ranging from 1 to 10). However, a common integration option, which is adopted in this study, is to place a CMOS transistor in series with the resistive element to control the current that moves through it using the so-called 1 transistor 1 resistor (1T1R) architecture. This approach prevents current paths through neighboring cells, known as “sneak paths” [27]. These unintended paths lead to leakage currents and reduce the read and write accuracy, as the current contribution of a cell might be influenced by currents from other cells rather than reflecting the target cell’s state.

The parameters of the software model are converted into conductance values during a programming operation that targets individual cells within the crossbar array. This process is facilitated by an additional selection transistor, which enables selective access to each cell and precise control over the current flowing through it, ensuring accurate and reliable conductance mapping. In particular, compliance current control is achieved by adjusting the gate voltage of the selection transistor, allowing the programming of conductance values ranging from 87 μS to 24.7 μS, as detailed in Table 2. Note that the conductance values are derived from the weight matrix using a linear transformation [28]. After conductance mapping, during inference, appropriate input voltages are applied to the crossbar inputs I_x, while all rows are activated through the Word Lines O_x, generating cumulative currents along the columns.

3.3. Vector–Matrix Multiplication in a 1T1R Array

As already mentioned, an array of RRAM cells could naturally accomplish VMM within one step by collecting the output currents of the array. Figure 5b describes how the basic neural network model of Figure 5a can be mapped to a 1T1R crossbar RRAM array.

The cells in a row are organized by attaching the transistor gate nodes to the Source Line (SL) and the transistor drain nodes to the WL, while the cells in a column are arranged by attaching the bottom electrodes of the RRAM cells to the Bit Line (BL). Input vectors (X_x) are associated with input voltages (V_x) and the matrix weights (W_ki) are associated with the cell resistance values, R_ki. Based on Equation (1), related to Figure 5a, VMM can be easily implemented following Equation (2), related to Figure 5b: when the voltages V_x are applied to the rows, the SLs are turned ON and the current through each cell is proportional to the product of the input voltage and the cell’s conductance (which represents its weight). Accumulation is then performed along the BLs through current summing and reflected in the total current I_k (1 < k ≤ m). I_k currents are considered to be the circuit responses and will be compared with the neural network’s software output to assess the hardware’s emulation accuracy. It is worth mentioning that an activation function (not presented here) can be applied to the total current.

$$Y_k=\sum _{i=1}^{i=n}{W}_{ki}.X_{i}1<k\le m$$

(1)

$$I_k=\sum _{i=1}^{i=n}{\displaystyle \frac{1}{R_{ki}}}.V_{i}1<k\le m$$

(2)

4. Circuit-Level Simulation Results for the Inference Stage

A 20 × 10 1T1R array was designed and simulated using the Eldo simulator within the Cadence environment, using a 0.13 μm high-voltage CMOS technology from ST-Microelectronics. The choice of a high-voltage technology is imposed by the RRAM FMG operation, which requires transistors to sustain a 3.3 V supply voltage. A compact model, fully calibrated on silicon, is used to represent the RRAM cells [29]. The proposed RRAM modeling approach relies on the electric field-induced creation/destruction of oxygen vacancies within the switching layer. The model enables continuous accounting for both SET and RST operations within a single master equation, in which the resistance is controlled by the radius of the conduction filaments (3):

$${\displaystyle \frac{d{r}_{CF}}{dt}}=\left(r_{\mathit{CF}\max }-r_{CF}\right)\cdot {10}^{{\beta }_{\mathrm{Re}dOx}}\cdot e^{-{\displaystyle \frac{Ea-q\cdot {\alpha }_{red}\cdot V_{cell}}{k_b\cdot T}}}-r_{CF}\cdot {10}^{{\beta }_{\mathrm{Re}dOx}}\cdot e^{-{\displaystyle \frac{Ea+q\cdot {\alpha }_{ox}\cdot V_{cell}}{k_b\cdot T}}}$$

(3)

where β_RedOx is the nominal oxide reduction rate, Ea is the activation energy, α_red and α_ox are the transfer coefficients (ranging between 0 and 1), k_b is the Boltzmann constant, r_CFmax is the maximal size of the conductive filament radius, T is the temperature, and V_cell is the voltage across the cell. Moreover, the model makes the assumptions of a uniform radius across the conduction pathways, a uniform electric field in the cell, and a temperature-triggered acceleration of the oxide reduction reactions (“redox”). Finally, the total current in the RRAM array includes two components, i.e., one related to the conductive species, I_CF (4), and the other to the conduction through the oxide, I_OX (5).

$$I_{CF}={\displaystyle \frac{V_{Cell}}{L_x}}\cdot \left(\pi \cdot r_{CF}^2\cdot \left({\sigma }_{CF}-{\sigma }_{OX}\right)+\pi \cdot r_{CF\max }^2\cdot {\sigma }_{OX}\right)$$

(4)

$$I_{OX}=A_{HRS}\cdot S_{Cell}{\left({\displaystyle \frac{V_{Cell}}{L_{\mathit{x}}}}\right)}^{{\beta }_{HRS}}$$

(5)

where L_x is the oxide’s thickness, S_Cell is the total area of the device, σ_Ox is the oxidation rate, and σ_CF is the reduction rate. To take into account the I_OX trap-assisted current (Poole-Frenkel, Schottky emission, Space Charge Limited Current (SCLC)), a power law between the cell current and the applied bias is considered, with the two parameters A_HRS and β_HRS. Finally, the total current flowing through the cell is given in (6):

$$I_{Cell}=I_{CF}+I_{OX}$$

(6)

Note that I_CF is the main contributor to an LRS current (I_LRS) and I_OX is the main contributor to an HRS current (I_HRS).

Based on this simulation setup, conductance mapping is performed using the compliance current modulation technique to achieve conductance values within the range specified in Table 2. During inference, the digital values of the image pixels are converted to voltage values. A white pixel (255) is associated with a voltage applied to the crossbar rows equal to 0.3 V, while a black pixel (0) is associated with a voltage equal to 0.0 V. These voltages are carefully chosen to ensure no shifting of the RRAM cell conductance state during inference. The model’s accuracy is evaluated based on a new dataset never seen by the model. In this dataset, the color of half of the pixels of each image has been modified to values different from 0 (black) and 255 (white). At the software level, values of 15 and 240 have been chosen for black and white, respectively. At the hardware level, corresponding intermediate voltage values are obtained after a linear transformation.

Figure 6a presents the inference accuracy results obtained through software-based simulations. The X-axis represents the output classes while the Y-axis represents the measured current values. Figure 6b shows the corresponding hardware-based simulation results, where the Y-axis represents the output logits corresponding to the results of the vector–matrix multiplication (VMM) operation, expressed as floating-point values. In classification tasks, logits refer to the raw output (i.e., unnormalized values) produced by the final layer before applying any activation functions, such as softmax.

For each digit ranging from 0 to 9, displayed on the X-axis, blue and red bars represent the amplitudes of the output logits/currents. The blue bar corresponds to the logit/current associated with the target digit (indicated at the top of each histogram), while the red bars correspond to the logits/currents of non-target digits, which should be ignored. For a targeted digit, the inference test is considered successful if the blue bar exceeds all the red bars. Moreover, inference accuracy improves as the margin by which the blue bar surpasses the red bars increases. Based on these observations, Figure 6a,b demonstrate that an overall accuracy of 100% is achieved at both the software and hardware levels. However, the difference between the blue and red bars’ heights is more pronounced in the software results, indicating that classification efficiency is comparatively lower at the hardware level.

To assess the confidence level of the model’s predictions during inference, a parameter called Margin Confidence (MC) [28] can be computed. The MC is defined as the difference between the logits or currents of the most probable class and the second most probable class. A higher MC value indicates a more confident prediction. In this study, the relative average MC of the software approach is 43.82% across all the tested digits, while the hardware approach achieves a relative average MC of 16.39% (a 27.43% drop), highlighting the superior accuracy of the software approach. The drop in classification accuracy at the hardware level is primarily due to the limited conductance range of RRAM technology, which restricts its possible weight values. As shown in Table 2, the mapped weights fall within a conductance range of 87 μS to 24.7 μS. Beyond these intrinsic limitations, circuit-level parasitics, including resistive and capacitive effects from transistors and the RRAM model, also impact the RRAM-based neural network’s accuracy, though to a lesser extent.

From an energy perspective, the hardware simulation results indicate that current levels fall within the range of tens of microamperes, with peak currents reaching 165 μA and an average current consumption during a single inference of 1260.6 μA. The energy efficiency of the inference process can be quantified in various ways, including the total inference energy, which represents the energy required to process an entire input digit. Assuming a 100 ns/0.3 V input voltage pulse during inference (aligned with the RRAM read voltage pulse requirements [25]), the total energy dissipated during inference is found to be 38 pJ. Energy efficiency can also be expressed as the energy consumed per MAC operation, typically expressed in pJ/MAC or fJ/MAC. Given that processing a single input sample involves 200 MAC operations (20 input neurons × 10 output neurons), the energy dissipation per MAC operation is found to be 190 fJ/MAC. Energy-related metrics are summarized in

Table 3. Neural network energy efficiency during inference.

Inference Parameters	Value
Crossbar current	12,686 μA
Crossbar power	37.8 mW
Total inference energy	38 pJ
Energy/MAC	190 fJ/MAC

. Regarding the latency of the VMM engine, it is on the order of nanoseconds, as it is primarily influenced by R-C delays (i.e., resistance–capacitance delays) associated with the crossbar’s interconnections. Since peripheral elements such as DACs and ADCs are not considered in the latency calculation, this parameter should be considered with caution, as currents are generated almost instantaneously at the output of the crossbar array.

5. Discussion

In the adopted software-weighted mapping approach, only positive floating-point numbers were used for the neural network parameters. Implementing negative weights and biases would have required additional rows or columns in the crossbar array, along with increased design complexity [30,31] due to the need for handling additional signals and managing negative voltages. Regarding energy considerations, it is important to note that before inference, memory cells must be programmed to achieve specific conductance levels aligned with the software weight matrix. During this stage, since the RRAM’s write performance is typically orders of magnitude worse than its read performance in terms of energy consumption [32], the NN accelerator needs to be designed to supply this amount of energy. Consequently, to minimize expensive resistive memory programming operations, weights are usually programmed into memory prior to inference and remain fixed throughout the inference process. Regarding the crossbar size, it is important to note that large images typically require a correspondingly large number of rows in the crossbar structure. In software-based ANNs, this is not a challenge. However, the available inputs in hardware NNs are limited by the maximal size of the crossbar. The approach adopted in this study involves generating a set of 5 × 4 custom-designed images, effectively limiting the crossbar to 20 rows. In this work, we have introduced and focused on the analog VMM engine of a hardware accelerator. However, AI accelerators come with unique challenges and limitations related to peripheral circuits, such as ADCs and DACs, which are not addressed here. The accuracy and energy consumption of a VMM engine are often dominated by DACs and ADCs. Depending on DACs’ and ADCs’ architecture, one or several of their performances can grow exponentially with bit precision [33]. Therefore, at high precision, VMM engines may lose the energy and area advantages they have over digital accelerators. Another parameter not addressed in this study is related to the flexibility of the VMM engine, which has been designed in our study to process images of a specific size. For an RRAM chip to be broadly adopted in practical AI applications, not only does it need to deliver notable energy efficiency, but it also needs to offer flexibility to support various AI model architectures [34].

Another challenge to be overcome for reliable RRAM-based VMM engines is related to the variability of the underlying memristor technology. Indeed, RRAM variability poses a significant hurdle for the widespread adoption of RRAM in neuromorphic computing systems. Variability refers to the inherent differences in the electrical characteristics of RRAM devices, even when fabricated under the same manufacturing conditions. This variability can manifest as variations in the key parameters of RRAM devices, including their resistance levels, thus preventing accurate conductance modulation, which is crucial for accurate neural network operations [35]. In addition to variability, over time, a typical bottleneck for OxRAMs lies in their endurance and retention reliability issues. These two reliability metrics narrow the resistance window, thus significantly reducing their conductance modulation capability [36,37]. Note that cycling and endurance can lead to hard errors (such as memory cell being stuck in one state forever). Similarly to other emerging memory technologies, RRAM is inclined to defects [38] due to manufacturing conditions. Hence, appropriate test strategies are required to detect RRAM-related failures [39]. In addition to conventional faults, RRAM, due to its specific manufacturing process and switching mechanism, can be impacted by unique faults such as over-forming and undefined state faults [40]. Therefore, a complete fault analysis methodology needs to be defined for this class of memory technology. Alternatively, RRAM neural networks have the potential to be used in harsh spatial environments [41,42]. In such conditions, there are certain considerations and challenges that need to be addressed for RRAM to operate reliably, such as high levels of radiation, including ionizing particles [43,44]. This radiation can cause unwanted effects, such as resistance drifts, during the OxRAM device’s operation. To mitigate these effects, OxRAM devices need to be radiation-hardened or shielded [9].

6. Conclusions

In recent years, hardware accelerators leveraging emerging resistive memory technologies have shown significant progress. However, research on the ability of resistive devices to efficiently emulate synaptic behavior remains in its early stages. In this context, this study investigates the implementation of RRAM-based crossbar arrays serving as analog VMM (vector–matrix multiplication) engines. Our analysis is supported by experimental data from HfO₂-based RRAM devices, whose conductance values can be finely tuned to map the neural network software’s weight matrix. The simulation results demonstrate that both software and hardware implementations of the neural network model achieve 100% inference accuracy. Accuracy results have shown that the classification performance of the hardware is reduced due to the limited conductance range provided by RRAM technology (the relative average MC drops from 43.82% to 16.39%, resulting in a decrease of 27.43%). While the hardware implementation experiences an accuracy degradation, it can achieve significant improvements in power efficiency and computation speed. Hardware simulations have provided an energy consumption of 2.53 pJ/MAC for the VMM engine with a latency on the order of nanoseconds. These results highlight the potential of memristor crossbar arrays as a viable alternative to traditional computing platforms for AI applications, particularly in edge computing scenarios where power constraints are predominant.