Investigation of Source/Drain Height Variation and Its Impacts on FinFET and GAA Nanosheet FET

Abstract

As semiconductor technology and process nodes advance, three-dimensional devices like FinFET and NSFET are increasingly becoming the primary choice, replacing planar MOSFETs. However, the complex manufacturing processes and high process sensitivity of three-dimensional devices at advanced process nodes inevitably cause significant deviations from the ideal structure during actual fabrication, leading to notable changes in their electrical characteristics. This paper investigates the impact of source/drain region height fluctuations caused by etching and epitaxial growth variations on the electrical characteristics of FinFET and NSFET devices, as well as their related circuits. The electrical characteristics when height variations occur in single and multiple electrodes indicate that, although NSFET and FinFET generally exhibit similar properties such as a decrease in the ON-state current when the source/drain height is reduced, the independent nature of the nanosheets in NSFET and the unidirectional conduction of Schottky contact resistance cause significant differences in their electrical characteristics. Additionally, the related circuit-level simulations show that height fluctuations in the source/drain regions of devices can significantly impact circuit characteristics, including voltage and delay, and in severe cases, they may even lead to circuit failure.

1. Introduction

As semiconductor process nodes continue to shrink, three-dimensional devices such as FinFET and NSFET are gradually replacing planar MOSFET as the main device structures in advanced nodes [1]. Furthermore, due to better gate control capabilities, NSFETs are considered the most promising candidate device structures for nodes below 3 nm [2,3]. However, the complex manufacturing processes of three-dimensional devices, combined with a higher sensitivity to process variations at advanced nodes, place higher demands on lithography, etching, deposition, and other processes. Due to the aforementioned reasons, devices in actual production often deviate from the ideal situation because of process variations and process deviations, resulting in changes in device characteristics [4,5]. Currently, many papers investigate the impact of process variations and deviations on advanced devices such as NSFETs and FinFETs, including the effects of channel dimensions and geometries [6], process angles [7], non-ideal etching [8], and defects under severe process deviations on the electrical characteristics of the devices [9,10]. In recent years, numerous papers have reported instances of source/drain height variations in manufacturing processes due to deviations in epitaxial growth and etching processes [11,12,13]. Additionally, existing studies have analyzed the impact of the recess process on the source/drain regions and the electrical characteristics of the devices [14]. Considering the high compatibility between NSFET and FinFET processes, the aforementioned process deviations related to the source/drain in FinFET are also likely to occur in NSFET devices [15]. However, due to the multi-layer stacked structure of NSFET devices in the vertical direction, the impact of source/drain height variations caused by deviations in etching and epitaxial processes on their electrical characteristics is significantly different from that of FinFET devices. Currently, there are few analyses on the impact of source/drain height fluctuations on the electrical characteristics of NSFET devices. To deeply investigate the impact of source/drain height variations caused by process fluctuations on the electrical characteristics of devices, this paper simulates different source/drain heights in FinFET and NSFET devices. Additionally, it explores the influence of these variations on circuit-level performance using an INV cell, NAND cell, and five-stage ring oscillator (RO) circuits.

2. Device Structure and Simulation Condition

Figure 1a shows the structures of NSFET and FinFET devices used in this work. Furthermore, Figure 1b shows the channel profile and doping of the devices. As can be seen from the images, in this study, the NSFET consists of three stacked nanosheets, whereas the FinFET is a single-fin device. The main parameters related to size and doping in this work are based on the 2020 International Roadmap for Devices and Systems [16], and the specific parameters are shown in

Table 1. Device physics parameters.

Parameter	Symbol	Value
Gate Length	${\mathit{L}}_{\mathrm{g}}$	12 nm
Spacer Length	${\mathit{L}}_{\mathrm{sp}}$	5 nm
Inner Spacer Length	${\mathit{L}}_{\mathrm{insp}}$	1 nm
S/D Length	${\mathit{L}}_{\mathrm{sd}}$	12 nm
S/D Height	${\mathit{H}}_{\mathrm{sd}}$	65 nm
Nano-Sheet Width	${\mathit{NS}}_{\mathrm{W}}$	25 nm
Nano-Sheet Thickness	${\mathit{NS}}_{\mathrm{T}}$	5 nm
Nano-Sheet Distance	${\mathit{NS}}_{\mathrm{D}}$	10 nm
Fin Width	${\mathit{Fin}}_{\mathrm{W}}$	8.3 nm
Fin Height	${\mathit{Fin}}_{\mathrm{H}}$	45 nm
Equivalent Oxide Thickness	${\mathit{E}}_{\mathrm{OT}}$	0.7 nm
Channel Doping	${\mathit{N}}_{\mathrm{Ch}}$	$1\times {10}^{16}{\mathrm{cm}}^{-3}$
LDD Doping	${\mathit{N}}_{\mathrm{LDD}}$	$2\times {10}^{18}{\mathrm{cm}}^{-3}$
S/D Doping	${\mathit{N}}_{\mathrm{SD}}$	$2\times {10}^{20}{\mathrm{cm}}^{-3}$
Bulk Doping	${\mathit{N}}_{\mathrm{Bulk}}$	$2\times {10}^{18}{\mathrm{cm}}^{-3}$
Substrate Doping	${\mathit{N}}_{\mathrm{Sub}}$	$2\times {10}^{18}{\mathrm{cm}}^{-3}$
Gate Work Function	${\mathit{W}}_{\mathrm{F}}$	4.41 eV

. To more intuitively and accurately compare the electrical performance of NSFET and FinFET as the source/drain height varies, the channel dimensions of FinFET were finely adjusted so that the channel areas of both devices are approximately the same, as shown in

Table 2. Effective channel area of NSFET and FinFET.

Device Types	Formula	Value
NSFET	${\mathit{NS}}_{\mathrm{W}}\times {\mathit{NS}}_{\mathrm{T}}\times 3$	375 ${\mathrm{nm}}^2$
FinFET	${\mathit{Fin}}_{\mathrm{W}}\times {\mathit{Fin}}_{\mathrm{H}}$	373.5 ${\mathrm{nm}}^2$

.

Simulation is performed in Sentaurus TCAD. Quantum confinement is considered by adopting the density gradient quantization model. The simulations employ the inversion layer and accumulation layer mobility models to simulate the mobility degradation caused by impurity, phonon, and surface roughness scattering. SRH recombination, Auger recombination, and the Philips unified mobility model are also adopted. Self-heating effects are considered in this simulation work, and the thermal conductivity of different regions is set according to the literature references [17]. The channel crystal orientation is precisely set, and the anisotropy of heat propagation is taken into account. Additionally, for Schottky contacts affected by lower source/drain heights, the SRDoping model is activated to consider the image-force potential lowering effect in Schottky contacts. To ensure the accuracy of the TCAD simulation, the physical model and material parameters are calibrated using NSFET experimental data [16]. The calibration results of NSFET are shown in Figure 2a and the electrical performance of FinFET under the same simulation settings are shown in Figure 2b. The simulation results in Figure 2b indicate that the electrical performance of NSFETs is significantly superior to that of FinFETs, which is consistent with the conclusions presented in other papers [3,18].

3. The Impact of Source/Drain Height Variations on Electrical Performance

3.1. The Impact of Height Variations of Different Electrodes on Device Electrical Characteristics

Height variations in the source/drain regions caused by etching or epitaxial growth process deviations lead to electrode metal deposition over the abnormal areas during the subsequent processing steps, resulting in direct contact with the LDD region, as depicted in Figure 3. It should be noted that due to the low doping concentration in the LDD region, the contact resistance between the metal and the LDD region is the Schottky contact resistance rather than ohmic contact resistance. In this section, to thoroughly investigate the impact of height variations in different electrodes on the electrical characteristics of the devices, comprehensive simulations were conducted for FinFET and NSFET devices under conditions of abnormal source, abnormal drain, and concurrent abnormalities in both source and drain. Additionally, to significantly compare the changes in electrical characteristics between NSFET and FinFET devices, in this section, the height of the source/drain is set at the midpoint between the two lowermost nanosheets of the NSFET.

The electrical behavior of NSFET and FinFET devices with reduced source/drain heights is shown in Figure 4a,b. It can be observed from the figures that the primary impact of reduced source/drain heights on device performance is a reduction in ON-state current. When the source/drain heights are both reduced, the ON-state currents of NSFET and FinFET decrease to 49.1% and 69.3% of their original values, respectively.

However, in cases where only the source or drain is affected, the electrical properties of NSFET and FinFET show significant differences. For FinFET, the excessive etching or insufficient epitaxy of only the source has a more profound impact, whereas for NSFET, the situation is reversed. The cause of this phenomenon lies in the unidirectional conduction characteristics of the Schottky barrier. For NSFET, due to the independence of each nanosheet, the Schottky contact resistance between the drain and the LDD region impedes current flow. In contrast, for FinFET, since its channel is integrated, electrons can move through the remaining drain region; thus, the Schottky resistance at the drain has a limited obstructive effect. Additionally, this explains why the electrical characteristic curves of NSFET remain similar whether only the drain is affected or whether both the source and drain are compromised. However, if the doping concentration in the LDD region is sufficient and the contact resistance formed with the metal is ohmic, the ON-state current of NSFET with only the source dimension reduced is significantly lower than that with only the drain dimension reduced. This observation is consistent with the behavior seen in FinFET, where the current is generally higher when the source height is reduced compared to when the drain height is reduced, thereby substantiating the conclusion depicted in Figure 5. Furthermore, the simulation results in Figure 5 indicate that increasing the doping concentration in the lightly doped region to form an Ohmic contact with the metal can effectively mitigate the degradation of device performance caused by the reduction in source/drain height.

Under specific source and drain anomalies, Figure 6 exhibits the eDensity distribution for NSFET and FinFET. The figure distinctly demonstrates that any irregularities in the source and drain markedly influence the eDensity, with the source having a more pronounced impact. It is important to note that for NSFET, under Schottky contact conditions, although the eDensity is significantly higher when only the source is affected compared to when only the drain is affected, the actual ON-state current exhibits the opposite trend. This further corroborates the simulation results and related inferences presented in Figure 4 and Figure 5.

The capacitance characteristics of NSFET and FinFET devices under height variations in different electrodes are shown in Figure 7. To facilitate the understanding of the proportion of ${\mathit{C}}_{\mathrm{GD}}$ and ${\mathit{C}}_{\mathrm{GS}}$ within ${\mathit{C}}_{\mathrm{GG}}$, these are plotted alongside ${\mathit{C}}_{\mathrm{GG}}$ on the same graph. As observed in Figure 7, when there is a change in height of only one electrode, the contact between the metal and LDD alters the electric field distribution within the channel. Consequently, both NSFET and FinFET exhibit a decrease in capacitance between the defective electrode and the gate, while the capacitance on the opposite side increases. However, the changes in capacitance characteristics on both sides counterbalance each other, resulting in minimal variation in the ${\mathit{C}}_{\mathrm{GG}}$-${\mathit{V}}_{\mathrm{G}}$ curve. In contrast, in scenarios where both the source and drain electrodes undergo height alterations, there are significant differences in the performance of NSFET and FinFET. Particularly for NSFET, the ${\mathit{C}}_{\mathrm{GG}}$ shows a noticeable decrease when such defects are present. This is because the channels in NSFET are independent of each other, and the complete contact of the upper two channels with the metal significantly changes the internal electric field. For FinFET, the Schottky barrier alters the electric field of the FinFET channel, causing shifts in ${\mathit{C}}_{\mathrm{GS}}$ and ${\mathit{C}}_{\mathrm{GD}}$ compared to the defect-free condition. However, the overall integrity of the channel in FinFET prevents significant changes in ${\mathit{C}}_{\mathrm{GG}}$, resulting in only a slight increase in ${\mathit{C}}_{\mathrm{GG}}$.

3.2. The Impact of Varying Degrees of Height Changes on Device Electrical Characteristics

This chapter investigates the impact of varying degrees of source/drain dimension reduction caused by process fluctuations and deviations on the electrical characteristics of devices. Based on the structural characteristics of NSFET, this study selects several typical height values to examine the impact of various height changes on device electrical performance. For comparison, the same height settings were applied to FinFET, as shown in Figure 8. Additionally, to facilitate the discussion, this chapter exclusively considers scenarios where both the source and drain dimensions undergo height changes.

Under the conditions of ${\mathit{V}}_{\mathrm{D}}={\mathit{V}}_{\mathrm{G}}=0.7$ V, the relationship between the ON-state current, ${\mathit{C}}_{\mathrm{GG}}$ capacitance and the degree of height reductions in the source/drain dimensions for NSFET and FinFET is illustrated in Figure 9a,b. In addition to the ON-state current and parasitic capacitance, to more thoroughly analyze the impact of reducing source/drain height on the performance of NSFET and FinFET, the threshold voltage of the devices was also extracted and the DIBL effect of the devices was calculated, as shown in Figure 9c,d. The drain bias voltage for the other transfer characteristic curve used to calculate the DIBL effect is 0.05 V. The detailed performance data of the devices, including the ON-state current, is shown in

Table 3. Electrical characteristic data of NSFET and FinFET at different source/drain heights.

Label	${\mathit{H}}_{\mathbf{sd}}$ (nm)	${\mathit{I}}_{\mathbf{on}}$ ($\mathsf{\mu }$A)		${\mathit{C}}_{\mathbf{GG}}$ (${10}^{-16}$ F)		${\mathit{V}}_{\mathbf{th}}$ (V)		DIBL (mV/V)
		NSFET	FinFET	NSFET	FinFET	NSFET	FinFET	NSFET	FinFET
H0	65.0	141.95	83.51	1.934	1.195	0.327	0.320	112.0	261.5
H1	55.0	155.88	87.21	1.937	1.199	0.326	0.319	106.2	247.7
H2	45.0	161.30	89.48	1.938	1.201	0.326	0.320	106.2	238.5
H3	42.5	154.39	86.35	1.938	1.201	0.332	0.324	104.6	243.1
H4	40.0	113.26	81.04	1.938	1.201	0.348	0.329	135.4	255.4
H5	35.0	115.32	73.00	1.723	1.202	0.348	0.333	132.3	281.5
H6	30.0	117.29	61.89	1.725	1.202	0.350	0.356	129.2	321.5
H7	27.5	108.60	53.95	1.725	1.203	0.360	0.373	138.5	356.9
H8	25.0	59.76	44.33	1.726	1.203	0.397	0.399	250.8	403.1
H9	20.0	60.13	34.85	1.585	1.204	0.398	0.433	243.1	×
H10	15.0	60.60	25.20	1.585	1.204	0.398	0.485	238.5	×
H11	12.5	47.22	17.75	1.584	1.204	0.432	0.546	290.8	×
H12	10.0	$8\times {10}^{-5}$	7.71	1.581	1.205	×	×	×	×
H13	5.0	$6\times {10}^{-5}$	1.01	1.443	1.205	×	×	×	×

. The parts marked with “×” in the table indicate that under these conditions, with a drain bias voltage of 0.05 V or 0.7 V, the threshold voltage of the transfer characteristic curve has already exceeded 0.7 V.

From Figure 9a, it can be observed that, for NSFET, the ON-state current exhibits an increasing trend as the source/drain dimensions decrease before reaching the top nanosheet, due to the decrease in vertical resistance. When the etching defect extends into the top nanosheet, the current begins to decrease. However, as mentioned in the previous chapter, the remaining parts of the source and drain that are in contact with the LDD can still provide a current path, making the decrease in current less significant. Once the LDD region is entirely in contact with the metal, the Schottky resistance greatly inhibits the current, leading to a noticeable drop. As the degree of etching caused by process deviations increases, this process will repeat, with the ON-state current showing alternating increases and decreases. Overall, there will be a significant reduction until the entire LDD region is in contact with the metal, at which point the ON-state current is almost completely suppressed. The current variation in FinFET devices is relatively straightforward. Before the abnormal etching reaches the channel height, the ON-state current gradually increases due to the reduction in vertical resistance. Subsequently, as the source/drain dimensions continue to decrease, the current gradually decreases. Since the remaining source/drain regions in contact with the LDD always provide a current path, the final ON-state current is more significant compared to NSFET.

As for the capacitance, as mentioned in the previous chapter, due to the independence of the channels in NSFET, once the LDD region is entirely in contact with the metal, the resulting electric field change will cause a significant reduction in the ${\mathit{C}}_{\mathrm{GG}}$ capacitance. In contrast, the capacitance in FinFET remains almost unchanged, with only a slight increase, as shown in Figure 9b. In summary, NSFET is more sensitive to defects in the reduction of source and drain dimensions, especially when the height corresponds to the bottom of each channel. Even minor process variations can lead to significant changes in the device’s current and capacitance.

Interestingly, the behavior of threshold voltage and DIBL effect for NSFET and FinFET are the opposite to those of the current and capacitance characteristics. As the source/drain height decreases, the changes in threshold voltage and DIBL effect for FinFET devices are much greater than those for NSFET devices. Besides the inherently better related performance characteristics of NSFET itself, the independent nature of the nanowires in NSFETs might offer some advantages. As mentioned earlier, when the drain height decreases, the Schottky barrier contact causes the nanowire to be completely turned off, almost entirely nullifying its effect of the device current. In other words, at this point, a three-stack NSFET would behave more like a two-stack NSFET or a one-stack NSFET. In contrast, for FinFET, as its channel is an integral whole, the continuously invading metal material causes the gate’s control over the upper part of the channel to weaken, eventually leading to greater fluctuations in the threshold voltage and DIBL effect.

4. Circuit-Level Benchmark Results

Based on the calibration data in Figure 2, a PMOS transistor was constructed in TCAD to ensure that its ON-state current closely matches the NMOS data, as shown in Figure 10. After obtaining the electrical characteristics of the PMOS, the KeySight MBP parameter extraction software was used to extract the SPICE characteristic parameters for both NMOS and PMOS, which will be used for the subsequent cell-level simulations. Considering the structural characteristics of NSFET and the variations in ON-state current, the current characteristic curves of NSFET at 35 nm (H5), 25 nm (H9), and 5 nm (H13) were selected from Table 3 as the representative values. These values were used to simulate the circuit performance of NSFET under different conditions of channel failure. Additionally, due to the significant difference in the magnitude of the ON-state current between defect levels of 25 nm (H9) and 5 nm (H13) in NSFET, cases with defect levels of 10 nm (H12) and 5 nm (H13) in FinFET were also selected to simulate the device’s performance under severe defects without complete failure (open circuit), caused by process deviations. For convenience, in the following text, the NMOS transistors are sorted in descending order of their ON-state currents and relabeled from Case 0 to Case 5, as shown in

Table 4. Data of NMOS transistors for circuit simulation.

Label	Case 0	Case 1	Case 2	Case 3	Case 4	Case 5
Device Type	NSFET	NSFET	NSFET	FinFet	FinFet	NSFET
Height (nm)	65 (H0)	35 (H5)	20 (H9)	10 (H12)	5 (H13)	5 (H13)
On Current ($\mathsf{\mu }$A)	141.9	115.3	60.1	7.7	1.0	$6.20\times {10}^{-5}$

.

In this study, NMOS and PMOS transistors were utilized to construct basic inverter cells, two-input NAND gates, and a five-stage ring oscillator, as shown in Figure 11. Subsequently, the internal NMOS transistors were replaced with transistors of different source/drain heights to study the impact of source/drain height variations caused by process deviations on cell-level circuit performance. The output voltage under DC simulation settings for the inverter (INV) is presented in

Table 5. Output voltage values and voltage offsets of inverters under different conditions.

Cell: INV ${\mathbf{V}}_{\mathbf{DD}}$ = 0.7 V
Label	On Current ($\mathsf{\mu }$A)	${\mathbf{V}}_{\mathbf{A}}$ (V)	${\mathbf{V}}_{\mathbf{ZN}}$ (V)	Voltage Offect
Case 0	141.9	0.70	0	0
Case 1	115.3	0.70	0	0
Case 2	60.1	0.70	0	0
Case 3	7.7	0.70	0.1229	17.6%
Case 4	1.0	0.70	0.6419	91.7%
Case 5	$6.20\times {10}^{-5}$	0.70	0.6985	99.8%

, the output voltage under DC simulation settings for the NAND gate is shown in

Table 6. Output voltage values and voltage offsets of NAND under different conditions.

Cell: NAND ${\mathbf{V}}_{\mathbf{DD}}$ = 0.7 V
Label	On Current ($\mathsf{\mu }$A)	${\mathbf{V}}_{\mathbf{A}}\&{\mathbf{V}}_{\mathbf{B}}$ (V)	${\mathbf{V}}_{\mathbf{ZN}}$ (V)	Voltage Offect
Case 0 (M1)	141.9	0.70	0.0059	0.8%
Case 1 (M1)	115.3	0.70	0.0085	1.2%
Case 2 (M1)	60.1	0.70	0.0695	9.9%
Case 3 (M1)	7.7	0.70	0.2429	34.7%
Case 4 (M1)	1.0	0.70	0.5987	85.5%
Case 5 (M1)	$6.20\times {10}^{-5}$	0.70	0.6961	99.4%
Case 0 (M2)	141.9	0.70	0.0058	0.8%
Case 1 (M2)	115.3	0.70	0.0146	2.1%
Case 2 (M2)	60.1	0.70	0.0711	10.2%
Case 3 (M2)	7.7	0.70	0.2648	37.8%
Case 4 (M2)	1.0	0.70	0.5991	85.6%
Case 5 (M2)	$6.20\times {10}^{-5}$	0.70	0.6962	99.4%

, and the delay data for the five-stage ring oscillator, under various conditions, is detailed in

Table 7. Delay of the 5-stage RO at VDD = 0.5 V/0.7 V under different conditions.

Cell: 5-Stage RO ${\mathbf{V}}_{\mathbf{DD}}$ = 0.5/0.7 V
Label	On Current ($\mathsf{\mu }$A)	0.5 V ${\mathbf{T}}_{\mathbf{Delay}}$ (ps)	0.7 V ${\mathbf{T}}_{\mathbf{Delay}}$ (ps)
Case 0	141.9	8.32	5.94
Case 1	115.3	8.95	6.42
Case 2	60.1	11.2	7.53
Case 3	7.7	Functional Failure	10.57
Case 4	1.0	Functional Failure	Functional Failure
Case 5	$6.20\times {10}^{-5}$	Functional Failure	Functional Failure

. It is important to note that test results demonstrate no significant delay changes when the five NMOS transistors in the ring oscillator are sequentially replaced with transistors of varying source/drain heights. Therefore, Table 7 displays only the average values. Additionally, the influence of parasitic parameters at the 7 nm process node was also considered in the simulation.

The DC simulation results for the inverter, as presented in Table 5, demonstrate that minor variations in current caused by height reduction do not impact the output voltage. However, as the severity of transistor defects increases, the deviation of the output voltage from the standard value also rises. When the ON-state current decreases by 95% (7.7 $\mathsf{\mu }$A), a noticeable shift in the output voltage is observed. Furthermore, when the ON-state current reduction exceeds 99% (1.0 $\mathsf{\mu }$A), the voltage offset surpasses 60%, leading to the failure of the inverter’s logical function. The simulation results for the NAND gate in Table 6 are similar to those for the inverter, though the overall trend is more gradual. Additionally, the simulation results indicate that the impact is more severe for transistors near the NAND gate output under the same defect conditions. The data in Table 7 indicate that the delay of the ring oscillator increases as the current decreases. When the current variation is minor, the ring oscillator does not generally experience functional failure. However, when the ON-state current decreases by 95% (7.7 $\mathsf{\mu }$A), functional failure occurs at a lower bias voltage (0.5 V), while at a higher bias voltage (0.7 V), its basic function can still be maintained but with extremely high delay. When the ON-state current reduction exceeds 99% (1.0 $\mathsf{\mu }$A), the functionality of a single inverter can no longer be sustained, leading to the functional failure of the five-stage ring oscillator.

5. Conclusions

This paper investigates the impact of process fluctuations and deviations in etching and epitaxial growth before the metal material deposition on the performance of NSFET and FinFET devices, providing a reliable basis for subsequent improvements in source/drain process detection. The results indicate that for both NSFET and FinFET, a reduction in the height of the source or drain leads to a decrease in the ON-state current, thereby affecting device performance. Notably, unlike FinFET, the individual nanosheets in NSFET are independent. When a nanosheet comes into complete contact with the metal, the Schottky resistance significantly obstructs the current flow within that nanosheet. Similarly, due to the independence of different channels in NSFETs, the Schottky barrier significantly alters the electric field distribution within the channels, resulting in a significant reduction in the capacitance of NSFET. Therefore, NSFET are more sensitive to changes in etching and epitaxial growth processes, making these processes critical factors in the manufacturing of NSFET as next-generation semiconductor devices. However, NSFET does not show higher sensitivity across all performance parameters. Compared to FinFET, NSFET shows better resistance to the threshold voltage and drain-induced barrier lowering (DIBL) effect. Additionally, the simulations of the INV cell, NAND cell, and ring oscillator indicate that the reduction in source/drain height leads to a gradual transition from defect-free functionality to hard defects. This specific performance is closely related to conditions such as bias voltage and transistor position. Therefore, in circuit-level defect diagnostics, it is also necessary to comprehensively consider factors such as the circuit structure and bias conditions to account for this scenario.