Investigation of Source/Drain Height Variation and Its Impacts on FinFET and GAA Nanosheet FET

Comments 1: In fig 1(b), the two panels should be flipped to align with fig 1(a).

Response 1: Thank you very much for pointing out the errors in our figures. We have made the necessary corrections to Figure 1.

Comments 2: The manuscript simulates the current reduction by Schottky contact formation due to source/drain height variation. If this height variation cannot be avoided, can the paper propose possible solutions to mitigate the problem through simulation? For example, the impact of doping concentration in the LDD region on the contact resistance or varying the contact work function.

Response 2: Thank you for your suggestion. In fact, the data presented in Figure 5 already provides a method to mitigate the current degradation caused by height reduction. Specifically, by appropriately increasing the doping concentration in the lightly doped region to form an Ohmic contact with the metal. As shown in the figure 5, this method effectively suppresses the current reduction caused by the decrease in drain height and also has a certain effect on the decrease in source height. We have added the corresponding statements in the paper based on your suggestion.

We have added the following description in line 112 based on your suggestion.

Furthermore, the simulation results in Figure 5 indicate that increasing the doping concentration in the lightly doped region to form an Ohmic contact with the metal can effectively mitigate the degradation of device performance caused by the reduction in source/drain height.

Comments 3: FinFETs and NSFETs have different thermal dissipation properties. In relation to source/drain height variations, self-heating effect might be discussed.

Response 3: Thank you very much for your suggestion regarding self-heating effects. We believe that the reduction in source/drain height has already caused significant impacts on various characteristics of the device, making the discussion of self-heating effects less necessary in this context. In fact, the data presented in this work has taken self-heating effects into account, and we can demonstrate this in our response to you. (The simulations regarding self-heating effects will be demonstrated in the attached document as part of our response to your valuable suggestions.)

Comments 4: The circuit-level simulations assume that all devices have the same source/drain variation simultaneously, which is not realistic in real IC fabrication since local process variations cause random height fluctuations. The circuit simulation may consider to include random height variations at the device level.

Response 4: Thank you very much for your discussion on the practicality of the process. In fact, we have indeed made simplifications here. The reasons for these simplifications are explained as follows. From the analysis of the carrier distribution in Figure 6 and the electrical characteristics of the NSFET device, it can be observed that the mechanisms by which source and drain height variations affect the device current are different, as mentioned in the text. Specifically, the impact of source height variation on the current comes from the reduction in the number of carriers, while the drain height variation is due to the unidirectional conduction of the Schottky contact. When both the source and drain heights decrease, the resulting smaller current is a combined effect of the two mechanisms. Therefore, setting them to the same height does not affect the conclusions regarding the significant current changes caused by the independence of the NSFET nanosheets in the text. To facilitate discussion and avoid redundant conclusions that could affect readability, we have made certain simplifications here.

Comments 1: The fit between the measured and simulated data for the NSFET in Fig. 2 is very impressive and confirms the good calibration of the model. But may more parameters are needed to obtain this level of agreement than the ones listed in Table 1. Perhaps the authors could augment Table 1 with additional model parameters such, for example, as the oxide charge densities and interface traps, they assume for the S:SiO2 interfaces. And by work function I assume they refer to that of TiN, if so perhaps that could be stated explicitly.

Response 1: Thank you for your valuable suggestions. We agree with your review comments and have made the necessary modifications to the relevant data in Table 1. The spacer in our work is of the Dual-K Space structure, and more detailed parameters regarding the spacer have been added. The terminology for the work function has been revised to "Gate Work Function." As for parameters such as the oxide charge densities, we have used the default values of the relevant materials, thus ensuring that the simulation consistency level is not affected.

Comments 2: Figure 3 has an arrow indicating “Ohim Contact”. Perhaps this should be “Ohmic Contact”?

Response 2: Thank you for your valuable review comments. We have corrected the errors in the figures. The annotations in Figures 3, 5, and 6 have all been revised to "Ohmic".

Comments 3: I do not understand the significance of Fig. 5. The figure mentions an NSFET device but the last sentence of page 5 mentions a FinFET. Why does Fig 5 only present results for a NSFET while many other figures compare results between the FinFET and the NSFET? What are the specific values assumed for the different contact resistances in Fig. 5? Please can the authors expand the discussion of Fig 5 so that the reader can better understand its significance.

Response 3: Thank you for your valuable suggestions. We now provide an explanation for the significance of Figure 5. Our work has found that FinFET devices and NSFET devices exhibit opposite current characteristics when there is a height change in either the source or drain. We attribute this to the unidirectional conduction characteristics of the Schottky contact, which causes a reduction in current when the drain height is lowered. To verify this conclusion, we removed the Schottky contact and conducted a re-simulation and found that, as expected, the qualitative current behavior was the same as that of the FinFET device. This figure aims to validate our hypothesis. We have added more detailed explanations in the paper to help readers better understand our findings.

The following are the revised statements.

This observation is consistent with the behavior seen in FinFET, where the current is generally higher when the source height is reduced compared to when the drain height is reduced, thereby substantiating the conclusion depicted in Figure 5.

Comments 1: The effective channel area between NSFET and FinFET appears to have been made similar. However, the effective channel area for NSFET = (sheet height + sheet width) * 6 * gate length and the FinFET area = (2*fin height + fin width) * gate length. Based on these equations and the provided dimensions, the effective channel area is not the same between NSFET and FinFET. Please verify or clarify this comparison.

Response 1: Thank you very much for your question. We would like to explain our reasoning behind it. The difference in the effective channel area between FinFET and NSFET devices is a result of our compromise. Specifically, the fin height of 45nm is a commonly used value in relevant simulation work, and the nanosheet width of 25nm is similarly common and matches the actual process situation. Although related papers have given a fin height of about 53nm, this requires atomic layer etching in the process. Therefore, we chose to adjust the data, which eventually resulted in an indivisible situation. As a result, we set the fin width to 8.3nm. Although the effective channel area of the two devices is not equal overall, the above dimensions are well matched to the actual process, and the deviation in the channel area is only 0.4%, which does not affect the conclusions of this paper.

Comments 2: In Figure 2b, I suggest plotting the normalized current density to effective width, to ensure a fair comparison of current between FinFET and NSFET. Additionally, in Table 3, it would be more standard to display the on-current density and capacitance per unit area to provide clearer insights.

Response 2: We are sorry, but we did not understand your point. Figure 2b shows the current results of FinFET devices under the same simulation settings as the calibrated NSFET devices. Could you please provide more detailed information to guide us on how to make modifications? Thank you very much.

Comments 3: In Figure 3, the magenta curve representing drain height variation is hidden behind the green curve, making it difficult to distinguish the differences. To enhance visibility, I recommend using hollow symbols for the curves to clearly illustrate the variation in IV characteristics.

Response 3: Thank you very much for your suggestion regarding the readability of the image. After our attempts, we found that hollow symbols did not significantly improve the readability of the image. Therefore, we appropriately reduced the number of linear coordinates in the "Both" case so that the pink dots in the background could be displayed, thus increasing the readability of the image. The revised image is shown below. 

Response 7: Thank you for your question. In Reference 13 of this paper, a serious defect is described where an entire electrode is completely missing due to a process error. In fact, the work in this paper is also based on process defects we discovered in actual production. For some reasons, we are unable to provide you with relevant inspection photos. However, according to our relevant inspection data, it is possible for the source/drain height to be reduced to 10% or even more of the original height.

Comments 8: Given that the topic is focused on source-drain height variation, I would suggest providing further analysis on the variability in device and circuit performance due to this variation. For example, how much would the threshold voltage (Vt) sigma change due to height variation? For example, how much does Vt sigma change?

Response 8: The response to this comment is the same as the response to point six. Once again, thank you for your review suggestions.