Low-Power Radix-2² FFT Processor with Hardware-Optimized Fixed-Width Multipliers and Low-Voltage Memory Buffers

Abstract

In this paper, we propose a novel low-power implementation of the radix-2² Fast Fourier Transform (FFT) processor that exploits optimized multiplications and low-voltage memory buffers. The FFT computation requires complex products between input samples and precomputed coefficients, known as twiddle factors, as well as a large number of memory elements to store intermediate signals. To reduce power consumption, we bypass multiplications when twiddle factors are equal to zero or one. Furthermore, we introduce a fixed-width technique that lowers multiplier complexity for non-trivial coefficients by pruning the least significant columns of the partial product matrix and discarding the most significant partial products with low activation probability. To further minimize power consumption, we lower the supply voltage of memory buffers, creating two power domains in the design. Post-synthesis analysis in 28 nm technology shows that the proposed FFT achieves superior SNR and MSE compared to existing implementations, with reductions of 33% in power consumption and 30% in the power-delay product. In an OFDM receiver, the design also achieves optimal bit error rate performance under various levels of channel noise.

1. Introduction

Discrete Fourier Transformation (DFT) is a well-known mathematical operation that finds widespread employment in several digital signal processing algorithms, allowing the elaboration of signals in the frequency domain rather than in the time or spatial domain. Among possible applications, DFT constitutes the core operation in real-time spectrum analysis, video broadcasting, cryptography, mobile digital communication, and neural networks [1,2,3,4,5,6]. For example, the work [3] proposes a cooperation between DFT and Convolutional Neural Networks to enhance speech quality, as well as [4,5] exploit domain transformation to reduce the computational complexity in convolution-based algorithms. Similarly, a DFT with a tunable number of points is proposed in [6], which can define signal bandwidth in LTE and WiMAX communication systems.

The computation of the Fourier transform requires a large number of multipliers. Since these circuits occupy significant silicon area and dissipate considerable power, the hardware implementation of the DFT is particularly challenging. The use of complex arithmetic, necessary to process both the real and imaginary parts of the signals, further increases design complexity. In addition, the memory elements needed to store intermediate signals during the transformation impose a substantial burden on hardware resources due to their large storage requirements. Consequently, developing effective design strategies to mitigate the impact of multipliers and memory on overall hardware performance is essential to satisfy system constraints.

Fast Fourier Transform (FFT) algorithm constitutes a valuable solution to implement DFT in hardware, enabling the computation of an N-point DFT with a set of P-point DFTs, having P < N. Each P-point DFT, featuring feasible hardware complexity, implements the so-called butterfly that constitutes the arithmetic engine of the transformation algorithm [7,8]. Among possible architectures like Multi-path and Single-path Delay Commutators, the Single-path Delay Feedback (SDF) approach is largely preferred for the hardware realization of FFT, as it involves reduced memory, affordable arithmetic structures, and simple data flow [9]. Moreover, selecting the proper butterfly topology is also important to achieve the desired performance, since it determines the number of arithmetic operations and the kind of utilization. For instance, the radix-2 butterfly has a simple architecture, but calls for a large number of multipliers to compute the overall transformation. Additionally, arithmetic circuits involved in the computation are inactive for half the time required to produce the transformed signal, resulting in an inefficient usage of multipliers and adders. Conversely, butterflies with higher radixes employ a lower number of products and also improve the utilization time of arithmetic circuits, but pose at the same time signal congestion issues [10]. Among these, architectures like the radix-2² offer a valid compromise, being able to reduce both the number of multipliers and the routing complexity of the circuit [11,12].

Approximate Computing techniques, which improve performance in computation-intensive systems like digital filters and neural networks [13,14,15], have been recently extended also to the FFT design, providing the option to adopt inexact calculations to reduce power consumption and area occupation [16,17]. Specifically, multipliers mainly benefit from the employment of approximate implementations. For example, the work [18] proposes to downsize multipliers by selecting the most significant parts of the inputs for the product, starting from the leading one bit. At the same time, papers [19,20] simplify the selection scheme, considering only a subset of predefined segments. The paper [20] finds the optimal location for the most significant segments that can minimize the approximation error, while [21] extends the approach to the design of multiply-accumulate units. At the same time, hardware improvements are achieved by following a different approach in [22,23,24,25], where approximate compressors sum up the rows in the partial product matrix (PPM) of the multiplier. As a further example, ref. [26] truncates the least-significant columns of the PPM, while [27,28] exploit encoding techniques to realize multiplications with shift-and-add operations.

Regarding the application of approximate arithmetic circuits in the FFT, the paper [29] exploits inexact Booth multipliers with customized 4-2 compressors for a radix-4 FFT implementation, while [30] investigates the effects of approximate adders like [31,32] on precision and hardware results. The paper [33] devises the usage of multipliers [18,27,28] for a radix-2 butterfly, exploiting dynamic segmentation and approximate encoding, and also proposes a customized architecture in which only a butterfly is shared among several stages of the SDF FFT. In [34], the authors address finite word-length effects on overall precision, proposing an algorithm that defines the bit-width of signals as a function of the SDF stage.

From the memory perspective, designing circuits with high storage capacity while maintaining optimal power and area efficiency requires careful consideration. Static Random-Access Memories (SRAM) represent a common solution for compact memory implementation with favorable hardware characteristics. However, their integration is often challenging due to reliance on technology-dependent macros provided by foundries. Alternatively, several works [35,36,37,38] propose implementing memories using standard cells. In such cases, latches or flip-flops are employed, enabling simpler integration strategies but typically resulting in suboptimal area and power efficiency.

In this paper, we propose a novel approximate radix-2² SDF FFT processor with hardware-efficient multiplications and low-power memory. The computation of the transformed signal requires the multiplication of the input samples and a set of coefficients defined at design time. Moreover, samples computed in the stages of the SDF algorithm need to be continuously stored in memory for subsequent elaborations, leading to high power dissipation. To improve performance, we first introduce a multiplexing scheme that skips multiplication when coefficients are equal to zero or one. This way, the switching activity of signals in multipliers is lowered, leading to a reduction in power dissipation. At the same time, a voltage-scaling approach is exploited to implement memory elements of the circuit with the aim of minimizing their impact on overall performance.

To further reduce power dissipation, we also approximate the design of multipliers, proposing a novel fixed-width technique to perform the product when the coefficients are non-trivial. In our approach, first, an intensive approximation is applied to the least significant part of the multiplier PPM, discarding its columns. Secondly, a finer approximation is used for the most significant part, where only partial products with a low probability of being one are dropped. Additionally, probability information is suitably exploited to find the optimal number of deleted terms in each row of the PPM. Then, two parameters define the multiplier architecture, which are the number of truncated columns and the number of pruned most significant partial products.

It is worth noting that our study is based on a thorough circuit-level analysis and quantitative validation of both the arithmetic and memory sections, enabling the identification of an optimal radix-2² FFT implementation. The proposed techniques—such as multiplier approximation, coefficient skipping, and memory voltage scaling—collectively achieve up to a 33% reduction in power consumption compared to state-of-the-art designs, while preserving high accuracy.

The proposed circuit is synthesized in TSMC 28 nm CMOS technology and compared with state-of-the-art designs in order to highlight accuracy and hardware achievements. Error analyses reveal the possibility of having configurable precision, measured in terms of Signal-to-Noise Ratio (SNR) and Mean Squared Error (MSE), which depends on the number of columns and close-to-zero partial products dropped in the multipliers. Hardware results also show substantial improvements with respect to other implementations (which only approximate arithmetic sections in the FFT, like in [29,33]), offering power saving up to 33%. Investigated FFTs are also employed in an Orthogonal Frequency-Division Multiplexing (OFDM) receiver. Again, results highlight the potential of our proposal, which achieves a valuable bit error rate (BER) under several noise levels.

The paper is organized as follows: Section 2 offers an overview of the radix-2² FFT processors, while Section 3 describes the proposed low-power technique. In Section 4, accuracy and hardware results are shown, as well as the behavior in the OFDM receiver is presented. Section 5 summarizes the main findings, highlighting the trade-off between hardware improvement and precision. Then, Section 6 concludes the paper.

2. Radix-2² FFT Processor

Let us consider the sequence x(n), expressed on N points, and the relative transformation X(k), with n and k lying in the range [0, N − 1]. The N-point DFT of x(n) is computed as follows:

$$X(k)={\displaystyle \sum _{n=0}^{N-1}x(n)·e^{-j2\pi \frac{nk}{N}}} ={\displaystyle \sum _{n=0}^{N-1}x(n)·W_N^{nk}}$$

(1)

with $W_N=e^{-j{\displaystyle \frac{2\pi }{N}}}$ that is the so-called twiddle factor. As observed from (1), the DFT requires N complex multiplications for each value of k. Therefore, the overall number of complex products needed to compute (1) is N², corresponding to 4·N² real multiplications.

To simplify the algorithm, indices n, k can be factorized to reduce the number of products. The type of factorization affects the architecture of the overall circuit, determining the structure of butterfly blocks. In the case of the radix-2² implementations and focusing the attention on a 256-point DFT, considered in the rest of the paper, the following expression is used for indices n, k:

$$n=128n_1+64n_2+n_3, k=k_1+2k_2+4k_3$$

(2)

with n₁, n₂, k₁, k₂ = 0, 1 and n₃, k₃ = 0, 1, …, 63. In general, indices are written in the form n = (N/2)·n₁ + (N/4)·n₂ + n₃ and k = k₁ + 2k₂ + 4k₃, with n₃, k₃ = 0, 1, …, (N/4) − 1.

Substituting the above expression in (1) for N = 256, the DFT becomes

$$X(k)={\displaystyle \sum _{n_3=0}^{63}{\displaystyle \sum _{n_2=0}^1{\displaystyle \sum _{n_1=0}^{1}x(128n_1+64n_2+n_3)}}}·W_{256}^{(128n_1+64n_2+n_3)(k_1+2k_2+4k_3)}$$

(3)

The twiddle factor in (3) can be written as

$$W_{256}^{ (128n_1+64n_2+n_3)(k_1+2k_2+4k_3)}={(-1)}^{n_1{k}_1}{(-j)}^{n_2(k_1+2k_2)}{W}_{256}^{n_3(k_1+2k_2)}{W}_{64}^{n_3{k}_3}$$

(4)

after simple algebra, having considered the following properties:

$$\begin{array}{l}{W}_{256}^{128nk}={(-1)}^{nk}\\ W_{256}^{64nk}={(-j)}^{nk}\\ W_{256}^{Ank}=1\\ W_{256}^{4nk}=W_{64}^{nk}\end{array}$$

(5)

with A that is an integer multiple of N = 256.

Then, substituting (4) in (3) and dividing the summation for indices n₁, n₂, and n₃, the following terms are highlighted:

$$B{F}_1(n_2,n_3)={\displaystyle \sum _{n_1=0}^{1}x(128n_1+64n_2+n_3)·{(-1)}^{n_1{k}_1}}=x(64n_2+n_3)+{(-1)}^{k_1}·x(128+64n_2+n_3)$$

(6)

$$B{F}_2(n_3)={\displaystyle \sum _{n_2=0}^{1}B{F}_1(n_2,n_3)·{(-j)}^{n_2(k_1+2k_2)}}=B{F}_1(0,n_3)+{(-j)}^{k_1+2k_2}·B{F}_1(1,n_3)$$

(7)

$$X(k)={\displaystyle \sum _{n_3=0}^{63}\left(B{F}_2(n_3)·W_{256}^{n_3(k_1+2k_2)}\right)W_{64}^{n_3{k}_3}}$$

(8)

As is observable, the transformed signal X(k) is computed starting from Equations (6) and (7), which determine the butterflies’ architecture in the radix-2² FFT processor. Then, the obtained results are further combined with the twiddle factors as shown in (8). In each butterfly, only complex additions and trivial multiplications are performed. Indeed, the term (−1)^k1 in (6) merely calls for a sign inversion, as well as the term (−j)^k1+2k2 in (7) only demands a swap between real and imaginary parts. On the other hand, products with twiddle factors in (8) are non-trivial, determining the employment of binary multipliers.

In addition, it is worth noting that the summation in (8) corresponds to the 64-point DFT of the quantity BF₂(n₃)·$W_{256}^{n_3(k_1+2k_2)}$. This observation suggests that the DFT can be iteratively factorized until no further decompositions are possible, having 64-point, 16-point, and 4-point DFTs in our case. Twiddle factors for 64 and 16-point DFTs are in the form $W_{64}^{n_3^2(k_1^2+2k_2^2)}$, $W_{16}^{n_3^3(k_1^3+2k_2^3)}$, respectively, with apex ⁱ on factorized indices that indicate the iteration number. At the same time, twiddle factors equal 1 for the 4-point DFT.

The SDF block diagram of the 256-point radix-2² FFT is represented in Figure 1a. As shown, the processor exhibits a modular structure, with each module emerging from a decomposition step. Each factorization requires (i) a complex multiplier (highlighted in red) and (ii) the butterflies BF₁, BF₂, whose inner structure is detailed in Figure 1b,c. As is observable, a simple multiplexer is used to perform trivial multiplications. In addition, ROM memories are also implemented to store non-trivial values of twiddle factors, and a state counter acts as a control circuit to configure butterflies and ROM outputs. Figure 1a also highlights the presence of memory buffers in each module (see the violet dashed box), whose task is to store the samples computed by the butterflies during the transformation.

In the following, the input sequence x(n), the output X(k), and twiddle factors are supposed to be on 16 bits, while the outputs of butterflies BF₁, BF_2, after the first decomposition, are expressed on 17 and 18 bits, respectively, to prevent overflow. Consequently, an 18 × 16 complex multiplier is employed in the first module. Additionally, the output is also truncated to 18 bits to reduce circuit complexity in the following stages. With similar reasoning, we obtain butterfly outputs on 19 and 20 bits, followed by a 20 × 16 multiplier in the second module, and signals on 21 and 22 bits, followed by a 22 × 16 multiplier in the third iteration. Then, three complex multiplications are required for the 256-point radix-2² FFT, corresponding to 12 real multipliers, and large buffers are also required to store computed samples. Since the size of multipliers and buffers is relevant, the adoption of optimal design strategies aimed at reducing area occupation and power consumption is of primary importance to improve circuit performance in the FFT processor.

3. Hardware Implementation

3.1. Multiplication with Trivial Coefficients

To describe the proposed technique, let us focus our attention on the third decomposition step. In this iteration of the algorithm, signals are elaborated as in a 16-point DFT with the following index factorization:

$$n_3=8n_1^3+4n_2^3+n_3^3, k_3=k_1^3+2k_2^3+4k_3^3$$

(9)

where $n_3^3$, $k_3^3$ = 0, 1, 2, 3, and the other terms vary between 0 and 1.

Moreover, let us call BF_2,Re, BF_2,Im the real and the imaginary parts of the signal computed by the butterfly BF_2, so that

$$B{F}_2(n_3^3)=B{F}_{2,\mathrm{Re}}(n_3^3)+jB{F}_{2,\mathrm{Im}}(n_3^3)$$

(10)

and let us consider the Euler representation for $W_{16}^{n_3^3(k_1^3+2k_2^3)}$

$$W_{16}^{n_3^3(k_1^3+2k_2^3)}=e^{-j2\pi {\displaystyle \frac{n_3^3(k_1^3+2k_2^3)}{16}}}=\cos (2\pi {\displaystyle \frac{n_3^3(k_1^3+2k_2^3)}{16}})-j\sin (2\pi {\displaystyle \frac{n_3^3(k_1^3+2k_2^3)}{16}})$$

(11)

Using (10) and (11), the multiplication with the twiddle factor becomes

$$\begin{array}{l}{BF}_2(n_3^3)·W_{16}^{n_3^3(k_1^3+2k_2^3)}=\left({BF}_{2,\mathrm{Re}}(n_3^3)+j{BF}_{2,\mathrm{Im}}(n_3^3)\right)·\left(\cos (2\pi {\displaystyle \frac{n_3^3(k_1^3+2k_2^3)}{16}})-j\sin (2\pi {\displaystyle \frac{n_3^3(k_1^3+2k_2^3)}{16}})\right)=\\ \left({BF}_{2,\mathrm{Re}}(n_3^3)·\cos (2\pi {\displaystyle \frac{n_3^3(k_1^3+2k_2^3)}{16}})+{BF}_{2,\mathrm{Im}}(n_3^3)·\sin (2\pi {\displaystyle \frac{n_3^3(k_1^3+2k_2^3)}{16}})\right)\\ +j\left({BF}_{2,\mathrm{Im}}(n_3^3)·\cos (2\pi {\displaystyle \frac{n_3^3(k_1^3+2k_2^3)}{16}})-{BF}_{2,\mathrm{Re}}(n_3^3)·\sin (2\pi {\displaystyle \frac{n_3^3(k_1^3+2k_2^3)}{16}})\right)\end{array}$$

(12)

The above equation highlights that the butterfly output is multiplied by sine and cosine terms whose arguments are defined by the indices $n_3^3$, $k_1^3$, $k_2^3$.

Table 1. Values of twiddle factor $W_{16}^{n_3^3(k_1^3+2k_2^3)}$ as a function of the ROM address in the 16-point DFT of the third iteration.

ROM Address	${\mathit{n}}_3^3$	${\mathit{k}}_1^3+2{\mathit{k}}_2^3$	$\mathbf{cos}(2\mathit{\pi }\frac{{\mathit{n}}_3^3({\mathit{k}}_1^3+2{\mathit{k}}_2^3)}{16})$	$\mathbf{sin}(2\mathit{\pi }\frac{{\mathit{n}}_3^3({\mathit{k}}_1^3+2{\mathit{k}}_2^3)}{16})$	sk
0	0	0	1	0	0
1	0	1	1	0	0
2	0	2	1	0	0
3	0	3	1	0	0
4	2	0	1	0	0
5	2	1	7.07 × 10−1	−7.07 × 10−1	1
6	2	2	6.12 × 10−17	−9.99 × 10−1	1
7	2	3	−7.07 × 10−1	−7.07 × 10−1	1
8	1	0	1.00 × 10−0	0.00 × 10−0	1
9	1	1	9.24 × 10−1	−3.83 × 10−1	1
10	1	2	7.07 × 10−1	−7.07 × 10−1	1
11	1	3	3.83 × 10−1	−9.24 × 10−1	1
12	3	0	1.00 × 10−0	0.00 × 10−0	1
13	3	1	3.83 × 10−1	−9.24 × 10−1	1
14	3	2	−7.07 × 10−1	−7.07 × 10−1	1
15	3	3	−9.24 × 10−1	3.83 × 10−1	1

shows the real and imaginary parts of $W_{16}^{n_3^3(k_1^3+2k_2^3)}$ stored in the ROM, with sine and cosine values that are represented with two digits after the point for the sake of simplicity. Moreover, indices $n_3^3$, $k_1^3$, $k_2^3$ are also reported for the sake of clarity. As observable, the index $n_3^3$ is zero when the ROM address varies between 0 and 4, determining zero argument for sine and cosine functions (see the table for reference). Accordingly, in such cases real and imaginary parts of the twiddle factor assume values that are one and zero, respectively, calling for five consecutive trivial multiplications.

The above observation suggests (i) skipping the multiplication in the mentioned cases, and (ii) directly selecting the term BF_2,Re for the real part of the product and BF_2,Im for the imaginary part of the product (see also (12)). Similarly, the same approach can be applied to the first and second modules of the SDF, finding that twiddle factors exhibit 65 and 17 trivial values, respectively.

Figure 2 depicts the skipping logic used to perform trivial multiplications. As shown, the ROM is augmented by one bit to output the state flag sk, which allows the identification of trivial products. Specifically, sk is kept low for addresses between 0 and 4, as also indicated in Table 1, whereas it is kept high in the other cases. Then, a couple of multiplexers are suitably configured to output BF_2,Re, BF_2,Im when sk = 0, bypassing multiplications. To reduce the switching activity, AND gates are also employed to hold BF_2,Re, BF_2,Im at zero at the input of the complex multiplication (highlighted in gray), thus lowering the power consumption of multipliers and adders. In relation to this, the ROM content is also modified as shown in Figure 2 to further minimize signal commutations when the circuit enters and exits from the skipping condition. To this aim, we impose that the first values of sine and cosine are equal to the last values stored in the ROM, highlighted in blue in the figure. This way, when the FFT enters the skipping condition, only BF_2,Re, BF_2,Im vary (as they are gated) while sine and cosine terms are kept constant, thus reducing glitches in the multipliers. With a similar approach, remaining values of sine and cosine are set to the first non-trivial values, highlighted in red, so that only BF_2,Re, BF_2,Im vary when the circuit exits from the skipping condition.

3.2. Proposed Fixed-Width Multiplier

Even though the skipping method allows for bypassing multiplications in trivial cases, the number of non-trivial products required to compute the transformed signal is still high and calls for careful analysis. To improve performance in this case, we have adopted a fixed-width design methodology. The structure of the proposed multiplier is depicted in Figure 3, where a 10 × 10 multiplier is taken for reference for the sake of demonstration. As shown, the PPM is divided into two parts, gathering the most significant and the least significant columns, respectively. In the least significant part, we discard the t columns, highlighted in gray, introducing an error in the computation. To recover accuracy, the central partial products of the first preserved column, colored in blue, are double weighted following the correction technique proposed in [26], so that the mean square error of the approximation is minimized.

In the most significant part of the PPM, we follow a finer approach in order to further alleviate hardware burden while preserving acceptable levels of accuracy.

To begin with, it is worth noting that twiddle factor values are defined at design time and that the probability of having a high partial product is computed as follows:

$$P(p_{ih})=P(b_i{w}_h)=P(b_i)·P(w_h)$$

(13)

with b_i that is the i-th bit of the real (or imaginary) part of the signal at the output of the butterflies BF_2, and w_h that is the h-th bit of the real (or imaginary) part of the twiddle factor. Please note that bits b_i and w_h are supposed to be independent in (13). Moreover, let us also consider P(b_i) = 50% for the sake of demonstration. Since twiddle factors are known at design time, we can compute the probability P(w_h) that a generic bit w_h is high. Figure 4 depicts the values of P(w_h) for the sine and cosine components of twiddle factors in the first, second, and third modules.

The differences observed among the probability diagrams in Figure 4a–c arise from the distinct values of the twiddle factors employed in each FFT stage. These coefficients depend on the factorized indices defined by the radix-2² decomposition and therefore vary from one stage to another.

Due to the large number of twiddle factors involved in a 256-point FFT, a purely analytical prediction of these bit probabilities is not straightforward. For this reason, we adopted a simulation-based approach to estimate the probability of each bit being ‘1’. This method is fully justified, as all twiddle factors are known at design time, and it provides the precise information required to identify which partial products in the multipliers’ partial product matrix (PPM) can be safely neglected without significantly affecting accuracy.

The dashed black line highlights the probability level of 50%, taken as a reference. The figure points out that some bits are high with low probability, making room for approximation. For example, bits w₁₃, w₁₀, w₈, w₆, w₅, w₄, w₃, w₂, w₀ of the sine in Figure 4c exhibit P(w_h) less than 40%, with w₀ showing the lowest probability (less than 10%). Supposing to have P(b_j) = 50%, the probability of having b_jw₀ = 1 is lower than 5%. Accordingly, partial products of the kind b_jw₀ can be truncated to gain hardware performance without dramatically degrading the accuracy of results. Similarly, bits w₁₄, w₁₁, w₁₀, w₉, w₈, w₀ of cosine are worth attention, as well as the central bits of sine and cosine in Figure 1a,b.

In our approach, we define the number of truncated partial products as a function of the bit probability P(w_h) to properly balance the trade-off between hardware improvement and multiplier accuracy. The rationale behind our idea is to apply a more aggressive truncation in rows where P(w_h) is lower, and a lighter approximation in rows where P(w_h) is higher. Figure 3 clearly shows the above concept, supposing that P(w₀) < P(w₈) < P(w₃). Here, the row of w₀ exhibits the maximum number of deleted terms (up to 5, depicted in brown), while a lower number of partial products is discarded in the other cases.

Additionally, it is also worth noting that the rows have different weights in the PPM as some of them are left-shifted, as clearly pointed out in Figure 3. Accordingly, the number of pruned terms should be chosen by taking into account the weight assumed by partial products, since it also affects the approximation error.

To define the amount of truncation, we first divide the multiplier rows into three groups based on the weight of their least significant bit (LSB). In the following, we refer to h as the row index, for h = 0, 1,… N_w − 1, with N_w being the number of bits of sine and cosine coefficients. Then, referring to Figure 3, we have that:

(i)

rows for h < 2 and t ≤ h ≤ t + 1 have LSB of weight 2^t;

(ii)

rows for 2 ≤ h < t have LSB of weight is 2^t+1;

(iii)

rows for h > t + 1 the LSB weighs 2^h.

Moreover, the approximation is applied when the probability that the w_h of the partial product is high is lower than a predefined threshold, named P_target in the following.

When m_h is the number of pruned partial products in the h-th row, the approximation error assumes the following expression:

$$e(h)=\left\{\begin{array}{l}{\displaystyle \sum _{i=t}^{t+m_h-1}{b}_i{w}_h{2}^i for h<2 and t\le h \le t+1 }\\ {\displaystyle \sum _{i=t+1}^{t+m_h}{b}_i{w}_h{2}^i for 2\le h<t}\\ {\displaystyle \sum _{i=h}^{h+m_h-1}{b}_i{w}_h{2}^i for h>t+1}\end{array}\right.$$

(14)

while the mean error µ_e(h) is

$${\mu }_e(h)=\left\{\begin{array}{l}E\left[{\displaystyle \sum _{i=t}^{t+m_h-1}{b}_i{w}_h{2}^i}\right] for h<2 and t\le h \le t+1\\ E\left[{\displaystyle \sum _{i=t+1}^{t+m_h}{b}_i{w}_h{2}^i}\right] for 2\le h<t\\ E\left[{\displaystyle \sum _{i=h}^{h+m_h-1}{b}_i{w}_h{2}^i}\right] for h>t+1\end{array}\right.$$

(15)

Assuming that the mean operator E[·] is linear and that b_i, w_h are independent, (15) becomes

$${\mu }_e(h)=\left\{\begin{array}{l}{\displaystyle \sum _{i=t}^{t+m_h-1}E\left[b_i{w}_h\right]2^h} for h<2 and t\le h \le t+1\\ {\displaystyle \sum _{i=t+1}^{t+m_h}E\left[b{f}_{2,i}{w}_j\right]2^i} for 2\le h<t\\ {\displaystyle \sum _{i=j}^{j+m_h-1}E\left[b_i{w}_h\right]2^i} for h>t+1\end{array}\right. =\left\{\begin{array}{l}E\left[b_i\right]E\left[w_h\right]·{\displaystyle \sum _{i=t}^{t+m_h-1}{2}^i} for h<2 and t\le h \le t+1\\ E\left[b_i\right]E\left[w_h\right]·{\displaystyle \sum _{i=t+1}^{t+m_h}{2}^i} for 2\le h<t\\ E\left[b_i\right]E\left[w_h\right]·{\displaystyle \sum _{i=h}^{h+m_h-1}{2}^i} for h>t+1\end{array}\right.$$

(16)

Writing the mean value E[w_j] as follows

$$E\left[w_h\right]=1·P(w_h)+0·(1-P(w_h))=P(w_h)$$

(17)

and using the following relations for the summations (for details refer to the Appendix A)

$$\begin{array}{l}{\displaystyle \sum _{i=t}^{t+m_h-1}{2}^i}=2^{t+m_h}-2^t=\left(2^{m_h}-1\right)·2^t\\ {\displaystyle \sum _{i=t+1}^{t+m_h}{2}^i}=2^{t+m_h+1}-2^{t+1}=\left(2^{m_h}-1\right)·2^{t+1}\\ {\displaystyle \sum _{i=h}^{h+m_h-1}{2}^i=}{2}^{h+m_h}-2^h=\left(2^{m_h}-1\right)·2^h\end{array}$$

(18)

we obtain:

$${\mu }_e(h)==\left\{\begin{array}{l}E\left[b_i\right]P\left(w_h\right)·\left(2^{m_h}-1\right)·2^t for h<2 and t\le h\le t+1\\ E\left[b_i\right]P\left(w_h\right)·\left(2^{m_h}-1\right)·2^{t+1} for 2\le h<t\\ E\left[b_i\right]P\left(w_h\right)·\left(2^{m_h}-1\right)·2^h for h>t+1\end{array} \right.$$

(19)

As highlighted in (19), the committed error depends on both the probability P(w_h) and on the number of truncated terms m_h, as well as on the weight of LSBs, represented by exponential contributions 2^t, 2^t+1, and 2^h.

Let us consider the worst-case scenario in which m partial products are truncated in the h*-th row, exhibiting the highest probability P(w_h*). The mean error for this row is:

$${\mu }_e(h^{*})==\left\{\begin{array}{l}E\left[b_i\right]P_{\max }·\left(2^m-1\right)·2^t for h^{*}<2 and t\le h^{*}\le t+1\\ E\left[b_i\right]P_{\max }·\left(2^m-1\right)·2^{t+1} for 2\le h^{*}<t\\ E\left[b_i\right]P_{\max }·\left(2^m-1\right)·2^{h*} for h^{*}>t+1\end{array}\right.$$

(20)

with P_max = P(w_h*).

To find the values of m_h for other indices, we impose that each row exhibits the same approximation error as a sizing criterion. Therefore, m_h is computed by solving the equality

$${\mu }_e(h)={\mu }_e(h^{*})$$

(21)

for each value of h. It is worth noting that the above equation is solved only for rows where the condition P(w_h) ≤ P_target is verified.

Table 2. Number of pruned partial products m_h as a function of the worst-case row index h* and the generic row index h.

Values of mh	h* < 2 and t ≤ h* < t + 1	2 ≤ h* < t	h* > t + 1
h < 2 and t ≤ h < t + 1	$⌈{\log }_2\left({\displaystyle \frac{P_{\max }}{P(w_h)}}·\left(2^m-1\right)+1\right)⌉$	$⌈{\log }_2\left(2·{\displaystyle \frac{P_{\max }}{P(w_h)}}·\left(2^m-1\right)+1\right)⌉$	$⌈{\log }_2\left(2^{h^{*}-t}·{\displaystyle \frac{P_{\max }}{P(w_h)}}·\left(2^m-1\right)+1\right)⌉$
2 ≤ h < t	$⌈{\log }_2\left({\displaystyle \frac{1}{2}}·{\displaystyle \frac{P_{\max }}{P(w_h)}}·\left(2^m-1\right)+1\right)⌉$	$⌈{\log }_2\left({\displaystyle \frac{P_{\max }}{P(w_h)}}·\left(2^m-1\right)+1\right)⌉$	$⌈{\log }_2\left(2^{h^{*}-t-1}·{\displaystyle \frac{P_{\max }}{P(w_h)}}·\left(2^m-1\right)+1\right)⌉$
h > t + 1	$⌈{\log }_2\left(2^{t-h^{*}}·{\displaystyle \frac{P_{\max }}{P(w_h)}}·\left(2^m-1\right)+1\right)⌉$	$⌈{\log }_2\left(2^{t+1-h^{*}}·{\displaystyle \frac{P_{\max }}{P(w_h)}}·\left(2^m-1\right)+1\right)⌉$	$⌈{\log }_2\left({\displaystyle \frac{P_{\max }}{P(w_h)}}·\left(2^m-1\right)+1\right)⌉$

reports the solution of (21) considering all possible combinations between indices h* and h. As shown, m_h exhibits a logarithmic dependence with respect to the ratio P_max/P(w_j) and the parameter m. In particular, if 2^m is sufficiently larger than one and the rows are in the same group, it is possible to increase m_h of one with respect to m for each doubling of P_max/P(w_h).

3.3. Memory Buffer

Memory buffers also constitute an important part of the SDF FFT processor, being in charge of acquiring the input samples and of storing signals computed by the butterflies. Generally, a first-in first-out topology is adopted for their implementation to make the selection of the stored signal simple, suggesting the employment of shift registers. At the same time, each register, made up of flip-flops in the standard-cell design flow, needs to be written at each clock cycle, thus negatively affecting power dissipation. Furthermore, the demand for large storage capabilities (in the case of our FFT, 256 registers are required to store signals expressed up to 22 bits) also leads to high energy consumption for clock distribution due to high-load capacitances. To reduce the hardware impact of memory buffers, we downscale the supply voltage of shift registers with respect to the arithmetic section of the FFT processor. In addition, level shifters are added in the design to ensure proper data flow between the buffers and the arithmetic circuits, working with the nominal supply voltage.

It is worth noting that voltage scaling integrates well in the context of standard-cell-based design flow, benefiting from the adoption of well-established design methodologies, and is also a suitable candidate to reduce power dissipation in systems exhibiting high-load capacitances (as in the case of clock distribution in memory buffers).

4. Results

4.1. Accuracy Assessment

To verify the accuracy of the proposed FFT processor, we compare the approximate results with the signal transformed through the Matlab R2023b function fft, considering a 256-point random input as a test case, quantized on 16 bits. Circuit-level precision is assessed in terms of Signal-to-Noise ratio (SNR) and Mean Squared Error (MSE) between the transformed signals.

Figure 5 depicts the accuracy performance of the proposed FFT with respect to the number of truncated columns in the first, second, and third multipliers, indicated as t₁, t₂, and t₃ respectively, and of the pruned partial products, computed in dependence on parameters m₁, m₂, m₃, defined starting from the worst-case probability of having high bits in twiddle factors. In Figure 5a, only multipliers in the first module are approximated, while in Figure 5b, 5c we apply our fixed-width technique also to multipliers of the second and third modules, respectively. As shown, FFT accuracy depends on both t and m parameters, exhibiting a worsening of performance when the number of pruned terms increases. For example, in Figure 5a, SNR clearly decreases for t₁ that ranges from 10 to 15, as well as a reduction in precision is registered for m₁ approaching 10. Accuracy due to approximation in the second multiplier worsens for increasing values of t₂ and m₂. Moreover, the precision is also affected by the approximation of previous stages. Indeed, SNR is able to approach 60 dB if the first multiplier is approximated with t₁ = 15 and m₁ = 3, whereas it is limited to 44 dB if m₁ = 7. Similar considerations are also valid for the approximation in the multipliers of the third module, as clearly shown in Figure 5c. On the basis of the above analysis, we truncate t = 10, 13, and 15 least significant columns in all multipliers, while the following combinations of m parameters are chosen, which lead to an advantageous trade-off between hardware results and precision: (i) m₁ = 3, m₂ = 2, m₃ = 3, (ii) m₁ = 6, m₂ = 3, m₃ = 4, (iii) m₁ = 7, m₂ = 4, m₃ = 5, (iv) m₁ = 8, m₂ = 8, m₃ = 10. We refer to these implementations as:

• A-FFT10_3,2,3, A-FFT10_6,3,4, A-FFT10_7,4,5, A-FFT10_8,8,10;
• A-FFT13_3,2,3 A-FFT13_6,3,4, A-FFT13_7,4,5, A-FFT13_8,8,10;
• A-FFT15_3,2,3, A-FFT15_6,3,4, A-FFT15_7,4,5 A-FFT15_8,8,10.

It is worth noting that other possible combinations of t, m parameters can be selected so that the most appropriate accuracy and hardware performance, tailored to the target application constraints, can be achieved.

For the sake of comparison, we also follow the approach of [33], investigating the effects of approximate multipliers described in [18,27,28] for the computation of the transformed signal. In [27], shift-and-add operations are exploited to compute the product, and the sign inversion of the multiplicands, required in signed arithmetic, is computed both through a two’s-complement operation (SRoBA version of the multiplier) and a one’s-complement operation (ASRoBA version of the multiplier). Also [28], referred to as LoBA in the following, exploits signal recoding followed by truncation to reduce hardware complexity, while [18], named DRUM, applies a dynamic segmentation on inputs in order to multiply only their most significant parts. In this analysis, we consider segments expressed on 6, 7, and 8 bits, having the implementations DRUM₆, DRUM₇, and DRUM₈. The static segmented approach of [19] is also investigated, having 14 × 8 and 14 × 12 multipliers (named SSM_14,8 and SSM_14,12, respectively). In this case, twiddle factors are expressed on 8 and 12 bits. Finally, multipliers with the approximate compressors of [22,23] are also considered for the FFT, named C4/2 Ahma and C4/2 Momeni, as well as the design implementing the Booth multiplier of [29], referred to as FFT-cmplx4 in the following.

Table 3. Accuracy and hardware comparison between the proposed FFT processors and the state-of-the-art designs.

FFT Implementation	SNR [dB]	MSE	Delay [ns]	Area [mm2]	Area Saving [%]	Power [mW]	Power Saving [%]
Standard	66.2	4.13 × 10−5	5.16	0.0343	-	8.53	-
SRoBA [27,33]	26.3	4.03 × 10−1	9.02	0.0303	−11.6	7.24	−15.1
ASRoBA [27,33]	26.3	4.04 × 10−1	9.14	0.0295	−14.1	6.88	−19.4
LOBA0_4 [28,33]	12.1	1.05 × 10+1	6.88	0.0270	−21.3	6.43	−24.6
AFFT-cmplx4 [29]	64.8	5.61 × 10−5	5.20	0.0310	−9.6	8.33	−2.3
DRUM6 [18,33]	29.4	1.97 × 10−1	7.83	0.0279	−18.6	7.18	−15.8
DRUM7 [18,33]	35.8	4.56 × 10−2	8.07	0.0286	−16.5	7.64	−10.4
DRUM8 [18,33]	41.5	1.21 × 10−2	8.04	0.0292	−14.7	8.15	−4.5
SSM14,8 [19]	35.5	4.85 × 10−2	7.18	0.0280	−18.4	7.08	−17.0
SSM14,12 [19]	51.8	1.12 × 10−3	7.44	0.0295	−13.9	7.51	−12.0
Comp4/2 Ahma [23]	55.2	5.16 × 10−4	5.10	0.0321	−6.5	7.90	−7.4
Comp4/2 Momeni [22]	55.2	5.11 × 10−4	5.20	0.0326	−4.9	8.14	−4.5
A-FFT153,2,3	57.1	3.29 × 10−4	5.21	0.0326	−5.0	5.82	−31.8
A-FFT156,3,4	47.0	3.43 × 10−3	5.20	0.0324	−5.6	5.77	−32.3
A-FFT157,4,5	42.1	1.05 × 10−2	5.21	0.0323	−5.9	5.74	−32.7
A-FFT158,8,10	24.6	5.87 × 10−1	4.79	0.0319	−7.1	5.68	−33.4
A-FFT133,2,3	64.7	5.81 × 10−5	5.20	0.0336	−2.2	6.01	−29.5
A-FFT136,3,4	54.7	5.75 × 10−4	5.20	0.0333	−2.9	5.96	−30.1
A-FFT137,4,5	50.8	1.42 × 10−3	5.20	0.0332	−3.2	5.95	−30.3
A-FFT138,8,10	36.3	4.00 × 10−2	5.20	0.0327	−4.6	5.83	−31.7
A-FFT103,2,3	66.2	4.13 × 10−5	5.32	0.0346	+1.0	6.20	−27.3
A-FFT106,3,4	65.4	4.94 × 10−5	5.33	0.0344	+0.4	6.15	−27.9
A-FFT107,4,5	63.8	7.16 × 10−5	5.34	0.0343	+0.0	6.14	−28.0
A-FFT108,8,10	54.2	6.46 × 10−4	5.20	0.0337	−1.8	6.03	−29.4

shows the precision results of the investigated FFT processors. The accuracy of the proposed circuits depends on the number of terms truncated in both the most significant and less significant parts of the PPM. For example, for t = 15, the SNR varies from 24 dB (case A-FFT15_8,8,10) to 57 dB (case A-FFT15_3,2,3), determining an improvement as the number of dropped partial products lowers in the most significant part. Similarly, the parameter t affects error metrics, determining the best accuracy with the implementation of A-FFT10. The MSE follows a similar behavior, improving up to an order of magnitude if the number of truncated terms is reduced.

FFT with C4/2 Momeni [22] is able to achieve similar performance, registering SNR of 55 dB, whereas FFT-cmplx4 [29] is the only one able to offer SNR larger than 60 dB and MSE around 5 × 10⁻⁵. Other implementations have lower precision. Implementations with DRUM and SSM exhibit a remarkable dependence of the accuracy on the segmentation scheme, showing SNR that varies in the ranges 30−42 dB and 36−52 dB, respectively. At the same time, the worst performance is achieved by SRoBA, ASRoBA, and LoBA, whose values of SNR and MSE are limited to 26 dB and 1.05 × 10⁻¹.

4.2. Hardware Results

To verify the hardware performance of the investigated circuits, we synthesize the FFT processors in TSMC 28 nm CMOS technology using Cadence Genus 18.13, with a clock frequency of 100 MHz and standard cells with nominal threshold voltage. The arithmetic sections of the proposed FFT are powered with a power supply of 0.9 V, while register buffers are supplied at 0.8 V. To this aim, we use the Common Power Format (CPF) file to define power domain directives and to add level shifters, chosen from the standard cells. The other implementations, which do not exploit power-scaling techniques for memory sections, are synthesized with a supply voltage of 0.9 V. Area occupation and critical path delay, assessed among register-to-register paths, are reported from post-synthesis analyses. Power consumption is computed through post-synthesis simulations as well, considering a 16-bit complex random noise as input. Here, the Standard Delay Format (SDF) file annotates the path delays, while the switching activity is registered through the Toggle Count Format (TCF) file. For this analysis, the standard implementation of the radix-2² processor, which exploits exact multipliers and a unique voltage domain, is taken for reference to compute area, power, and delay performance of the proposed and state-of-the-art designs.

As shown in Table 3, area reduction ranges between 2% and 7% with the implementations A-FFT13 and A-FFT15, whereas a negligible worsening is registered with A-FFT10. This behavior results from the balance between the fixed-width approach, which downsizes the multipliers, and the introduction of the skipping logic, managing trivial multiplications. Additionally, the level shifters lead to an area overhead.

Similarly, slight area improvements are achieved with C4/2 Ahma [23] and C4/2 Momeni [22], while the employment of Booth multipliers leads to higher reductions (9.6%). The best results are achieved using segmentation techniques and input recoding. Specifically, the area improves more than 18% with DRUM₆ [18] and SSM_14,8 [19]. On the other hand, our FFT and designs exploiting [22,23,29] offer critical path delays very close to the standard implementation, whereas other circuits exhibit lower performance. From a power perspective, our FFT is the only one able to overcome 30% of energy reduction, with A-FFT15_8,8,10 that achieved an improvement of about 33%. Power reduction registered with approximate compressors [22,23] and AFFT-cmplx4 [29] is minimal, whereas, among the other implementations, only LoBA [28] is able to approach an improvement of 21%.

4.3. Performance in OFDM Receiver

In addition to the circuit-level evaluation, we further validated the proposed FFT processor in a practical communication scenario. Specifically, this section presents its integration within an Orthogonal Frequency-Division Multiplexing (OFDM) receiver, serving as a system-level case study. This second analysis complements the post-synthesis results by demonstrating that the proposed low-power architecture maintains excellent bit error rate (BER) performance under various channel noise conditions, thereby confirming its applicability and reliability in real-world communication environments.

In telecommunication, Orthogonal Frequency Division Multiplexing (OFDM) is a technique widely employed for data transmission and reception, which allows for achieving high bit rates with optimal bandwidth occupation. Among different advantages, OFDM is resilient to inter-symbol interference and path fading, becoming one of the best choices for effective communication in modern transceivers. In the OFDM approach, the transmitted information is allocated to different subcarriers. Then, the receiver finds the subcarriers’ content in order to recover the desired data. Figure 6 shows a simplified block diagram representing the transmitter, the receiver, and the communication channel, modeled with Additive White Gaussian Noise. As shown, the direct and inverse Fourier transformations occupy a central role in the definition of the OFDM signal. In the transmitter, the bitstream is mapped through a digital modulation, like the Quadrature Amplitude Modulation (QAM) of Figure 6. Then, each symbol obtained from the digital modulation is placed on a subcarrier and transformed into the time domain by means of the inverse FFT (IFFT). At the same time, the FFT allows for finding the content of subcarriers in the receiver. Then, a demodulator rebuilds the bitstream starting from the received samples.

In this analysis, we studied the performance of an OFDM receiver when the investigated FFTs are employed to recover the subcarriers’ content. In this trial, the “Cameraman” image is transmitted, mapping the bitstream on a 64-QAM and distributing the obtained symbols on 208 subcarriers. The Bit Error Rate (BER), defined as the ratio between the number of incorrect bits after reception and the overall number of transmitted bits, is computed as an accuracy metric. Furthermore, several levels of channel noise are considered for our analysis, so that the OFDM signal features an SNR at the input of the receiver that ranges from 0 dB to 25 dB. Figure 7 depicts the behavior of BER, comparing results obtained with the standard and the proposed FFTs. As shown, BER is practically the same when the image is transmitted for SNR lower than 15 dB, as the channel noise mainly affects the accuracy of reception. If the SNR is larger than 15 dB, the precision changes depending on the amount of approximation. Specifically, the choice of m parameters has a large impact on the A-FFT15 architecture. For instance, the BER achieved with A-FFT15_3,2,3 is very close to the standard FFT in the whole range of SNR since only a few partial products are dropped, whereas other implementations exhibit performance limited between 5 × 10⁻¹ and 5 × 10⁻³. Conversely, better results are achieved with A-FFT13 and A-FFT10, highlighting a lower impact of m parameters on the quality of reception.

Table 4. Bit Error Rate performance obtained with FFT computed implementing approximate multipliers.

FFT Implementation	Channel SNR
	6 dB	12 dB	18 dB	20 dB	22 dB	24 dB	25 dB
Standard	2.22 × 10−1	1.03 × 10−1	2.01 × 10−2	6.75 × 10−3	1.22 × 10−3	1.01 × 10−4	1.71 × 10−5
SRoBA [27,33]	2.23 × 10−1	1.06 × 10−1	2.55 × 10−2	1.12 × 10−2	3.93 × 10−3	1.30 × 10−3	7.40 × 10−4
ASRoBA [27,33]	2.23 × 10−1	1.06 × 10−1	2.55 × 10−2	1.12 × 10−2	3.92 × 10−3	1.31 × 10−3	7.46 × 10−4
LOBA [28,33]	2.55 × 10−1	1.94 × 10−1	1.81 × 10−1	1.80 × 10−1	1.81 × 10−1	1.80 × 10−1	1.80 × 10−1
AFFT-cmplx4 [29]	2.22 × 10−1	1.03 × 10−1	2.02 × 10−2	6.72 × 10−3	1.24 × 10−3	1.01 × 10−4	1.71 × 10−5
DRUM6 [18,33]	2.24 × 10−1	1.07 × 10−1	2.43 × 10−2	9.82 × 10−3	2.73 × 10−3	5.56 × 10−4	2.23 × 10−4
DRUM7 [18,33]	2.23 × 10−1	1.05 × 10−1	2.14 × 10−2	7.50 × 10−3	1.58 × 10−3	1.73 × 10−4	3.81 × 10−5
DRUM8 [18,33]	2.23 × 10−1	1.04 × 10−1	2.06 × 10−2	6.90 × 10−3	1.29 × 10−3	1.22 × 10−4	2.09 × 10−5
SSM14,8 [19]	2.23 × 10−1	1.05 × 10−1	2.15 × 10−2	7.54 × 10−3	1.56 × 10−3	1.73 × 10−4	3.43 × 10−5
SSM14,12 [19]	2.22 × 10−1	1.03 × 10−1	2.02 × 10−2	6.87 × 10−3	1.27 × 10−3	1.10 × 10−4	1.71 × 10−5
C4/2 Ahma [23]	2.22 × 10−1	1.03 × 10−1	2.07 × 10−2	7.17 × 10−3	1.43 × 10−3	1.83 × 10−4	4.76 × 10−5
C4/2 Momeni [22]	2.22 × 10−1	1.03 × 10−1	2.07 × 10−2	7.17 × 10−3	1.44 × 10−3	1.85 × 10−4	4.76 × 10−5
A-FFT153,2,3	2.23 × 10−1	1.04 × 10−1	2.11 × 10−2	7.31 × 10−3	1.51 × 10−3	2.09 × 10−4	4.76 × 10−5
A-FFT156,3,4	2.24 × 10−1	1.08 × 10−1	2.92 × 10−2	1.48 × 10−2	6.70 × 10−3	3.26 × 10−3	2.18 × 10−3
A-FFT157,4,5	2.28 × 10−1	1.17 × 10−1	4.74 × 10−2	3.41 × 10−2	2.55 × 10−2	2.03 × 10−2	1.86 × 10−2
A-FFT158,8,10	3.28 × 10−1	3.02 × 10−1	2.92 × 10−1	2.91 × 10−1	2.90 × 10−1	2.90 × 10−1	2.89 × 10−1
A-FFT133,2,3	2.22 × 10−1	1.03 × 10−1	2.03 × 10−2	6.80 × 10−3	1.23 × 10−3	1.14 × 10−4	1.71 × 10−5
A-FFT136,3,4	2.23 × 10−1	1.04 × 10−1	2.14 × 10−2	7.76 × 10−3	1.73 × 10−3	2.78 × 10−4	6.66 × 10−5
A-FFT137,4,5	2.23 × 10−1	1.05 × 10−1	2.38 × 10−2	9.61 × 10−3	2.89 × 10−3	7.37 × 10−4	3.20 × 10−4
A-FFT138,8,10	2.42 × 10−1	1.52 × 10−1	1.07 × 10−1	9.90 × 10−2	9.44 × 10−2	9.12 × 10−2	9.01 × 10−2
A-FFT103,2,3	2.22 × 10−1	1.03 × 10−1	2.01 × 10−2	6.76 × 10−3	1.22 × 10−3	9.71 × 10−5	1.71 × 10−5
A-FFT106,3,4	2.22 × 10−1	1.03 × 10−1	2.02 × 10−2	6.79 × 10−3	1.23 × 10−3	1.08 × 10−4	2.09 × 10−5
A-FFT107,4,5	2.23 × 10−1	1.03 × 10−1	2.02 × 10−2	6.82 × 10−3	1.25 × 10−3	1.14 × 10−4	2.28 × 10−5
A-FFT108,8,10	2.23 × 10−1	1.04 × 10−1	2.27 × 10−2	8.57 × 10−3	2.15 × 10−3	3.77 × 10−4	1.29 × 10−4

reports BER values also registered with the other implementations. Again, accuracy exhibits negligible improvements for small values of SNR, whereas larger differences are registered for SNR approaching 25 dB. Among different circuits, AFFT-cmplx4 [29] and SSM_14,12 [19] are the only ones able to achieve precision equal to the standard case. Designs with C4/2 Ahma [23] and C4/2 Momeni [22] also offer remarkable results, achieving BER similar to A-FFT15_3,2,3, while SRoBA and ASRoBA [27] perform in the middle, offering BER of 7.4 × 10⁻⁴. On the other hand, LoBA [28] has the worst performance, with BER around 10⁻¹. Figure 8 represents the QAM constellation obtained after the reception of the image for A-FFT15_3,2,3 and ASRoBA [27] in the case SNR = 25 dB. The constellation points are clearly distinguishable in the case of A-FFT15_,2,3 (see Figure 8a), whereas the plot for ASRoBA [27] shows a higher level of noise (see Figure 8b). This behavior is further confirmed in Figure 9, depicting the Cameraman images after the reception. Indeed, the image rebuilt with ASRoBA [27] exhibits visible differences with respect to the original case (see the white dots spread in the background). Conversely, results obtained with A-FFT15_3,2,3 are practically unchanged with respect to the original image, as also indicated by the higher value of BER.

5. Discussion

As shown in the previous sections, the proposed FFT processor is able to offer a wide range of precision depending on the choice of the approximation parameters t and m. Indeed, as also shown in Figure 5 and Table 2, increasing the number of truncated terms in the PPM of multipliers leads to a worsening of accuracy. Additionally, the additive logic used to handle the skipping technique and cross-power domain appears to be compensated by the fixed-width approach, used to approximate multipliers. Accordingly, a consistent reduction in power is registered, with implementation A-FFT15_8,8,10 that approaches the best energy improvement (−33%), while area improvement is limited to 7%. Critical path delay also exhibits acceptable results, featuring only a slight worsening of performance with respect to the standard FFT.

Similarly, implementations obtained with C4/2 Ahma [23], C4/2 Momeni [22] and approximate Booth multipliers [29] are able to achieve high accuracy. Here, only the least significant part of the multiplier PPM is approximated, whereas no error is introduced in the most significant part. On the other hand, the high precision is achieved at the cost of hardware performance, as demonstrated by the limited power saving (up to 7.4%). In the case of segmented multipliers like DRUM and SSM, the FFT accuracy strongly depends on segment bit-width, having an SNR gap of 15 dB passing from SSM1_4,8 to SSM_14,12. Although power and area reduction are consistent, the critical path delay is almost limited due to the logic used for the input segment selection and for the bit-width extension of the result. Similar reasoning is also valid for SRoBA, ASRoBA, and LoBA, as the recoding technique requires additional shifters at the input and the output of the multipliers. To put results in perspective, Figure 10 depicts the power-delay-product (PDP) and the area-delay-product (ADP) registered for the investigated FFT processors; the blue bars represent state-of-the-art architecture, while red, green, and purple bars correspond to the proposed A-FFT15, A-FFT13, and A-FFT10 architectures, respectively, each configured with different m values, shown on the x-axis. The black dashed line highlights the PDP and ADP levels of the standard implementation. As shown, only the proposed FFTs achieve remarkable improvements in PDP (in the order of 30%). PDP reduction is negligible in the case of C4/2 Ahma [23], C4/2 Momeni [22], and AFFT-cmplx4 [29], whereas a clear worsening is registered with the other implementations, mainly due to the larger critical path delay. The proposed A-FFT15 is also the only one able to offer ADP improvement along with C4/2 Ahma [23], C4/2 Momeni [22], and AFFT-cmplx4 [29], registering reductions up to 5%.

Finally, Figure 11 compares accuracy and power behavior with the aim of offering a joint assessment between hardware performance and precision of calculations. Implementations close to the top-right corner of the figure exhibit the higher SNR with the higher power reduction. Performance of A-FFT10, A-FFT13, and A-FFT15 implementations is highlighted by the dotted lines. As shown, the proposed designs offer the best power-accuracy trade-off in all cases, allowing the possibility to achieve the largest power saving in a wide range of accuracy.

6. Conclusions

In this paper, we propose a novel low-power, hardware-efficient design for the SDF radix-2² FFT processor exploiting approximate multiplication and voltage scaling. To save power consumption, multiplications are skipped when twiddle factors exhibit trivial values, and a suitable gating on the signals is also applied to reduce the switching activity of the circuit. Additionally, the ROM content is suitably modified to minimize the propagation of glitches when the circuit crosses the skipping condition. At the same time, a novel fixed-width technique is proposed to further alleviate hardware burden by (i) discarding the columns of the least significant part of the PPM and (ii) pruning a selected number of partial product terms in the most significant part. In the latter case, the probability of each partial product being high is exploited to identify and remove terms that are often zero, as they weakly affect the FFT computation. The number of negligible partial products is then determined so as to equally distribute the approximation error among all PPM rows, achieving an optimal balance between hardware simplification and accuracy of results. Finally, memory buffers, required to store samples processed by butterflies, are realized in a separate power domain with a lower supply voltage for further improvements.

Accuracy analyses revealed that the proposed approximate FFT is able to span a wide range of values of SNR and MSE depending on the choice of truncation parameters, being competitive with the investigated implementations. The adoption of skip-and-approximate multiplications, suitably customized on features of twiddle factors, and the design of optimized memory buffers led to power reductions superior to other implementations (up to 33%), which basically exploit general-purpose approximate multipliers taken from literature. Optimal results are also achieved in terms of PDP and ADP, exhibiting the best PDP improvements and competitive ADP behavior. The proposed design was validated through a system-level study within an OFDM receiver, showing that power improvements are achieved without degrading communication performance, as evidenced by the near-optimal BER across different channel SNRs.

Future research will be directed toward improving the area performance of the circuit while preserving high power reductions and accuracy capabilities.