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Review Reports

Electronics2025, 14(20), 4008;https://doi.org/10.3390/electronics14204008 
(registering DOI)
by
  • Thi Viet Ha Nguyen*,† and
  • Cong-Kha Pham

Reviewer 1: Anonymous Reviewer 2: Anonymous Reviewer 3: Baoqiang Liu

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

This manuscript presents a dual-mode PLL able to first operate in large-bandwidth integer-N mode, to attain fast lock acquisition, and then transition to narrow-bandwidth fractional-N mode to achieve high resolution and noise optimization. These features are enabled by the use of a reconfigurable loop filter, whose operation mode is determined based on detected phase errors, and of a novel adaptive digital noise filter. The proposed 180-nm CMOS design achieves -119 dBc/Hz in-band phase noise with 13 mW power consumption. The authors are invited to address the following points to improve quality of their manuscript in view of possible publication.

  1. The achieved frequency range should be mentioned in the abstract.
  2. The noise filter architecture shown in fig. 8 should be more extensively discussed and compared with alternative circuit implementations.
  3. Concerning the VCO design (sect. 3.5), the authors could briefly discuss alternative solutions, such as relaxation oscillators (doi: 10.3390/electronics11111794, doi: 10.3390/electronics13173511) and motivate the benefits of their choice of using a ring oscillator.
  4. The authors are advised to mention in the abstract that experimentally measured results are included in this paper, as this strengthens their proposed work.
  5. If possible, the authors might provide statistics of their circuit performances evaluated from measurements across various chip samples. In addition, sensitivity to Vdd variations and temperature could also be interesting to report.

Author Response

  1. Reviewer #1

1.1. Concern #1

The achieved frequency range should be mentioned in the abstract.

Author action: Thank you for your valuable feedback. We have revised the Abstract to explicitly state the achieved tuning range (Abstract, lines 12 “Operating frequency range at 2.9-3.2 GHz....”)

 

1.2. Concern #2

The noise filter architecture shown in fig. 8 should be more extensively discussed and compared with alternative circuit implementations.

Author response: Thank you for this suggestion. We have added comparative analysis with alternative noise filtering implementations to better justify our design choices.

Author action: We have expanded the noise filter discussion (lines 321-333 in Section 3.3.2) to include quantitative comparison with three alternative approaches: passive LC filters, purely digital filters, and Gm-C filters. The added content explains why our hybrid gyrator-based architecture provides the best trade-off between area (<0.01 mm²), suppression depth (>30 dB), power efficiency, and tunability for our application. This comparison clarifies the technical advantages of the proposed solution over conventional implementations.

1.3. Concern #3

Concerning the VCO design (sect. 3.5), the authors could briefly discuss alternative solutions, such as relaxation oscillators (doi: 10.3390/electronics11111794, doi: 10.3390/electronics13173511) and motivate the benefits of their choice of using a ring oscillator.

Author response: Thank you for this suggestion. We have added discussion of alternative VCO topologies to better motivate our design choice.

Author action: We have added a paragraph at the beginning of Section 3.5 (lines 367-376) that briefly compares ring oscillators with relaxation oscillators and LC-tank VCOs. The discussion includes the suggested references on relaxation oscillators and explains why a ring oscillator was chosen for our application: compact area (<0.001 mm²), wide tuning range, and process compatibility. We acknowledge the phase noise trade-off while demonstrating that our bias-controlled implementation achieves sufficient performance for IoT and wireless applications through careful circuit design.

1.4. Concern #4

The authors are advised to mention in the abstract that experimentally measured results are included in this paper, as this strengthens their proposed work.

Author action: Thank you for the suggestion. The Abstract has been revised to explicitly state that the paper includes experimentally measured results. We added: “Operating frequency range at 2.9-3.2 GHz from a 1.8 V supply, the circuit achieves a worst case fractional spur of - 62.7 dBc, which corresponds to a figure of merit (FOM) of -228.8 dB.” that is shown in Section Abstract from line 12 to line 14.

 

1.5. Concern #5

If possible, the authors might provide statistics of their circuit performances evaluated from measurements across various chip samples. In addition, sensitivity to Vdd variations and temperature could also be interesting to report.

Author response: Thank you for this valuable suggestion. We agree that statistical analysis across multiple samples and sensitivity characterization would strengthen the experimental validation.

Author action: We have added measurement statistics from multiple chip samples to Figure 14 (page 14). Additionally, we have included characterization data showing VCO sensitivity to supply voltage variations (VDD = 1.7-1.9 V) and temperature variations (-40°C to +120°C).

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The work on A Dual-Mode Adaptive Bandwidth PLL for Improved Lock Performance is well described with clear problem statement, clear theoretical descriptions, experimental evidences, and readability. The manuscript is technically sound with some minor corrections as follows :

  1. The authors can expand the related work comparison section highlighting the need for the PLL beyond fast-lock/adaptive bandwidth
  2. Clarify VCO trade-offs compared to LC-VCO designs.
  3. Expand application discussion for IoT/ 5G scenarios where dual mode PLL is meaningful. 
  4. Since the technology used is 180 nm and is compared against considerable lower dimension tech, can authors throw some light on how lower dimensions such as 28mm impact the parameters. 
  5. English and presentation is well maintained with minor corrections related to use of articles, such as a, an, the. 

Author Response

  1. Reviewer #2

2.1. Concern #1

The authors can expand the related work comparison section highlighting the need for the PLL beyond fast-lock/adaptive bandwidth.

Author action: Thank you for this suggestion. We have expanded the related work section Introduction (lines 50-57) to clarify the limitations that existing adaptive PLLs still face. Specifically, we discuss two key issues: first, prior dual-mode PLLs use fixed timing for mode transitions without real-time loop feedback, leading to either stability problems or wasted power; second, meeting stringent phase noise requirements (< -105 dBc/Hz at 1 MHz) typically requires oversized loop filters that increase both lock time and area.

2.2. Concern #2

Clarify VCO trade-offs compared to LC-VCO designs.

Author action: Thank you for requesting this clarification. We have added quantitative comparisons between our ring oscillator approach and LC-VCO designs (in Section Introduction, lines 64-68). LC-tank oscillators typically achieve better phase noise (-120 to -125 dBc/Hz at 1 MHz offset for ~5 GHz), but a single differential inductor occupies 0.15-0.25 mm² in modern CMOS processes, which often represents 40-60% of the total PLL area. Additionally, varactor-based tuning limits frequency coverage to around 15-20%. For our target application, we prioritized compact area and wide tuning range over absolute phase noise performance, as our achieved phase noise of -101.5 dBc/Hz still meets the system requirements while enabling significantly smaller silicon footprint and broader frequency coverage.

2.3. Concern #3

Expand application discussion for IoT/ 5G scenarios where dual mode PLL is meaningful.

Author action: Thank you for this comment. We have expanded the application discussion (in Section Introduction, lines 89-96) to better illustrate where dual-mode operation provides practical benefits. For battery-powered IoT devices, we explain how the PLL can quickly lock in wide-band mode to transmit data bursts, then switch to narrow-band mode during idle periods to conserve power and extend battery life. For 5G scenarios, we discuss how dual-mode capability enables agile frequency hopping across multiple bands - using wide-band mode for fast channel switching while maintaining the low phase noise needed for high-order modulations like 256-QAM in narrow-band mode. This addition clarifies how the architecture addresses the conflicting speed and precision requirements in these applications.

2.4. Concern #4

Since the technology used is 180 nm and is compared against considerable lower dimension tech, can authors throw some light on how lower dimensions such as 28mm impact the parameters.

Author action: Thank you for raising this important point. We chose 180 nm technology primarily due to fabrication accessibility and cost constraints for our research. To enable fair comparison with state-of-the-art designs in advanced nodes, we normalized key metrics to 28 nm (in Section 4 Experimental Results, lines 431-435).

2.5. Concern #5

English and presentation is well maintained with minor corrections related to use of articles, such as a, an, the.

Author action: Thank you for your comment. We checked and fixed some errors with as, a, an, the.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

Comments to Author:

  1. In Figures 2 and 3, the notations (N = 4, M = 5, δ = 0.2) are not sufficiently explained in the text. A brief clarification of their physical meaning would improve readability and make the link between figures and equations clearer.
  2. In Section 2.2, Eq. (1) introduces the dual-mode switching formula, but lacks a mathematical derivation for the switching criterion. For instance, how the optimal tsw is determined and how loop stability is ensured should be discussed.
  3. The reconfigurable bandwidth loop filter is described conceptually, but no circuit-level schematic or layout view is provided. Including an implementation diagram would strengthen the technical contribution.
  4. Figure 14 shows the chip micrograph but lacks detailed annotations. It would be helpful to mark the locations of the VCO, loop filter, ISC, and other key blocks.
  5. The number of references is limited and does not fully reflect recent developments in hardware integration methods. For additional background, the authors may consider referring to Handheld Large 2D Array with Azimuthal Planewave and Row-Multiplexed Elevation Beamforming Enabled by local ASIC Electronics, which highlights the importance of local ASIC integration for improving efficiency and scalability.

Author Response

  1. Reviewer #3

3.1. Concern #1

In Figures 2 and 3, the notations (N = 4, M = 5, δ = 0.2) are not sufficiently explained in the text. A brief clarification of their physical meaning would improve readability and make the link between figures and equations clearer.

Author response: Thank you for this comment. We agree that these parameters needed clearer explanation to improve readability and help readers understand the connection between the figures and the underlying circuit operation.

Author action: We have added detailed clarification in the text (lines 128-131 in Section 2.1) explaining the physical meaning of these parameters:

  • N and M are fixed integers in the accumulator-prescaler combination that yields a fractional division ratio of N + κ/M, where κ = 0,1,2,...,M−1 is the channel selection index
  • In the example shown (N = 4, M = 5), the total division ratio is N×M + κ = 21.
  • δ = 0.2 represents the normalized accumulator threshold that controls the prescaler switching behavior, as illustrated in the steady-state voltage waveforms

The revised text now explicitly links these parameters to Figure 2, showing how the accumulator, prescaler, and static divider cooperate to generate the precise output pulse sequence with the required division ratio.

 

3.2. Concern #2

In Section 2.2, Eq. (1) introduces the dual-mode switching formula, but lacks a mathematical derivation for the switching criterion. For instance, how the optimal tsw is determined and how loop stability is ensured should be discussed.

Author action: Thank you for pointing this out. We have added a mathematical derivation for the switching criterion in Section 2.2. Specifically, we now define the switching time tsw​ based on dual thresholds for phase error and frequency error (Eq. 2). We derive a closed-form lower bound for tsw​ (Eq. 4) by analyzing the phase-error envelope during wide-band acquisition for a type-II second-order loop (Eq. 3). To ensure loop stability during transition, we introduce a slow-variation condition (Eq. 5) that prevents jitter peaking by requiring the natural frequency and damping to change gradually relative to the loop dynamics. The derivation shows how loop-filter state continuity and parameter ramping preserve phase margin during mode switching. We believe these additions provide the rigorous mathematical foundation that was missing in the original submission.

 

3.3. Concern #3

The reconfigurable bandwidth loop filter is described conceptually, but no circuit-level schematic or layout view is provided. Including an implementation diagram would strengthen the technical contribution.

Author action: Thank you for this valuable suggestion. We have added a detailed circuit-level schematic of the reconfigurable bandwidth loop filter (Figure 5 in Page 6 in Section 3.1 ) showing the switchable capacitor array and resistor network implementation. The schematic illustrates how the bandwidth switching is achieved through MOS switches controlled by the mode selection signal, along with the specific some circuits used to realize the dual-mode operation.

 

3.4. Concern #4

Figure 14 shows the chip micrograph but lacks detailed annotations. It would be helpful to mark the locations of the VCO, loop filter, ISC, and other key blocks.

Author action: Thank you for this helpful suggestion. We have updated Figure 15 to include detailed annotations marking the locations of key building blocks. These annotations make it easier to identify the physical implementation and relative sizing of each component on the chip.

3.5. Concern #5

The number of references is limited and does not fully reflect recent developments in hardware integration methods. For additional background, the authors may consider referring to Handheld Large 2D Array with Azimuthal Planewave and Row-Multiplexed Elevation Beamforming Enabled by local ASIC Electronics, which highlights the importance of local ASIC integration for improving efficiency and scalability.

Author response: Thank you for this suggestion. We have expanded the introduction to include discussion of ASIC integration strategies and their impact on system-level efficiency.

Author action: We have added a paragraph (lines 83-87 in Section Introduction) discussing how ASIC co-integration of PLLs with signal processing reduces power and area—directly relevant to our target IoT applications. The suggested reference on ASIC integration has been included to provide context on distributed synthesizer design under strict constraints. This addition better connects our circuit-level contributions to p

Author Response File: Author Response.pdf