Output Filtering Capacitor Bank Monitoring for a DC–DC Buck Converter

Abstract

The remote prognostic, diagnosis, and maintenance of electrolytic capacitors are research topics of interest due to their presence in numerous electronic devices and their increased susceptibility to degradation over time. The authors’ focus in this article is on the proposal of a new diagram for monitoring the parameters of the capacitors that compose the filter bank of a DC–DC buck converter by connecting them in parallel. Each capacitor is modeled by an equivalent series R–C circuit composed of an equivalent capacitance and an equivalent series resistance (ESR). The method used allows successive investigation of the three capacitors that compose the bank by triggering discharge/charge sequences, acquiring the voltages at the capacitor terminals, and estimating the time constants of each capacitor using a parameter observer. During the estimation of the parameters of a capacitor, the converter uses the other two capacitors maintained in operation. The monitoring cycle of all capacitors of the bank lasts less than $40 \mathrm{m}\mathrm{s}$, not significantly affecting the operation of the converter. The study undertaken is correlated with the thermal map of the board on which the converter is made. The dispersion of the measured values of the equivalent capacitances is below $0.25\%$, and of the ESR below $2.6\%$. The major advantage of the method is that the monitoring is performed online and in real time.

1. Introduction

The important role of electronic equipment, in particular power electronic converters, requires monitoring the health and condition of the equipment and/or of the corresponding components. This also entails monitoring filter capacitors and converters. Both the diagnosis and prognosis of the condition of capacitors are of interest. The diagnosis signals the failure of a capacitor and, potentially, of the converter. The prognosis provides information about the capacitor’s remaining useful lifetime (RUL) and, implicitly, about the stability of the converter operation [1,2]. As such, the remote prognosis, diagnosis, and maintenance represent a goal for real-world applications [3] that require methods of real-time monitoring capacitors by operating conditions [4], in an online or at least quasi-online regime.

To assess the capacitors’ ability to perform various functions in electronic converters, in particular the filtering function, the most frequently used model is the R–C series model, with R representing the equivalent serial resistance of the capacitor, denoted in the article by $R_{se}$, and C representing its capacitance, denoted by ${ C}_e$. In applications, electrolytic capacitor degradation thresholds are 200% of the R value and/or 80% of the C value compared to the nominal/initial values [5]. Subsequently, the values of R and C should be regarded as diagnostic parameters, either individually or collectively. Many papers focused on monitoring individual capacitors rely on the value of R as a diagnostic parameter. The use of only the value of C as a diagnosis parameter has also been considered in [6,7]. In some cases, such as the case of metalized film capacitors, with the ESR values being very low [8,9], only the value of C is used to monitor the health of capacitors. The literature reports a lot of research that proposes methods for determining capacitor parameters. The main categories of methods are based on the investigation of the current or voltage ripple of the capacitor in steady state operation, on the investigation of induced transient regimes, of capacitor discharge and/or charging, and on the investigation of the capacitor behavior under the injection of external signals [10,11,12].

Depending on the capacitor’s operating mode during the estimation, the estimated values are associated with different ranges of frequencies, which, on the one hand, makes it difficult to compare the methods and on the other hand, requires operations to adapt the estimated values to real-world conditions. Finally, from a practical point of view, online methods applicable in real time that use minimum sensors and that perform the estimation in the shortest time possible are of primary interest.

The estimations of capacitor parameters in power converters are affected by the errors introduced by the methods of acquisition of the measured signals, the estimation methods, and by the failure to meet the validity assumptions of the estimation methods (e.g., the accuracy of modeling/characterization of the components, the constancy of the operating temperature of the converters, etc.). The precision of the estimates also depends on many other factors, mainly on the amplitude and spectrum of the measured signals, the signal-to-noise ratio, and the characteristics of the converter load. It is important to mention that these aspects, although analyzed and discussed in numerous papers, were obtained mainly under laboratory conditions. As we limit ourselves only to the influence of temperature on capacitor behavior, it is obvious that the estimation accuracy of the proposed methods also suffers, because the temperature value cannot be determined exactly [10]. Numerous studies highlight based on experiments that as the capacitor temperature increases, $C_e$ increases and $R_{se}$ decreases. Also, with the increase in the fundamental frequency of the voltage at the capacitor terminals, the frequency characteristics of $C_e$ and $R_{se}$ fall [13]. These variations are synthesized through mathematical models. Regarding applications related to filter capacitors, [14] shows that, until 2018, research was predominantly focused on filters made with a single capacitor. The paper emphasizes that since the capacitors in a bank are not identical, it is necessary to monitor the capacitors of a bank individually and not only the bank. At the same time, [14] mentions that the more sensors are used for monitoring, the more the converter operation is distorted. Subsequent research related to capacitor banks is scarce. The replacement of a single capacitor with capacitor banks in power electronics applications primarily aims to increase the reliability of the capacitive block (arrangement) [15]. However, the article [16] notes that in the field of photovoltaic applications, most of the studies are dedicated to evaluating the reliability of single-capacitor schemes, specifically the one at the DC interface of the PV inverter, based on the research [12,14,17,18,19,20,21,22,23,24].

Table A1. Papers related to capacitor bank.

Paper/Year of Publication	Treated Issue	Complexity/Prototype/Simulation	Capacitors Monitoring	Observations
[17]/2014	Methods for increasing the reliability of capacitors for DC-link applications in power electronic converters	Overview paper	-	- Capacitor banks are treated as a whole - A method for designing capacitor banks to optimize reliability, cost, and size
[18]/2016	Description and classification of methods for monitoring the health of capacitors	Overview paper	-	Data and advanced algorithm-based methods category treats power electronic converters as a black box or semi-black box (can be used for capacitor banks)
[14]/2018	Health monitoring of each capacitor of a bank using Physics of Failure models updated sequentially with Extended Kalman Filter algorithm	- Prototype with experimental results after 400 h of aging - DSP used for acquisition and data processing - No individual sensor for each capacitor needed	Estimates capacity and ESR for each capacitor of a bank based on models and electrical inputs measured with sensors for the entire bank	-
[19]/2019	DC-link capacitors in three-phase pulsewidth modulation ac–dc–ac power converters	A VEN unit is used for each capacitor in the bank.	C and ESR of dc-link capacitors are estimated through VEN units during the discharging process.	A series capacitor bank consisting of several capacitors is employed to sustain the intermediate circuit voltage.
[12]/2020	Health monitoring techniques for capacitors used in power electronics converters	- Overview paper - The monitoring methods mentioned vary in their level of complexity	- Methods for monitoring the parameters of individual capacitors; - Monitoring the equivalent parameters of the capacitor bank as a whole	Considerations about mixed banks containing multiple types of capacitors.
[20]/2022	Design of a Rogowski coil for online monitoring of a single-capacitor in the dc bank.	Complex as Rogowski coils sensor are integrated in PCB and offer small signals.	- Monitoring each capacitor in DC-link bank - Practical performance assessment of the circuit	ESR at high-frequency region as a new aging indicator.
[21]/2022	Quasi off-line monitoring of the time constant for discharging circuit during converter shutdown	- Prototype	Monitoring for DC-link bank capacitors	Optimizing the sampling frequency to reduce noises
[22]/2023	Monitor ESR and C of each capacitor in a dc-link capacitor bank with PCB integrated Rogowski coils as sensors.	Complex as Rogowski coils and other sensors are integrated in the PCB circuit.	- Monitoring individual capacitor in the bank; - After temperature standardization provides monitoring and prediction for each capacitor	- Theoretical analysis, simulation and laboratory experimental setup using a single-phase inverter.
[23]/2023	Monitor capacitor condition in a dc-link of power converters, following active methodology by signal injecting to estimate the ESR and C of a dc-link capacitor.	Complex as it implies signal injection	Monitoring of capacitor DC-link bank as a whole	- Capacitor parameter estimation method comparison from execution time point of view; - Theoretical analysis and microgrid laboratory experimental setup
[24]/2025	High-gain adaptive observer for estimating floating voltages and monitoring capacitors aging in multicell converters	Simulation for 3-cell converter	- Simultaneous estimation of states and parameters in a p-cell converter, - Does not apply to each capacitor of a bank	- Good balance between estimation accuracy and computational feasibility - Needs a high-performance current sensor and sufficiently powerful computing software for commercial implementation

in Appendix A presents a synthesis in the context of these aspects.

Among the capacitor condition monitoring methods, there are also methods that use state observers [25,26,27]. Depending on the case, the observers are associated with the entire output circuit of the converters or only parts of it. In [28], a new type of observer, called a parameter observer (PO), is implemented. Its role is to determine the time constant of the filter capacitor discharge circuits and to calculate, based on their values, the equivalent parameters $C_e$ and $R_{se}$. The adaptation of PO to discharge/charge processes led to the parameter observer on two edges (PO2) [29].

The present paper continues the research from [30] by presenting a possibility of estimating the equivalent parameters of several capacitors connected in parallel to form the output filter of a DC–DC buck converter. From the point of view of the signal profile acquired to estimate the capacitor parameters, the presented diagram corresponds to principle II proposed in [10], i.e., non-periodic charging/discharging large signal. The non-periodic large signals appear in the transient regimes generated by switches that interconnect the basic configuration of the converter with a variable electrical network (VEN). VEN consists of resistors through which the filter capacitor discharges/charges. The acquired signal is the voltage at the evaluated capacitor terminals. The values of the equivalent parameters of each capacitor are obtained by a PO2 implemented on a microcontroller monitoring the corresponding voltage. The experiments were performed on a DC–DC buck–boost converter based on a dedicated integrated circuit (LTC3780). Since the proposed scheme has only the goal of estimating the values of the capacitor parameters, which represents only part of the converter’s maintenance strategy, the microcontroller implicitly also has the task of transmitting the estimated values to the higher level of the implemented maintenance strategy.

The main contribution of the paper consists of the proposed method, namely, the implementation of the monitoring of the parameters of a DC–DC buck converter filter bank capacitors. These differ from the diagrams in [29] by combining the discharge/charge processes from which the equivalent parameters of the bank capacitors result. The consequence was a considerable reduction in the duration of the cycle of estimation of all capacitors. The estimation is performed online, in real time, without the use of sensors. The results of the experiments are discussed in the context of the thermal map of the converter used.

Section 2 briefly presents the theoretical support for calculating the equivalent parameters of the capacitors in the output filter and its implementation method for a DC–DC buck converter. Section 3 details both the circuit used and the experimental results obtained. Section 4 analyzes the experimental results. Section 5, the last one, summarizes the conclusions of the article.

2. Materials and Methods

2.1. The Principle of Estimating the Values of the Equivalent Parameters of a Capacitor Modeled by a Series R–C Circuit

Consider the circuit in Figure 1a with the capacitor initially charged. By selecting the switch position 1 or 2, the capacitor will discharge across the resistors $R_1$ or $R_2$, the discharge circuits having, respectively, the time constants:

$$T_1=\left(R_1+R_{se}\right)·C_e, T_2=\left(R_2+R_{se}\right)·C_e$$

(1)

Considering $T_1$, $T_2$, $R_1\ne R_2$ known, equalities (1) allow the calculation of the equivalent parameters $R_{se}$ and $C_e$. Equation (1) is also valid for the circuit in Figure 1b, in which the capacitor is charged through $R_2$ from a source that supplies the constant DC voltage $v$ and then discharged across $R_1$.

According to [29] ${ T}_1$ and $T_2$ can be estimated in real time from the signals $v_C(t)$ generated during the capacitor discharges and charges using a parameter observer (PO). Denoting by ${\widehat{T}}_1$ and ${\widehat{T}}_2$ the estimates of the time constants, the estimates of the equivalent capacitor parameters are obtained by Formulas (2):

$${\widehat{R}}_{se}={\displaystyle \frac{{\widehat{T}}_2·R_1-{\widehat{T}}_1·R_2}{{\widehat{T}}_1-{\widehat{T}}_2}}, { \widehat{C}}_e={\displaystyle \frac{{\widehat{T}}_1-{\widehat{T}}_2}{R_1-R_2}} .$$

(2)

The principle of estimating the parameters of the filter capacitors of the converter that is the subject of the present study corresponds to the discharge/charge process in Figure 1b. From a systemic point of view, this is a process with a variable structure. The circuit in Figure 1b represents a master system (MS) whose output signal $v_C(t)$ is processed by PO2.

According to Figure 2a, PO2 contains a PO capable of estimating T only for a discharge signal $v_C(t)$, and an adapter (AD). When a discharge process occurs in the MS, the adapter provides the signal $y\left(t\right)=v_C(t)$, and when a charging process occurs, it provides $y\left(t\right)=K-v_C(t)$, where K is the value of the capacitor supply voltage $v(t)=K$, and the limit value $K=\underset{t\to \infty }{\mathit{lim}} v_C(t)$. In Figure 2b, a discharge/charge process, hereafter called a sequence, is shown, which highlights this limit. The adapter switching to one of the two expressions of $y(t)$ is synchronized by an external command with the discharge/charge processes in the MS (see the blue command line in Figure 2a).

PO2 is the second-order discrete-time tracking system (3) that processes the samples $v_C\left[k\right]=v_C(kh)$ of $v_C(t)$ acquired with the sampling step $h$ [4].

$$O2: \left\{\begin{array}{c}\mathrm{I}\mathrm{A}\mathrm{v}\mathrm{S}:\mathrm{y}\left[\mathrm{k}\right]=\left\{\begin{array}{c}{\mathrm{v}}_C\left[\mathrm{k}\right],\hspace{1em}\hspace{0.5em}\mathrm{f}\mathrm{o}\mathrm{r} \mathrm{a} \mathrm{d}\mathrm{i}\mathrm{s}\mathrm{c}\mathrm{h}\mathrm{a}\mathrm{r}\mathrm{g}\mathrm{i}\mathrm{n}\mathrm{g} \mathrm{p}\mathrm{h}\mathrm{a}\mathrm{s}\mathrm{e}\\ \mathrm{K}-{\mathrm{v}}_C\left[\mathrm{k}\right], \mathrm{f}\mathrm{o}\mathrm{r} \mathrm{a} \mathrm{c}\mathrm{h}\mathrm{a}\mathrm{r}\mathrm{g}\mathrm{i}\mathrm{n}\mathrm{g} \mathrm{p}\mathrm{h}\mathrm{a}\mathrm{s}\mathrm{e}\hfill \end{array} ,\right.\hfill \\ \mathrm{P}\mathrm{O}:\left\{\begin{array}{c}\hspace{0.5em}z\left[\mathrm{k}\right]=\ln \left(\mathrm{y}\left[\mathrm{k}\right]\right),\hfill \\ \widehat{\mathrm{z}}\left[\mathrm{k}\right]=\widehat{\mathrm{z}}\left[\mathrm{k}-1\right]+\mathrm{h}·\widehat{\mathrm{c}}\left[\mathrm{k}\right], \hspace{1em}\widehat{\mathrm{z}}\left[0\right]={\widehat{\mathrm{z}}}_{\mathrm{o}},\hfill \\ \hspace{0.5em}\epsilon \left[\mathrm{k}\right]=z\left[\mathrm{k}\right]-\widehat{\mathrm{z}}\left[\mathrm{k}\right],\hfill \\ \hspace{0.5em}\widehat{\mathrm{c}}\left[\mathrm{k}\right]={\mathrm{K}}_{\mathrm{p}}·\left(\mathsf{\epsilon }\left[\mathrm{k}\right]-\mathsf{\epsilon }\left[\mathrm{k}-1\right]\right)+{\mathrm{h}·\mathrm{K}}_{\mathrm{i}}·\mathrm{\epsilon }\left[\mathrm{k}-1\right]+\widehat{\mathrm{c}}\left[\mathrm{k}-1\right], \widehat{\mathrm{c}}\left[0\right]={\widehat{\mathrm{c}}}_{\mathrm{o}},\hfill \\ \hfill \\ \hspace{0.5em}\widehat{T}\left[\mathrm{k}\right]=-{\displaystyle \frac{1}{\widehat{\mathrm{c}}\left[\mathrm{k}\right]}},\hfill \end{array}\right.\end{array}\right.$$

(3)

The parameters $K_p$ and $K_i$ in (3) are calculated with Formulas (4) depending on the length τ of the time interval after which it is desired to reach the tracking regime. In (4), ${\omega }_o$ is chosen so that $\tau ·{\omega }_o\ge 10$.

$$K_p=2·{\omega }_0, K_i={\omega }_0^2$$

(4)

PO2 completes the calculation of the time constant when condition (5) is met and the current value $\widehat{T}\left[\mathrm{k}\right]$ is assigned to the estimated $\widehat{T}$ value. In Equation (5), $k_0$ is the value of k when the calculation is started.

$$\widehat{T}\left[\mathrm{k}\right]\ge \alpha ·\left(k-k_0\right), \alpha =2.5.$$

(5)

In practical applications, the presented principle is implemented by including the $R_1\text{-}{R}_2$ resistors and the switches in a VEN controlled by a microcontroller, able to measure the voltage $v_C(t)$ and run the PO2 algorithm.

2.2. Basic Electrical Diagram for Estimating the Equivalent Parameters of the Capacitors That Make up the Output Filter of a DC–DC Buck Converter

To apply the principle in Figure 2b, we propose the diagram in Figure 3. It can be extended to banks with more than three capacitors. The diagram allows for estimating the equivalent parameters $C_{ei}$, $R_{sei}$, $i=\overline{1,3}$ of the parallel-connected capacitor bank, Capacitor 1-Capacitor 2-Capacitor 3, of a buck DC–DC converter. The $T_f$ terminal is connected to the converter. The stabilized voltage source LDO provides the voltage $v$. The microcontroller measures the voltages $v_{Ci}$ at the terminals ➀, ➁, ➂, implements PO2 and controls the 9 switches sw11, …, sw33. These operations are symbolized by the notation M-PO2-C.

The monitoring of the three capacitors is performed sequentially by estimating the equivalent parameters during an estimation cycle with duration $t_c$. During the cycle, the parameters of each capacitor are successively evaluated when disconnected from the load, and the output filter is operating with the other two remaining capacitors. The evaluation of the parameters of a capacitor includes a sequence of discharge through R₁/charge through R₂. With the notations in Figure 2, the duration of an estimation sequence $i, i=\overline{1,3}$ is $t_{2_i}-t_{0_i}$, and the duration of a cycle is $t_c={\sum }_{i=1}^3\left(t_{2_i}-t_{0_i}\right)+2∆$, where ∆ is the time interval between two consecutive sequences.

To reduce estimation errors, the sizing of the resistor pair $(R_1,R_2)$ in the VEN composition must comply with the following requirements [30]: (i) the value of the ratios $R_{sei}/R_2$, $i=\overline{1,3}$ should be as close as possible to 1; and (ii) $R_1\gg R_2$. At the same time, the charging time interval must allow, together with the sampling rate, for obtaining a sufficiently large number of samples of the measured voltages $v_{Ci},i=\overline{1,3}$ for PO2 to complete the estimation.

In Figure 4a, the stages of an estimation sequence are detailed at the level of the measured voltage $v_{\mathrm{C}}\left(t\right)$. Stage I corresponds to the normal DC–DC operating mode. In stage II the capacitor is isolated from the DC–DC converter, and its discharge can be triggered resulting in a transient regime during the whole stage. In stage III, the estimation of the time constant $T_1$ is performed. The recharging is triggered in stage IV characterized by a similar transient regime followed by stage V where the estimation of the time constant $T_2$ is processed and finished at its end. In stage VI, the charging continues up to the output voltage level of the converter making it possible to reconnect the capacitor to the bank for filtering and operating in DC–DC mode. Figure 4b shows the states of the switches in the different stages and the way in which one passes from one stage to another through them. The symbols used for the states, the respective commands are 1—closed, 0—open, respectively, ↑—open, ↓—close.

The diagram in Figure 3 extends the list of the four principal diagrams presented in [30], intended for estimating the equivalent parameters associated with the capacitors of the output filter of a converter.

Table 1. Characteristics of some diagrams for estimating the equivalent parameters of filter capacitors in DC–DC buck converters.

Id	Figure 7a, [29]	Figure 7b, [29]	Figure 7c, [29]	Figure 7d, [29]	Figure 3
1.	1	1	1	2	3
2.	1	1	2	2 or 4	2
3.	$C\searrow Load$ $\&$ $C\nearrow R_{VEN}$	$C\searrow Load$ $\&$ $C\nearrow R_{VEN}$	$C\searrow {R1}_{VEN}$ $\&$ $C\searrow {R2}_{VEN}$	$C\searrow {R1}_{VEN}$ $\&$ $C\searrow {R2}_{VEN}$	$C\searrow {R1}_{VEN}$ $\&$ $C\nearrow {R2}_{VEN}$
4.	PO2	PO2	PO	PO	PO2
5.	quasi-online /quasi-online	quasi-online /quasi-online	quasi-online /online	1quasi-online+1online /online	1quasi-online+2online /online (*)
6.	-	-	-	successive	successive
7.	$1\searrow /1\nearrow$	$1\searrow /1\nearrow$	$1\searrow in 2 stages$ or $2\searrow /1\nearrow$	$2\searrow /2\nearrow$	$1\searrow /1\nearrow$ (**)

(*), (**) New features detailed below.

presents a characterization of the four diagrams, as well as the one proposed in this paper (last column). The meaning of the Ids is specified in

Table 2. Meaning of the Ids in Table 1.

Id.	Meaning
1.	Number of capacitors in the output filter.
2.	Number of resistors in the VEN.
3.	The process to which the capacitor is subjected during the estimation.
4.	Type of parameter observer.
5.	Participation of the monitored capacitors in the filtering operation during the estimation/continuity of the load connection to the converter during the estimation.
6.	How to include the capacitors in the bank in the measurement process.
7.	Number of discharges (↘)/charges (↗) supported by the evaluated capacitor during the estimation of the parameters.

. The diagrams are indicated by the number of the figures in [30], respectively, by the figure in this article.

Compared to the most complex solution in [29] (fourth column), the main novelty of the proposed solution, highlighted in the table by the positions marked with (*) and (**), respectively, can be summarized as follows: To monitor the parameters of a capacitor, the scheme in [29] uses two discharge/charge sequences, unlike the scheme in Figure 3, which uses a single sequence. By reducing the number of sequences, the duration of estimating the parameters of a capacitor becomes much shorter than in [29]. Both schemes operate continuously, and the greater the number of capacitors in the bank, the greater the reliability of equivalent bank capacitance.

3. DC–DC Buck Converter Based on the Proposed Principle Diagram

3.1. Implementation

The implementation of the principle diagram in Figure 3 is illustrated by the structure in Figure 5 for a DC–DC buck-boost converter based on the LTC 3780 dedicated integrated circuit working in buck mode [30]. The diagram also includes a microcontroller, a Low Dropout Regulator (LDO), the VEN components (switches sw11, …, sw33 made with MOSFET transistors and resistors R₁ and R₂), and the TS stage, which ensures that the circuit is always started with the full capacity of the bank. The acquisition of the voltages $v_{C1}$, $v_{C2}$ and $v_{C3}$ is performed as in [28], through an application program running with an oversampling period of $2.5 \mathsf{\mu }\mathrm{s}$ and an equivalent sampling period $h = 20 \mathsf{\mu }\mathrm{s}$. The microcontroller also ensures the external transmission of the capacitor parameter values for use in estimating the RUL of the capacitors or the converter.

The LTC 3780 integrated circuit allows three operating modes: buck if $V_{out}\le V_{in}$, boost if $V_{out}\ge V_{in}$, and buck-boost if $V_{out}\cong V_{in}$. In the present case, the evaluation of the capacitors was carried out in buck mode with $V_{in}=9 \mathrm{V}$, respectively, $V_{out}=3.3 \mathrm{V}$. The output filtering bank capacitors consist of three 330 μF/35 V aluminum electrolytic capacitors $Ci,i=\overline{1,3}$ targeted in the evaluation process, and one 100 nF/40 V ceramic capacitor C. The set of MOSFET transistors ensures the necessary switching during the estimation cycle—T-swi1 allows the disconnection/connection of the evaluated capacitor from the converter, T-swi2 ensures the discharge of the capacitor over R₁ = 90 Ω in order to estimate the time constant $T_{i1}$, and T-swi3 charges the capacitor from the LDO through R₂ = 3.3 Ω, in order to estimate the time constant $T_{i2}$. A Teensy 4.0 development board containing an ARM Cortex-M7 microcontroller running at 600 MHz [31] is used as a control, acquisition, processing, and storage data unit. The structure of the program used to monitor the equivalent parameters of the converter output filter capacitors is presented in Figure 6.

The flowchart is organized in two branches: the main flow and the interruption routine. It describes the algorithm for calculating the estimates of the equivalent parameters ${\widehat{C}}_{ei}$ and ${\widehat{R}}_{sei}$, $i=\overline{1,3}$. The calculation is carried out using Equation (2), whose application requires a prior estimate of the time constants ${\widehat{T}}_{1i},i=\overline{1,3}$ for discharging over resistor $R_1$, and ${\widehat{T}}_{2i},i=\overline{1,3}$ for charging through resistor $R_2$. Time constants are estimated using Equation (3). The estimation of a time constant is completed when condition (5) is met. The primary branch of the flowchart starts with setup operations, which involve initializing the microcontroller ports, ADC parameters, and PO2 parameters. This is followed by setting the converter operating mode, initializing the op variable and enabling the interrupt ($400 \mathrm{k}\mathrm{H}\mathrm{z}$) routine where the estimates of ${\widehat{T}}_{1i}$, ${\widehat{T}}_{2i}$ based on algorithm (3) and the calculation of ${\widehat{C}}_{ei}$ și ${\widehat{R}}_{sei}$ are implemented. Following the completion of all calculations, the op variable is reset, and the interrupts are disabled. The interrupt handling routine implements a sequence of estimating the parameters of a capacitor according to Figure 4. The op variable tracks the stages I, II, …, V, with the values $op = 1$, $op = 2$, …, $op = 5$ being updated at the end of each stage. If the value of $op$ is 1 or 3, the switches of the evaluated capacitor are set according to the charge/discharge routine as specified in Figure 4b. In case of $op = 2$ or 4 the PO2 block of the routine is triggered. In this sequence, the $t_{op}$ is appropriately set as $t_2$ and $t_4$, matching the moments $t_0+t_{n1}$ and $t_1+t_{n2}$ in Figure 4. As a result of this sequence, time constants are estimated. The last step of the interruption, $op = 5$, sets the switches to normal operation mode and calculates the equivalent parameters ${\widehat{C}}_{ei}$ and ${\widehat{R}}_{sei}$, based on the time constants. The conditional block in the main branch enables the selection of the number of capacitors to be evaluated. “Choose the capacitors to be evaluated” block allows setting seven configurations for estimation: C1, C2, C3, C1 + C2, …, C1 + C2 + C3.

In case of monitoring cycles for only one or two capacitors, the operator will manage the operations of assigning the values of the variable $op$.

Figure 7 displays the frequency characteristics of the bank capacitors C1, C2, and C3 from Figure 5 obtained with a BK Precision RLC-bridge set for the serial capacitor model. In terms of C(f) and R_s(f) characteristics, some differences can be noticed, while the Z(f) characteristics are almost superimposed.

The experimental board corresponding to the diagram in Figure 5 is shown in Figure 8a. Figure 8b presents a thermal map of the board acquired with a thermal imager Hti-Xintai HT19. To determine the temperature variations in specific areas, the device’s IR ImageTools Software v1.0.0.13 was used.

3.2. Experimental Results

Figure 9a displays an estimation cycle consisting of the three estimation sequences of the capacitor parameters C1, C2, and C3. The cycle duration is $0.037341 \mathrm{s}$. The capacitors are monitored by voltage $v_C$ in the sequence C1-C2-C3. The beginnings of the sequences are noted as $v_{C1}$, $v_{C2}$ and $v_{C3}$. Figure 9b details the results provided by PO2 during the cycle. The values of the time constants are obtained when condition (5) is met. Graphically, this moment corresponds to the abscissa of the intersection point between the half-line with slope 2.5, represented by the dashed line, and the curve ${\widehat{T}}_{jCi}\left(t\right), i=\overline{1,3}, j=\overline{1,2}$ calculated by PO2. It is observed that the extension of the curves calculated for the charging processes, ${\widehat{T}}_{2Ci}\left(t\right), i=\overline{1,3}$, is much smaller than those corresponding to the discharging processes ${\widehat{T}}_{1Ci}\left(t\right), i=\overline{1,3}$.

Table 3. Numerical data corresponding to estimation cycle in Figure 9.

C1	C2	C3
$t_{n1}=0.00024 \mathrm{s}, {∆t}_{dch}=0.01134 \mathrm{s},$$t_{n2}=0.0004 \mathrm{s}$, ${∆v}_{C-dch}$ = [3.266088 V, 2.209389 V]	$t_{n1}=0.00022 \mathrm{s}$$, {∆t}_{dch}$$= 0.01124 \mathrm{s}, t_{n2}=0.00044 \mathrm{s}$, ${∆v}_{C-dch}$ = [3.216883 V, 2.18035 V]	$t_{n1}=0.00018 \mathrm{s}$$, {∆t}_{dch}$$= 0.011 \mathrm{s}, t_{n2}=0.00054 \mathrm{s}$, ${∆v}_{C-dch}$ = [3.216076 V, 2.181156 V]
${∆t}_{ch}$ = 0.00048 s, ${∆v}_{C-ch}$ = [2.628035 V, 2.865994 V]	${∆t}_{ch}$ = 0.00046 s, ${∆v}_{C-ch}$ = [2.606256 V, 2.845828 V]	${∆t}_{ch}$ = 0.000461 s, ${∆v}_{C-ch}$ = [2.619162 V, 2.861154 V]

includes the following parameters for each discharge/charge sequence in Figure 9a: duration t_n1, average duration of the discharge process ${{∆t}_{dch}=t}_1-(t_0+t_{n1})$, duration t_n2, average duration of the charge process ${∆t}_{ch}=t_2-(t_1+t_{n2})$, average intervals of voltage variation $v_C$ during the discharge/charge processes ${∆v}_{C-dch}=\left[v_C(t_0+t_{n1}),v_C(t_1)\right]$, respectively, ${∆v}_{C-ch}=\left[v_C(t_1+t_{n2}),v_C(t_2)\right]$. The notations are those in Figure 4a. The values $t_{n1}$ and $t_{n2}$ were experimentally determined based on the characteristics of ${\left\{{\widehat{T}}_1\left[k\right]\right\}}_{k\in N}$ and ${\left\{{\widehat{T}}_2\left[k\right]\right\}}_{k\in N}$, so that PO2 does not monitor the transient regimes due to the switching in Figure 4b. The time interval ∆ between two consecutive sequences was zero.

The thermal regime of the converter board varies during operation. After powering up the converter, the temperatures of different locations on the board increase and stabilize at values that depend on the board geometry, the operating regime, and the ambient temperature. Consequently, as Figure 8b suggests, the thermal distribution on the surface of the board and the components is non-uniform. The temperature status of the output filter capacitors is detailed in the inset at the top of the figure. It is observed that the temperatures differ both from one capacitor to another and on the surfaces of the capacitor capsules, depending on the measurement point: ${33.1 }^{°}\mathrm{C}$ and ${35.8 }^{°}\mathrm{C}$ for C1, ${36.7 }^{°}\mathrm{C}$ and ${38.3 }^{°}\mathrm{C}$ for C2, ${\mathrm{a}\mathrm{n}\mathrm{d} 37.3 }^{°}\mathrm{C}$ and ${39.1 }^{°}\mathrm{C}$ for C3. In these circumstances, the values of the equivalent parameters of the capacitors were determined during 20 series of 400 cycles with intervals of approximately 12 min between two series.

Table 4. The estimated equivalent parameters of PO2 resulting from the series A and from the series $\mathsf{\Omega }$. (1—the average values of the 400 estimates, $\overline{C_{ei}}$, $\overline{R_{sei}}$; 2—the intervals in which the values in a series were located; 3—the mean square deviation in absolute values/percentage of the 400 estimates from the average value ${\sigma }_{··}$; 4—the number/percentage of the values in the series [$\overline{C_{ei}}-{\sigma }_{··},\overline{C_{ei}}+{\sigma }_{··}], [\overline{R_{sei}}-{\sigma }_{··}, \overline{R_{sei}}+{\sigma }_{··}]$. The last two lines of the table show the temperature variation and the deviation of the value in line (*) from the value in line (**), respectively.

	${\mathit{C}}_{\mathit{e}1}$[F]	${\mathit{R}}_{\mathit{s}\mathit{e}1}$[Ω]	${\mathit{C}}_{\mathit{e}2}$[F]	${\mathit{R}}_{\mathit{s}\mathit{e}2}$[Ω]	${\mathit{C}}_{\mathit{e}3}$[F]	${\mathit{R}}_{\mathit{s}\mathit{e}3}$[Ω]
(A)-${\theta }_{Ci}$	${\theta }_{C1}=27.4 °\mathrm{C}$		${\theta }_{C2}=28.8 °\mathrm{C}$		${\theta }_{C3}=27.7 °\mathrm{C}$
1. (*)	0.000308	0.500353	0.000304	0.493573	0.000295	0.586933
2.	[0.000306, 0.000315]	[0.401475, 0.543484]	[0.000302, 0.000307]	[0.440476, 0.535087]	[0.000293, 0.000296]	[0.55714, 0.622899]
3.	8.13 × 10−7/ 0.247%	0.01287/ 2.572%	5.54 × 10−7/ 0.169%	0.011034/ 2.235%	4.51 × 10−7/ 0.124%	0.010091/ 1.719%
4.	301/75.25%	292/73%	275/68.75%	276/69%	275/75.25%	278/73%
(Ω)-${\theta }_{Ci}$	${\theta }_{C1}=37.4 °\mathrm{C}$		${\theta }_{C2}=41 °\mathrm{C}$		${\theta }_{C3}=42 °\mathrm{C}$
1. (**)	0.000311	0.467614	0.000308	0.458981	0.000299	0.556098
2.	[0.000309, 0.000312]	[0.42724, 0.509411]	[0.000306, 0.000309]	[0.4263, 0.513102]	[0.000298, 0.0003]	[0.528205, 0.584585]
3.	5.18 × 10−7/ 0.162%	0.00989/ 2.114%	4.64 × 10−7/ 0.148%	0.010116/ 2.204%	3.67 × 10−7/ 0.120%	0.009489/ 1.706%
4.	281/70.25%	283/70.75%	270/67.5%	278/69.5%	284/70.25%	277/70.75%
Deviations of (*) from (**)	$∆{\theta }_{C1}=10 °\mathrm{C}$		$∆{\theta }_{C2}=12.2 °\mathrm{C}$		$∆{\theta }_{C1}=14.3 °\mathrm{C}$
	−0.9646%	+7%	−1.2987%	+7.5366%	−1.3377%	+5.5448%

summarizes the beginning and end of the experiment: series (A) and series (Ω). Figure 10 refers to four series: series (A), two intermediate series, and series ($\mathsf{\Omega }$). The vertical segments correspond to the ranges of the series values, and the connecting lines join the average values calculated for each series. The abscissas of the segments correspond to the temperatures of the capsule upper surface centers. The temperature characteristics ${\theta }_{C1}(t)$, ${\theta }_{C2}(t)$, and ${\theta }_{C3}(t)$ are strictly increasing, without suggesting an exponential variation. The series values of the ($\mathsf{\Omega }$) practically characterize the last five series of measurements.

Figure 11 displays the probability distributions corresponding to the estimates made in the series (A) and ($\mathsf{\Omega }$).

During the estimation of the equivalent parameters of each capacitor in the bank, the capacitor is electrically isolated both from the converter and the load. As a result, the variation in the input voltage and the load value do not change the results mentioned in the article. When the input voltage, the load, and the configuration of the capacitor bank vary, the ripple changes occur. The influence of the change in the capacitance value on the ripple was highlighted in [29] (Figure 14c). Figure 12 illustrates these influences obtained experimentally for three input voltage values, $V_{in}= 8 \mathrm{V}, 9 \mathrm{V}, 10 \mathrm{V}$, and three values of $R_{Load} = 6.6 \mathsf{\Omega }, 4.95 \mathsf{\Omega }, 3.3 \mathsf{\Omega }$. Zones 1, 2, 3, and 4 correspond to the operation of the converter with C1 not connected, C2 not connected, C3 not connected, with all capacitors connected. During the measurement process, the average value of the $V_{Load}$ voltage decreases by about $2.5 \mathrm{m}\mathrm{V}$. It is also observed that independently of the estimation process: (i) when the load current increases (decrease of $R_{Load}$) the average voltage on the load decreases by about $2 \mathrm{m}\mathrm{V}$; (ii) disconnecting a capacitor has a similar effect to increasing the load; and (iii) the influence of disconnecting a capacitor is related to its capacitance. These last three findings characterize the converter.

4. Discussion

(i)

The experiments performed with the DC–DC converter in Figure 5 confirm the applicability of the principle diagram in Figure 3. Moreover, the principle of estimating the parameters of the output filter capacitors can be applied for banks with more than three capacitors. In this case, scalability issues may arise, for example, regarding the number and compatibility of the microcontroller input/outputs needed for connecting the VEN.

(ii)

The sum of the times in Table 3 indicates that a cycle of estimating the parameters of the three-capacitor bank is performed online and in real time, in less than $37 \mathrm{m}\mathrm{s}$.

(iii)

Within each series of estimates, the temperatures of the three capacitors were different. During the experiments, they increased with effect on the average values of the equivalent parameters (Table 4) by increasing $C_e$ and decreasing $R_{se}$.

• Considering that the stabilized equivalent mean values (line 1 of the series (Ω)) are correct, it is found that the values of $C_{e1}$, $C_{e2}$ and $C_{e3}$ of the series (A) are lower by approximately 1%, and the values of $R_{se1}$, $R_{se2}$ and $R_{se3}$ are higher by approx. 6–7% (last line of Table 4). Apart from $C_{e3}$, for any segment in Figure 10, the ranges of the estimated values intersect, although the mean values of $C_e$/$R_{se}$ monotonically increase/decrease.
• The probability distributions in Figure 11, correlated with the data in Table 4, allow us to consider that the accuracy of the estimates is very good: below $1 \mu \mathrm{F}$ in the case of equivalent capacitances and about $11 \mathrm{m}\Omega$ in the case of ESR.
• The purpose of the configuration illustrated in Figure 3 is to estimate the capacitor parameters during the converter’s current operation. The triggering estimation depends on the management of diagnosis and prognosis. The above observations are crucial for defining these moments. The decision can only be made by the designer and/or converter user. They should also take into consideration the specific constructive elements, the environmental conditions, and the working regime of the converter.

(iv)

In the discharge/charge circuits of a capacitor, both the equivalent resistance of the capacitor and the conduction resistance $r_{DSon}$ of the switch transistor act as resistive elements. Therefore, the $R_{se}$ values in Table 4 correspond to the sum $R_{se}=R_{se}^{\ast }+r_{DSon}$, where $R_{se}^{\ast }$ is the corrected value of ESR. The MOSFET transistors were chosen with a minimum control signal in the grid and conduction resistance $r_{DSon}$ as low as possible, i.e., $r_{DSon}=10 \mathrm{m}\mathrm{\Omega }$. Their effect on the ESR values in the $\mathsf{\Omega }$ series of Table 4 is illustrated in

Table 5. Corrected values of average values of ESR in line 1, series ($\mathsf{\Omega }$) of Table 4, taking into account the resistance $r_{DSon}$ of the switch transistors.

${\mathit{R}}_{\mathit{s}\mathit{e}1}$[Ω]	${\mathit{R}}_{\mathit{s}\mathit{e}1}^{\ast }$[Ω]	${\mathit{R}}_{\mathit{s}\mathit{e}2}$[Ω]	${\mathit{R}}_{\mathit{s}\mathit{e}2}^{\ast }$[Ω]	${\mathit{R}}_{\mathit{s}\mathit{e}3}$[Ω]	${\mathit{R}}_{\mathit{s}\mathit{e}3}^{\ast }$[Ω]
0.467614	0.457614	0.458981	0.448981	0.556098	0.546098

. The $R_{se}^{\ast }$ values are reduced by 2.14% for C1, 2.18% for C2 and 1.8% for C3. The mean square deviation in percentage remains practically the same. If the bank capacitors had been of better quality, with a lower ESR, the $r_{DSon}$ weight in the estimation result using the presented method would have been higher.

(v)

A notable fact is the closeness of the frequencies associated with the average values of the equivalent parameters in Table 4 established on the frequency characteristics in Figure 7. They are given in

Table 6. Frequencies extracted from the frequency characteristics of the capacitor bank corresponding to the average values of the equivalent parameters in line 1, series ($\mathsf{\Omega }$) of Table 4 and Table 5.

${\mathit{C}}_{\mathit{e}1}$[F]	${\mathit{R}}_{\mathit{s}\mathit{e}1}$[Ω]	${\mathit{C}}_{\mathit{e}2}$[F]	${\mathit{R}}_{\mathit{s}\mathit{e}2}$[Ω]	${\mathit{C}}_{\mathit{e}3}$[F]	${\mathit{R}}_{\mathit{s}\mathit{e}3}$[Ω]
0.00031054 *	0.457614	0.0003075 *	0.448981	0.0002988374 *	0.546098
53.88 Hz	58.27 Hz	55.3 Hz	58.27 Hz	52.49 Hz	56.77 Hz
$f_{e1}=56.075 \mathrm{H}\mathrm{z}$		$f_{e2}=56.785 \mathrm{H}\mathrm{z}$		$f_{e3}=54.63 \mathrm{H}\mathrm{z}$

(*) These capacitance values have not been rounded to correlate as accurately as possible with the frequency characteristics.

for the series of experiments ($\mathsf{\Omega }$). The fact that the pairs of values ($C_{ei}$, $R_{sei}^{\ast }$), $i=\overline{1,3}$ correspond, according to Figure 7, to very close average frequencies ($58.27 \mathrm{H}\mathrm{z}$, $56.785 \mathrm{H}\mathrm{z}$, $54.63 \mathrm{H}\mathrm{z}$), suggests that the presented estimation method associates an equivalent frequency $f_e$ to the equivalent values of the capacitor parameters. The attribute “equivalent” designates in this case both the association with the equivalent circuit and the association with the capacitor discharge/charge voltage signal spectrum.

(vi)

PO2 can be implemented on the same microcontroller interfaced with the converter integrated circuit, and the diagram in Figure 5 can be partially integrated into a single dedicated circuit [31]. The estimation cycle can be triggered whenever it is relevant during the operation of the converter, and the calculated parameters can be transmitted to the upper level of a maintenance application. It is also important to note that the number of monitored capacitors can be adapted as needed.

(vii)

The experiments were performed with a DC–DC buck-boost converter made with the LTC 3780 integrated circuit operating in buck mode at an output voltage of $3.3 \mathrm{V}$ and with a resistive load $R_{Load}=6.6 \mathsf{\Omega }$ aimed to validate the method for estimating the parameters of a filter capacitor bank. These values were chosen, on the one hand, from conditions of direct compatibility with the input voltage levels of the microcontroller, and on the other hand, so as not to charge the converter with a large load. To apply the proposed method for higher output voltage levels, both in buck and boost mode, it is necessary to complete the configuration with level shifter stages for adapting the converter voltages to the microcontroller.

(viii)

The estimation of capacitor parameters with the proposed model should be considered as an operation, part of the maintenance strategy chosen by the converter user. For this purpose, the microcontroller transmits to a higher level of maintenance structure the estimated values of C and ESR. The following aspects are useful for adopting a strategy:

• PO2 estimates the capacitance and ESR values by repeating cycles that may contain 1, 2, or 3 sequences.
• The estimations can be made continuously on preset time intervals, without interrupting the converter operation. They can highlight the following, in real time: (i) the aging effect when the capacitance decreases and the ESR increases, and (ii) the large variations in the time constants specific to the pre-breakdown regime when the insulation resistance decreases.
• Through additional operations, after each estimation cycle consisting of three sequences, an equivalent bank capacity can be calculated based on a bank model.
• The schematic allows, through additional control, performing maintenance operations at the capacitor level, not the capacitor bank. Thus, extracting and replacing a faulty capacitor can be discharged and disconnected without converter shutdown, as in the case of the estimation. This means a higher level of reliability at the system level by avoiding the system shutdown.

5. Conclusions

The article presents a method for determining the equivalent parameters of the capacitors that make up the capacitor bank of the output filter of a DC–DC buck converter. The method provides a usable tool for monitoring the condition of the capacitors. The estimated parameters correspond to the equivalent series R–C circuit of a capacitor. The capacitors of the bank are connected in parallel. The estimation is performed online and in real time using a parameter observer, without interrupting the converter operation. The observer successively processes the signals at the capacitor terminals during a discharge/charge sequence. The absence of auxiliary sensors represents a notable advantage of the method. The experiments using a converter, with $3.3 \mathrm{V}$ output voltage and a filtering bank consisting of $3 \times 330 \mathsf{\mu }\mathrm{F}/35 \mathrm{V}$ aluminum capacitors proved a good precision and a duration for the 6-parameter estimation cycle of approximately $38 \mathrm{m}\mathrm{s}$.

The application of the method in circuits that use capacitor banks, primarily for filtering, involves solving practical problems such as the following: creating the possibility of isolating the capacitors from the circuit during parameter estimation, adapting VEN to the circuit voltages, interfacing with the microcontroller, and calibrating PO2 depending on the dynamics of the discharge/charge processes. All these problems, together with the proposed method, must also be analyzed from the point of view of the reliability and maintenance cost of the more complex structure that results from the implementation of the method.

The main direction for future research is to adapt the method to DC–DC boost–buck converters.