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Journal: Electronics, 2025
Volume: 14
Number: 3317
Article:
Hardware Accelerator Design by Using RT-Level Power Optimization Techniques on FPGA for Future AI Mobile Applications
Authors:
by
Achyuth Gundrapally, Yatrik Ashish Shah, Sai Manohar Vemuri and Kyuwon (Ken) Choi
Link:
https://www.mdpi.com/2079-9292/14/16/3317
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