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Article

Suppression of Cohesive Cracking Mode Based on Anisotropic Porosity in Sintered Silver Die Attach Encapsulated by Epoxy Molding Compounds

by
Keisuke Wakamoto
*,
Masaya Ukita
,
Ayumi Saito
and
Ken Nakahara
ROHM Co., Ltd., Kyoto 615-8585, Japan
*
Author to whom correspondence should be addressed.
Electronics 2025, 14(16), 3227; https://doi.org/10.3390/electronics14163227
Submission received: 30 June 2025 / Revised: 12 August 2025 / Accepted: 13 August 2025 / Published: 14 August 2025
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Abstract

This paper investigates the suppression of the cohesive cracking mode (CCM) in the sintered silver (s-Ag) die layer by intentionally introducing anisotropic porosity through two press sintering methods. Full press (FP) and local press (LP) bonding represent the s-Ag formed by pressing the die-attached assemblies (DAAs) on either the entire top surface or only on the silicon carbide (SiC) top surface, respectively. The fabricated DAAs were encapsulated with epoxy molding compounds. Degradation was evaluated using a nine-point bending test (NBT) under cyclic force between 0 and 270 N with a triangle waveform for 3 min per cycle at 150 °C. Scanning tomography images after 500 NBT cycles showed that the LP reduced the inner degradation ratio by up to 21.1% compared to the FP. Cross-sectional scanning electron microscopy revealed that the FP progressed cracking in the s-Ag die layer, whereas the LP showed no evidence of cracking. A finite element analysis revealed that in the FP, the accumulated plastic strain (APS) was concentrated in the s-Ag layer within the inner SiC chip. In contrast, the APS of the LP was preferentially concentrated outside the SiC chip. This preferential localization of damage outside the chip presents a promising approach for enhancing the reliability of packaging products.

1. Introduction

Packaging (PKG) for power electronics involves bonding multiple materials together. Typically, semiconductor dies are bonded to directly bonded copper substrates or active metal brazing substrates. These die-attached assemblies (DAAs) are then encapsulated using epoxy molding compounds (EMCs) [1]. Recently, power conversion systems have required PKG with a higher power density [2]. Power devices based on so-called-wide bandgap (WBG) materials are considered to be the key to meeting this goal [3,4]. However, WBG materials also introduce new technological challenges. A high power density inherently reduces the available pathways for heat dissipation in power conversion systems, necessitating the use of high thermal conductivity materials. To meet this requirement, sintered metal bonding techniques, such as sintered silver (s-Ag), have been explored as promising solutions because of s-Ag’s relatively higher thermal conductivity than conventional soldering materials [5,6]. However, the porosity in s-Ag limits its industrial application because it leads to low thermal conductivity. Therefore, pressurized s-Ag has gained attention as an effective die attach material because applying pressure during sintering significantly reduces porosity [7,8,9,10]. Additionally, meeting the AQG324 qualification standards has become essential for evaluating PKG reliability [11]. The thermal shock test (TST), which subjects samples to alternating high and low ambient temperatures for specific durations, is widely used to assess PKG reliability. It has been widely adopted to assess the reliability of PKG. Due to the different coefficients of the thermal expansion (CTE) among the various components, the TST induces thermal and mechanical stress, often leading to failure [12]. Two primary failure modes are often observed during the TST: a cohesive cracking mode (CCM) in the die layer [13,14,15] and an interface delamination mode (IDM) at the metal/metal or EMC/metal [16,17]. To simplify the TST assessment, we developed a nine-point bending cyclic test (NBT), which can provide the similar out-of-plane deformation observed during the TST by applying a force variation at a specific temperature [18]. We previously demonstrated that the NBT at 150 °C reproduced the s-Ag CCM observed in the TST conducted over a temperature range from − 40 °C to 150 °C. The advantage of the NBT lies in its isothermal environment and precise control of the mechanical motion, making it well-suited for identifying the root cause of the CCM.
Cracking that develops horizontally beneath the semiconductor chips is a critical failure mode because it significantly increases the thermal resistance of the PKG (Rth). Rth is defined as the temperature difference between the highest temperature at the chip and the ambient temperature, divided by the power loss at the chip [19,20,21]. The Rth increase ratio (rth) is defined as the relative increase in the Rth after reliability tests, calculated by dividing the change in Rth by the initial Rth. This increase is primarily caused by degradation within the chip, which hinders the thermal pathway from the chip to the lower-side material. In general, the lifetime of a product is defined as the point at which rth reaches 20% [11]. As an inspection methodology for the existence of cracking, scanning acoustic tomography (SAT) has been commonly used for nondestructive inspections. A high acoustic reflection intensity in the die layer corresponds to the existence of air inside, signifying degradation due to horizontal cracking. There is a positive correlation between the product lifetime and the degradation area ratio in the die layer as measured by SAT; when the degradation exceeds 20%, the product is considered to have reached its lifetime limit [22,23]. Therefore, a key design objective is to suppress the cracking area in the die layer during the reliability tests. Among the CCM and IDM, the CCM is more manageable from a design perspective. This is because the CCM progresses slowly and steadily over time, whereas the IDM tends to propagate dynamically and unpredictably [24]. The following section will focus on reviewing the design strategies for mitigating the CCM.
The level of damage in the CCM of the s-Ag layer was assessed by the accumulated plastic strain (APS) per cycle, which was calculated by a finite element analysis (FEA), considering the experimental conditions [25,26,27,28]. The APS of the s-Ag especially increases at high temperatures, when the temperatures exceed the point at which the tensile mechanical property of s-Ag changes from elastic to plastic, which usually occurs at approximately 100 °C [29,30,31]. This transition temperature is indexed as “HT” in this section. From this viewpoint, lowering the maximum temperature is favorable for suppressing the CCM [32,33]; however, this is not practical. If high maximum temperatures are required, die material modification in the DAA is the primary approach. Three aspects for increasing the lifetime in the s-Ag die layer during the TST are introduced.
The first approach involves modifying the porosity and elemental composition of the s-Ag layer. To increase the plasticity range at high temperatures exceeding HT, a less porous structure is preferred. This can be effectively achieved by increasing the applied pressure during the hot sintering process [34,35,36,37,38,39]. As a result, less porous s-Ag positively decreases die degradation by increasing the durability of the APS during the TST [31,32]. Additionally, adding another element, such as a diamond, boron nitride, or copper oxide, to s-Ag positively enhances the material strength at exceeding HT by restricting the Ag grain motion during TSTs [39,40,41,42,43]. However, this strengthening phenomenon simultaneously sacrifices the s-Ag plasticity at high temperatures, which has still not been demonstrated in the lifetime enhancement in the TST [39,42].
The second approach concerns the thickness of the s-Ag layer. Among the various PKG materials, the CTE gap between the semiconductor and substrate is typically the highest. Increasing the thickness of the s-Ag die layer reduces the APS per cycle during the TST, as shown by the FEA [43,44]. For instance, the degradation in a 100 µm thick s-Ag layer after 1000 TST cycles was reduced to one-third of that in a 50 µm thick layer under the same TST conditions [32]. Furthermore, increasing the die layer and the filet height of the s-Ag also contributes to reducing the concentration of the APS, which is located at the corner of the chip edge, as previously discussed in solder DAAs [45,46].
The third approach focuses on controlling the stress gradient within the s-Ag layer. As previously noted, the durability of s-Ag is highly sensitive to its porosity distribution. When the porosity is inhomogeneous in the s-Ag layer, the cracking behavior during the TST can change. For the horizontal porosity distribution of the s-Ag die layer, DAAs with active metal brazing substrates and soft copper unintentionally resulted in a hill valley surface configuration. These irregularities led to the formation of multiple diagonal cracks in the s-Ag layer after 2400 TST cycles [47]. The expectation is that the total horizontal crack length will be suppressed by replacing a generation of diagonal cracks; however, this crack change has not yet been demonstrated to improve the lifetime of the TST. For the vertical porosity distribution of the s-Ag die layer, Zhao et al. [48] found that pore segregation is found beneath the SiC chip after thermal storage at 350 °C for 800 h. They took a more deliberate approach by creating a vertical pore gradient, stacking two s-Ag layers with different sintering temperatures and applying stress profiles. This pore gradient in the die layer effectively reduces the thermomechanical stress, as confirmed by the FEA simulations. The degradation ratio after the TST in this gradient s-Ag layer was 5% lower than that in DAAs with homogeneous porosity [49]. However, this method increases the risk that the Rth increases due to the worsening of the thermal conductivity of the larger porosity in the s-Ag layer [7,8,9,10]. If the porosity level remains within the die layer but maintains the microstructure, it is possible to achieve reliable PKG with a low Rth.
In this study, we attempted to suppress the CCM by intentionally creating anisotropic porosity in the s-Ag layer in the horizontal direction via two pressings. Both pressings maintain a small porosity of s-Ag within the die layer. The outer side of the chip’s s-Ag porosity is regulated by the applied pressure. The remainder of this paper is organized as follows. Section 2 describes the assessment flow of the PKG reliability and clarifies how we intentionally created the anisotropic porosity in the s-Ag layer. Section 3 presents the degradation results of the PKG after the NBT as a function of NBT cycles. The degradation portion after the NBT was inspected by SAT. The failure mode was investigated by backscattering electron (BSE) images of the cross-sectional scanning electron microscopy (SEM). In Section 4, the FEA was used to discuss the APS distribution and failure mode correlations. Finally, Section 5 presents the conclusion.

2. Materials and Methods

Figure 1 shows the experimental schematic view of this study. First, a commercial Ag paste was screen-printed on the metal substrate. The 64Ti (Ti 90%, Al 6%, and V 4% in weight) with Ag sputtering was adopted for the metal substrates. The 64Ti prevents plastic deformation during NBT to maintain test controllability. Ag sputtering improves the adhesivity with the s-Ag die layer. A 0.2 mm thick stainless steel metal plate with a 9 mm squared hole was used as the stencil mask.
The printed Ag was then dried at 140 °C for 90 min in air. After drying, a 4.8 mm square SiC chip with a thickness of 0.35 mm was mounted on the center of the dried Ag layer. The external uniaxial press was then applied by uniaxial motion while supplying heat. As shown in the top left schematic view of Figure 1, the press region was adjusted by changing the carbon sheet size. “FP” and “LP” refer to the s-Ag die layer formed by pressing the entire top surface of a DAA or the SiC chip of a DAA, respectively. In this study, the carbon sheet size of FP and LP was 20 + 0.2 mm and 4.8 + 0.2 mm square, respectively. The carbon sheets are manually placed at the center of the DAAs. The applied force for FP and LP was regulated to 24 kN and 1.38 kN to provide the 60 MPa pressure on the pressed area. The thickness of the s-Ag layer at the pressed area was set to 50 μm. SEM bird-view images show the porous structure of the s-Ag layer between the FP and LP, which is located outside the SiC chip. For the FP, outside s-Ag, almost all surfaces appear smooth in the overall image, except for the area surrounding the SiC chip edge. Since the applied stress direction is uniaxial, in the edge portion surrounding the SiC chip it was difficult to supply enough pressure. To prevent this occurrence, cold isostatic press sintering is a promising approach for applying hydrostatic pressure with a sufficient press at the edge region [50]. For a more detailed view of the pressed area, the crystal is aggregated to form a bulk sputtered Ag as-deposited surface [51]. Note that a tiny nanoporous material was found at the grain boundary.
For the LP, the difference from the FP is twofold. As observed from the overall SEM image, a groove with approximately 20 μm width is found surrounding the SiC chip. When the SiC chip was locally pressed, it sank to actively create space between the SiC chip and outer s-Ag layer. The outside overall s-Ag layer in the LP is more rugged than the surface in the FP outside the s-Ag layer. The enlarged SEM view shows that the s-Ag has a microsized porous structure, resulting from insufficient sintering under no pressure. The average grain diameter of non-pressed s-Ag was approximately 1.8 μm, which was approximately three times larger than that of the pressed s-Ag observed outside the s-Ag layer in FP, due to insufficient sintering. Consequently, FP and LP successfully created a porous structure distinction on the outside of the SiC chip in the DAAs. Although it is not presented in this paper, the porous control method has scalability because the porous state can be attained by only changing the cushion size in the uniaxial press tester, which is manufactured by companies like Boschman Technologies [52] and Webber GmbH [53].
After fabricating the DAA, the EMC powder was thermo-compressed in the molding machine. Then, as illustrated in step 3 of Figure 1, a UV laser was used to process the DAA so that the EMC and s-Ag die layer were the same size. This encapsulated DAA is the evaluated PKG in this study. The PKG was set between eight support pins and one push pin, which was the same configuration as in our previous studies [18]. The NBT was conducted under a cyclic force between 0 and 270 N with a triangle waveform for 3 min per cycle at 150 °C. The stress level of NBT corresponds to the stress level during TST, changing the temperature from − 40 °C to 150 °C [31]. The detailed experimental conditions for each step, including the machine and material information, are presented in Table 1.
SAT was used to evaluate the degradation area of the PKG after 100, 300, and 500 cycles of NBT. BSE images of cross-sectional SEM after NBT were used to assess the failure mode trajectory from initial, 100, and 500 cycles of NBT in the FP and LP PKG. FEA based on the PKG in FP and LP was used to examine the differences in the failure mode between the FP and LP PKG.

3. Results

Figure 2a shows the SAT images for the NBT initially and at 100, 300, and 500 cycles of the FP and LP. The number of samples for the NBT was set to three. The SAT images in one sample indexed as No. 1 were examined initially and at 100, 300, and 500 cycles to confirm the degradation progress during the NBT. The SAT images in two samples indexed as No. 2 and 3 were examined initially and at 500 cycles to confirm the divergence of results after 500 cycles of the NBT. All images were taken from the bottom side using an ultrasonic probe at 25 MHz. The color difference represents the difference in the reflective acoustic intensity. The lighter color represents the degradation area, which corresponds to the high reflective intensity caused by the air inside. In contrast, the darker color represents no such air, meaning that no degradation occurred in this area. The red frame represents the die area, which corresponds to the SiC chip area. For FP-No. 1, degradation mainly occurred after 100 cycles of the NBT on both sides of the areas located outside the die area. This degradation area spread to the bottom outside area after 300 cycles. Notably, the degradation can also be found at the bottom left corner within the die area. After 500 cycles, the degradation occurred not only in the outer area but also in the inner die area. The other samples of FP-No. 2 and 3 also showed degradation, as observed in the 500 cycles of FP-No. 1. In contrast, LP-No. 1 always shows a darker color in the images from the initial start to 500 cycles of the NBT. LP-No. 2 and 3 also showed no degradation after 500 cycles of the NBT.
Figure 2b shows the numerical analysis results of the degradation ratio in the inner and outer regions of the SiC chip die area based on the 500-cycle SAT images of the NBT in the FP and LP in Figure 2a. The definition of the degradation ratio is provided in the “Definition of degradation ratio” box in Figure 2b. According to the numerical analysis results in the table, as shown in the middle of Figure 3b, the inner and outer degradation average values at the FP were 13.6% and 54.7%, respectively. In contrast, the LP shows 0% in those values. That is, the FP shows degradation not only on the inner but also on the outer side during the NBT. The standard variation value of the degradation ratio in the FP was 6.5% for the inner region and 16.6% for the outer region. In addition, we showed the bar graph on the right side of Figure 3b to illustrate the full range of the FP data after 500 cycles of the NBT, from the minimum to the maximum value. According to the bar graph results, the inner degradation ratio for the FP after 500 cycles is 13.6 − 4.7 + 7.5 %. This implies that the LP degradation suppression effect from the FP inner degradation ratio achieves up to 21.1%. This improvement is particularly noteworthy, as it represents a significant enhancement over the previously reported 5% reduction achieved using vertical inhomogeneous porosity distribution techniques [49]. Additionally, the outer degradation ratio in the FP is 56.2 − 15.8 + 17.4 %.
To determine the reason for the degradation difference between the FP and LP during the NBT, a cross-sectional BSE SEM analysis was performed as a function of the NBT cycle. Figure 3a,b show the cross-sectional BSE SEM observation results at the initial stage, 100, and 500 cycles of the NBT for the FP and LP, respectively. Five types of images were captured to elucidate the state of the DAAs in each condition. The top line shows an overall image to understand the shape of the s-Ag layer in the PKG. The second line shows an enlarged image near the SiC edge to illustrate the cracking behavior. The third line shows a local image in the blue square area, as depicted in the second line, to illustrate the s-Ag pore microstructure morphology. The fourth line shows the enlarged image of the EMC/s-Ag to examine the bonding state. The fifth line shows the reinforced edge image to illustrate the interface status.
For the FP at the initial stage of an overall image, the s-Ag layer crawls up at the side wall of the SiC chip, and the s-Ag layer shows a gradual downward slope to the outside. The s-Ag layer shows a homogeneous porous structure both beneath and outside the SiC chip, as observed in the second-line image. The porosity level was approximately 5%. and the pore shape was circular, as observed from the enlarged third-line image. This pore morphology is similar to the previous results of the pressurized s-Ag at a 60 MPa pressure at 300 °C for 10 min [54]. Consequently, we confirmed that the FP successfully achieved the homogeneous porosity in the s-Ag layer at the initial stage. For the EMC/s-Ag, the interface is almost flat, as seen from the fourth- and fifth-line images.
For FP at 100 cycles of NBT, the CCM in the s-Ag die layer is visible, as shown in the first- and second-line images. The inclined crack damage starts from the corner of the SiC chip edge to the s-Ag layer inside. Note that the irregular pore shape is located close to the SiC chip edge, resulting in increased porosity, as observed from the third-line image. The porosity level increases to 12%, which is 2.4 times higher than that at the initial. Additionally, IDM is visible between EMC and s-Ag, as observed from the fourth- and fifth- line images.
For the FP at 500 cycles of the NBT, both failure modes are still visible, as seen during the 100 cycles of the NBT. The primary difference in the CCM between the 100 and 500 cycles of the NBT is the cracking propagation in the s-Ag die layer. With 500 cycles of the NBT, the crack ran along the substrate surface in a horizontal direction, as seen from the second-line image. The porosity continues to increase at 24%, and the pore is located closely, as seen from the third-line image. It is well-known that the s-Ag pore growth is associated with Ag sliding under applied stress at high temperatures [31]. Consequently, this pore growth from the initial state to 500 cycles is related to the stress concentration at the edge of the SiC chips during the NBT. A detailed discussion will be presented in the next section based on the FEA results. The EMC/s-Ag delamination is still found in the fourth- and fifth-line images.
In stark contrast with the LP case, the cross-sectional morphologies show an entirely different tendency from those in the FP. For the initial state, the s-Ag morphology in the LP showed no crawling up along the SiC chip side, as seen in the first-line image. For the SiC chip outside, the thickness of the s-Ag layer is almost the same as that of the SiC die layer up to 50 μm outward from the edge. After that, the thickness is approximately twice that of the SiC die layer. This increased thickness is attributed to a higher porosity in the s-Ag layer at the outside of the SiC chip under the no-pressure condition, as depicted in Figure 1. The s-Ag layer has a distinct structure along the horizontal line, as seen in the second-line image. Dense structures are observed beneath the SiC chip, as seen in the FP porosity at the initial state. In contrast, a higher porous structure is observed outside the SiC chip. It is worth noting that the SiC chip inside the approximately 20 μm width within the blue dashed region shows more porosity than the inside of the SiC chip. The porosity level was 13%. Thus, the proposed LP has a slight pore gradient from the SiC chip inside to the SiC chip outside. In the third-line image, nonuniform microsized pores are randomly located in the blue square, as depicted in the second-line image. The porosity level on the outside was 25%, which originated from a smaller press outside the SiC chip. Additionally, the high porosity produces a rugged EMC/s-Ag interface, as depicted in the forth- and fifth-line image. This rugged interface seems preferable for suppressing delamination during the NBT because an increased interface region increases the toughness [55,56]. After 100 and 500 cycles of the NBT in the cross-sectional BSE images, the morphology remained almost identical to its initial state, with no delamination observed at the EMC/s-Ag and no cracking in the s-Ag layer beneath the SiC chip. The difference from the initial state to 100 and 500 cycles is the microstructure of the s-Ag layer, as shown in the third-line images. For 100 and 500 cycles, the Ag grains are located separately, like the discontinuous cracking from the initial state that has a Ag grain connection.
We also investigated the adhesive condition between the SiC chip side wall and the adjacent material after 100 cycles of the NBT in the FP and LP using local cross-sectional SEM observations to accurately reflect the model configuration in the FEA, as will be presented in the next section. The choice of 100 cycles for this observation corresponds to the start cycle of the fracture mode difference between the FP and LP during the NBT. Figure 4 shows an enlarged view around the side of the SiC chip for the FP and LP after 100 cycles of the NBT, along with the reinforced edge images. For the FP sample, a visible gap exists between the SiC and s-Ag. The s-Ag also exhibited irregular pore shapes similar to those observed in the pressureless s-Ag layer that exists outside of the SiC chip of the LP in Figure 3b. This gap is attributed to the insufficient sintering of the s-Ag, which is likely caused by the limitations of uniaxial pressing. In contrast, the LP sample shows complete adhesion between the EMC and the SiC chip without any gaps in the LP. Therefore, we conclude that the FP after 100 cycles of the NBT is a discontinuous structure with SiC side wall/s-Ag and EMC/s-Ag, whereas the LP after 100 cycles of the NBT still maintains a perfect continuous structure.
Figure 5 summarizes the differences between the FP and LP in terms of the pressing area control methodology, achievable porosity gradient, and CCM degradation within the SiC chip during the NBT, considering the obtained results. The LP method is a favorable method for DAAs. Although the applied force value in the LP was one-seventeenth of the applied force in the FP in the die bonding process, the CCM degradation ratio after the NBT was 0%, whereas the FP showed the CCM degradation ratio with 13.6 − 4.7 + 7.5 % after 500 cycles of the NBT. This CCM degradation ratio in the FP exceeds the rth by 15%, considering the relationship between the degradation ratio and thermal resistance in the previous study [23]. That is, the FP approaches the product lifetime defined as the rth of 20% [11].

4. Discussion

Based on the observation analysis results stated in the previous section, we investigated the stress distribution around the SiC chip’s bottom right corner. The main objective of this FEA is to determine the reason why the FP proceeded with the degradation of the pore growth and cracking in the s-Ag layer from 100 cycles of the NBT, whereas the LP showed no substantial damage in the s-Ag beneath the SiC chip up to 500 cycles of the NBT.
Figure 6a shows a schematic of the modeling and boundary conditions used for the FEA. For simplicity, we adopted two-dimensional (2D) FEA models, reflecting our experiment set up in the NBT. Note that this 2D model cannot illustrate the partial outer degradation effect on the inner delamination. However, we assumed that the inner degradation and outer degradation relationship is pivotal to considering the main cause of the degradation during the NBT. The model was produced using commercial software ANSYS 19.0. The axis-symmetric condition was set on the left edge of the model. A force variation of 270 N was set at the bottom line of the load jig. The calculation was implemented with three cycles of force variation to stabilize the FEA accuracy, as previously adopted [21]. The fix was set on the top line of the support jig. The ambient temperature was set to 150 °C. The model configuration around the SiC chip’s bottom right corner varies in the FP and LP, as shown in the red frame of Figure 6a, which corresponds to the cross-sectional observation results presented in Figure 3a and Figure 4. For the FP s-Ag layer’s pore distribution, the entire s-Ag part has the same material, with low-porosity (lp) s-Ag based on the top-line image in Figure 3a at the initial state. The gap was intentionally fabricated among the SiC, EMC, and s-Ag layers because the EMC delamination easily occurred due to the planarized interface during the NBT. In contrast, for the LP s-Ag layer pore distribution, the s-Ag layer is set to lp, with a high-porosity (hp) for the inner and outside of the SiC, respectively, based on the numerical analysis results of the third-line image in Figure 3b at the initial state. Note that the middle state of porosity exists from the edge to the inside with a 20 μm width, as shown in the second-line images of Figure 3b; however, in this FEA, we eliminated this layer because simplifying the model directly allows us to discuss the cause of the fracture mode difference between the FP and LP. The differences in material characteristics between the hp and lp s-Ag layers are considered by elucidating the S–S curves for the lp and hp s-Ag, as will be stated later. All interfaces have no gaps, as shown in Figure 3b and Figure 4.
Figure 6b shows the mesh pattern in the FEA and local numerical analysis region around the stress concentration area during the NBT. We adopted an almost quadrilateral shape of the mesh to stabilize the calculation. In the jig portion, we allowed the triangular mesh to fit the arc shape in the jig. The mesh size was biased to be a fine size to precisely calculate the stress concentration area, where the edge of the SiC, EMC, and s-Ag layer gathers, as shown in the red frame in Figure 6b. The bias pattern was identical to that in our previous study [18,31]. As observed from the enlarged view of the mesh pattern, the element size was regulated to 4 μm2. To avoid the singularity of the numerical analysis results, the averaged values at 74 nodes located within the pink dotted frame around the boundary were chosen in this study. To improve the numerical convergence, the force step number was regulated to 240 times in this FEA.
Among the materials used in PKG, the elastic–plastic properties of s-Ag at 150 °C must be considered in the lp and hp s-Ag when evaluating the APS precisely in this FEA. To model the elastic–plastic curve in the lp and hp s-Ag, we conducted uniaxial tensile film testing prior to the FEA. Figure 7a shows the obtained stress–strain (S–S) curves for the lp and hp s-Ag at 150 °C under the strain speed of 5 × 10−4/s. The lp and hp s-Ag specimens were sintered at 300 °C for 10 min under a 60 and 0.7 MPa pressure, respectively, to illustrate the lp and hp s-Ag porosity levels of 5 and 25%. The strain rate and test temperature were selected to match the NBT conditions. The tensile specimens were shaped into a dog-bone specimen and pulled in the direction indicated by the white arrows, as shown in the photographs in Figure 7a, as reported in our previous work [57]. Both S–S curves show nonlinear behavior, indicating that the lp and hp s-Ag fractured in a ductile manner. For the lp s-Ag, the linear trend associated with the elastic region ends at the applied stress of approximately 35 MPa, followed by a gradual reduction in the slope up to around 45 MPa. Beyond this point, the curve exhibits a broad plateau extending to approximately 6% to be fractured. For the hp, the linear trend ends at around 5 MPa, and the slope becomes gentle, with a gradual increase in stress up to 7 MPa before it declines toward the fracture. Both curves were fitted using bilinear kinematic curves, as were widely used in previous studies because of their simplicity and ability to accurately capture the material’s elastic–plastic properties [18,31,43,44]. In this study, the red dotted lines represent the bilinear fitting curves (S–S curves) for the lp and hp s-Ag. We defined the first slope of E1 in the stress range from 20% to 70% of the ultimate tensile stress. Since the clear yield stress (YS) is difficult to define in both lp and hp s-Ag curves, we defined the YS by the 0.2% offset method, which was applied for a porous metal material [58]. The second slope of E2 was defined as the slope of the S–S curves after the yield point, up to the point where the curve changes relatively linearly. The red dotted line represents an approximate line, used for the fitting to the obtained S–S curves. The numerical data used for the bilinear fitting are shown in the box of the “Bilinear fitting for lp and hp” in Figure 7a. The other elastic material input values are shown in Figure 7b.
Figure 8a shows the APS distribution in the s-Ag layer for the FP and LP at three cycles of force applied in the NBT. The red zone represents the APS concentration. For the FP, a large APS value is locally distributed at the bottom right corner edge of the SiC chip next to the gap. From an enlarged image of this corner portion, the concentration area spreads approximately 20 × 5 μm2 around the corner of the SiC chip. This APS concentration caused s-Ag layer degradation, with cracking beneath the SiC chip and local pore growth outside of the SiC during the NBT. In contrast, the APS concentration in the LP was not found. The higher APS in the LP is located at the hp layer, which is located at the boundary between the lp and hp layer. The APS level was between 0.08 and 0.12, considering the enlarged results. This APS distribution was associated with the input mechanical property relationship between the lp and hp. Since Young’s modulus in the hp is lower than that in the lp, the APS in the hp s-Ag layer preferentially deforms by the applied stress during the NBT with increasing APS. As a result, the s-Ag in the hp entirely deforms to avoid the local APS concentration at the corner of the edge. This mild APS distribution contributed to avoiding damage in the s-Ag layer during the NBT.
To consider the CCM difference between the FP and LP quantitively, the average APS per cycle was compared in the local region, as is defined in Figure 6b. Figure 8b shows the bar graph of the average APS per cycle. The fill difference represents the difference in the average area of the inner and outer regions. The filled and hatched black refer to the average inner and outer areas of the SiC chip, respectively. For the FP, the value in the inner region is 0.032, which is approximately 1.5 times higher than that in the outer region. Since the FP’s s-Ag experienced plastic strain accumulation at this level during the applied force during the NBT, a crack inside the die layer was caused after 100 cycles of the NBT. In addition, this APS value level of 0.032 caused a CCM degradation during the NBT, which was confirmed by our previous results in which the CCM degradation ratio was 12% after 600 cycles of the NBT [31]. Therefore, the FEA result effectively reflects the CCM behavior and that the cracking of the s-Ag layer preferentially progressed inside the SiC chip during the NBT. In contrast, for the LP, the value relation between the inner and outer areas is contrary to the FP. The average APS per cycle value in the inner region was 6.5 × 10−6, meaning that the cracking damage risk during the NBT was almost zero for the s-Ag layer inside the SiC chip. As a result, the CCM was not observed during the NBT in the LP. The average APS per cycle value at the out region was 0.019, indicating that the damage risk existed outside the SiC chip for the LP during the NBT. However, this value did not cause continuous cracking outside the s-Ag layer. We confirmed that this drastic APS distribution along the boundary between the lp and hp layer suppressed the CCM of the s-Ag layer within the SiC chip during the NBT. In the previous study of conventional methods with a vertical pore gradient, the simulation analysis was limited to an elastic model, and the strain distribution within the joint layer was found to be contained within an approximately twofold magnitude. This is in significant contrast to the dramatic APS distribution we confirmed in this study. As a result, the degradation ratio improvement in the vertical pore gradient was limited to a maximum of 5% after the TST [49].
We also considered the s-Ag pore growth caution surrounding the SiC chip during the NBT based on the average maximum principal stress (MPS) because pore growth is associated with Ag grain boundary diffusion, which is accelerated by the applied stress [59,60]. Figure 8c shows the bar graph of the average MPS. The color scheme for the graphs is identical to that in Figure 8b. For the FP, the average MPS in the inner and outer regions was 102 and 93 MPa, respectively. As discussed above, cracking preferentially occurred inside the chip due to the 1.5 times higher APS per cycle value than that at the SiC chip’s outside area. Therefore, the average MPS value of 93 MPa is a target value to discuss the possibility of pore growth in the outside area under NBT conditions. The possibility of pore growth is considered based on our previous results of the pressurized s-Ag pore growth criterion map [31]. The input value for this pore growth equation assumes that the initial pore radius is the same because the sintering condition and paste are identical to those in the previous study. The aging time was set to 150,000 s, which corresponds to the 500 cycles of the NBT. As a result, the local average MPS caused pore growth outside the s-Ag layer in the FP. For the LP, the average MPS value inside the SiC chip was 31 MPa. This value is below the pore growth criterion plane, which coincides with no microstructure change in the s-Ag layer inside the SiC chip. In contrast, the average MPS value outside the SiC chip was 15 MPa, exceeding the ultimate tensile strength of 7 MPa of the lp s-Ag (Figure 7a). The Ag grains were located separately, similarly to the discontinuous cracking during the NBT (Figure 3b).
Preferential damage occurring outside the SiC chip helps maintain the Rth, as the degradation in this region does not affect the primary thermal path originating from the SiC chip. However, potential tradeoffs include the risk of interface delamination outside the s-Ag layer. When the interface force is weak between the non-pressed s-Ag and the substrate metal, a catastrophic interface fracture may occur during reliability testing. If these cracks allow air to infiltrate the PKG, oxygen exposure can alter the material properties or weaken the local bonding at the bottom corner region, creating new stress intensity points. To mitigate this risk, applying a barrier layer, such as Al2O3, to the outermost layer of the EMC is a promising approach [61,62].

5. Conclusions

This study investigated the suppression of the CCM beneath the semiconductor die using the NBT. Two pressurized types of s-Ag assemblies were used to control the porosity in the s-Ag layer. The FP showed both failure modes of the s-Ag layer degradation of the cracking beneath the SiC chip and EMC/s-Ag delamination from 100 cycles of the NBT. In contrast, the LP showed no such degradation up to 500 cycles of the NBT. The APS distribution in the s-Ag layer illustrates this fracture mode difference. For the FP, the APS distribution was locally concentrated at the corner of the SiC chip, which acted as an APS singularity point, leading to the CCM beneath the SiC chip in the s-Ag layer. In contrast, for the LP, the applied stress preferentially deformed the hp of the s-Ag layer due to the lower stiffness compared to that in the lp s-Ag layer. As a result, if the APS is not located concentrically at the s-Ag layer, any significant CCM beneath the SiC chip in the s-Ag layer can be avoided.
In summary, from the reliability design perspective, how we intentionally construct a deformable area in the PKG structure is especially important in protecting against the unfavorable CCM, such as horizontal cracks beneath the SiC chip. In this study, when the s-Ag porosity beneath the SiC is lower than that outside the SiC chip, the s-Ag layer’s cracking beneath the SiC chip can be stopped.
For future PKG reliability designs, the APS distribution obtained by the FEA is an essential step in predicting the danger zone during reliability tests. However, we should elucidate the model configuration validation, whether it is a continuous structure or not. In particular, the interface in the PKG should be considered carefully because the interface commonly loses its perfect connection due to local defects. Elucidating the morphology and quantifying the toughness of each interface should be a priority. We will integrate the interface evaluation results and the reliability results to develop a comprehensive reliability design in PKG. Additionally, we will investigate the different combinations of PKG and reliability tests to elucidate the validity of the reliable LP potential. Our research limits the reliability evaluation to the TST mode only. However, we will also clarify the aging effect (e.g., humidity) on the degradation of the PKG to explore the potential of the LP for practical case universality.

Author Contributions

Conceptualization, K.W. and K.N.; methodology, K.W.; software, K.W.; validation, K.W.; formal analysis, K.W.; investigation, K.W., M.U., and A.S.; resources, K.W., M.U., and A.S.; data curation, K.W.; writing—original draft preparation, K.W.; writing—review and editing, K.W. and K.N.; visualization, K.W.; supervision, K.N.; project administration, K.W. and K.N. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Data Availability Statement

The original contributions presented in this study are included in the article. Further inquiries can be directed to the corresponding author.

Conflicts of Interest

All authors are employed by the company ROHM Co., Ltd. and they declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

Abbreviations

CCMCohesive cracking mode
IDMInterface delamination mode
s-AgSintered silver
hpHigh-porosity
lpLow-porosity
FPFull press
LPLocal press
DAAsDie-attached assemblies
WBGWide band gap
SiCSilicon carbide
NBTNine-point bending test
TSTThermal shock test
APSAccumulated plastic strain
PKGPackaging
EMCEpoxy molding compounds
CTECoefficients of thermal expansion
RthThermal resistance of the PKG
rthRth increase ratio
SATScanning acoustic tomography
2DTwo dimensional
FEAFinite element analysis
BSEBackscattering elecron
SEMScanning electron microscopy
S–SStress–strain
YSYield stress
MPSMaximum principal stress

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Figure 1. A schematic of the experimental procedure along with bird-view SEM images after the die bonding process.
Figure 1. A schematic of the experimental procedure along with bird-view SEM images after the die bonding process.
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Figure 2. (a) Scanning acoustic tomography images of the FP and LP after the NBT. (Red frame: die area. Darker color: bonded area. Lighter color: degradation area.) (b) Numerical analysis results with the degradation ratio after 500 cycles of the NBT in the FP and LP. The bar graph shows the FP results of the degradation ratio after 500 cycles to illustrate the full data variability, representing the maximum and minimum values.
Figure 2. (a) Scanning acoustic tomography images of the FP and LP after the NBT. (Red frame: die area. Darker color: bonded area. Lighter color: degradation area.) (b) Numerical analysis results with the degradation ratio after 500 cycles of the NBT in the FP and LP. The bar graph shows the FP results of the degradation ratio after 500 cycles to illustrate the full data variability, representing the maximum and minimum values.
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Figure 3. Cross-sectional SEM images for (a) FP and (b) LP at initial state and after 100 and 500 cycles of NBT. (First line: overall image. Second line: enlarged image near SiC chip. Third line: microporous structure of s-Ag within blue square region in second-line images. Fourth line: enlarged area at EMC/s-Ag. Fifth line: reinforced edge image of forth-line images.)
Figure 3. Cross-sectional SEM images for (a) FP and (b) LP at initial state and after 100 and 500 cycles of NBT. (First line: overall image. Second line: enlarged image near SiC chip. Third line: microporous structure of s-Ag within blue square region in second-line images. Fourth line: enlarged area at EMC/s-Ag. Fifth line: reinforced edge image of forth-line images.)
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Figure 4. An enlarged view of cross-sectional SEM images around the side SiC chip for the FP and LP after 100 cycles of the NBT. Top-line images indicate the reinforced edge images. (Purple line: edge line.).
Figure 4. An enlarged view of cross-sectional SEM images around the side SiC chip for the FP and LP after 100 cycles of the NBT. Top-line images indicate the reinforced edge images. (Purple line: edge line.).
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Figure 5. The differences between the FP and LP in terms of the pressing area control methodology, achievable porosity gradient, and CCM degradation within the SiC chip during the NBT, considering the obtained results.
Figure 5. The differences between the FP and LP in terms of the pressing area control methodology, achievable porosity gradient, and CCM degradation within the SiC chip during the NBT, considering the obtained results.
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Figure 6. (a) The simulation model configuration and boundary condition. (Red frame: the enlarged view of the edge around the SiC chip.) (b) The mesh condition along with an enlarged mesh view to illustrate the numerical analysis region.
Figure 6. (a) The simulation model configuration and boundary condition. (Red frame: the enlarged view of the edge around the SiC chip.) (b) The mesh condition along with an enlarged mesh view to illustrate the numerical analysis region.
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Figure 7. (a) S–S curves for lp and hp s-Ag at 150 °C along with bilinear fitting line and coefficients in lp and hp s-Ag. (b) Input mechanical properties for FEA.
Figure 7. (a) S–S curves for lp and hp s-Ag at 150 °C along with bilinear fitting line and coefficients in lp and hp s-Ag. (b) Input mechanical properties for FEA.
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Figure 8. (a) FEA results of the APS distribution at three cycles of the s-Ag layer along with the FP and LP model. A bar graph of the (b) average APS per cycle and (c) the average MPS at the evaluated area.
Figure 8. (a) FEA results of the APS distribution at three cycles of the s-Ag layer along with the FP and LP model. A bar graph of the (b) average APS per cycle and (c) the average MPS at the evaluated area.
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Table 1. Detailed experiment conditions, including tester or material and their specification or conditions.
Table 1. Detailed experiment conditions, including tester or material and their specification or conditions.
StepTester or MaterialSpecification or condition
1Nano silver paste (commercial product)- 18 nm in diameter
1Carbon sheet (TOYO TANSO, VVF30, Osaka, Japan)- FP: 20 mm square, LP: 4.8 mm square, thickness: 1.6 mm
1Uniaxial press machine (SHINTOKOGIO, Ltd., CYPM-200, Aichi, Japan)- 60 MPa pressure for 10 min at 300 °C
2EMC (commercial product)- Silica filler 88 wt% (20 nm–40 μm in diameter)
- Biphenyl type epoxy resin
2Compression molding machine (TOWA, CPM-1080, Kyoto, Japan)- 13.8 MPa pressure
- Cure: 2 min at 165 °C
2Thermal chamber (ESPEC, ST-120, Osaka, Japan)- Air atmosphere
- Post-mold cure: 5 h at 175 °C
3Laser marker (KEYENCE, MD-U1000C, Osaka, Japan)- Ultraviolet laser (λ = 355 nm) of Gaussian beam profile
4Universal test system (Instron Japan, 68TM-5, Kanagawa, Japan)- In air atmosphere at 150 °C
- Force control (0 and 270 N under triangle waveform)
- 500 cycles
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MDPI and ACS Style

Wakamoto, K.; Ukita, M.; Saito, A.; Nakahara, K. Suppression of Cohesive Cracking Mode Based on Anisotropic Porosity in Sintered Silver Die Attach Encapsulated by Epoxy Molding Compounds. Electronics 2025, 14, 3227. https://doi.org/10.3390/electronics14163227

AMA Style

Wakamoto K, Ukita M, Saito A, Nakahara K. Suppression of Cohesive Cracking Mode Based on Anisotropic Porosity in Sintered Silver Die Attach Encapsulated by Epoxy Molding Compounds. Electronics. 2025; 14(16):3227. https://doi.org/10.3390/electronics14163227

Chicago/Turabian Style

Wakamoto, Keisuke, Masaya Ukita, Ayumi Saito, and Ken Nakahara. 2025. "Suppression of Cohesive Cracking Mode Based on Anisotropic Porosity in Sintered Silver Die Attach Encapsulated by Epoxy Molding Compounds" Electronics 14, no. 16: 3227. https://doi.org/10.3390/electronics14163227

APA Style

Wakamoto, K., Ukita, M., Saito, A., & Nakahara, K. (2025). Suppression of Cohesive Cracking Mode Based on Anisotropic Porosity in Sintered Silver Die Attach Encapsulated by Epoxy Molding Compounds. Electronics, 14(16), 3227. https://doi.org/10.3390/electronics14163227

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