Impact of Charge Carrier Trapping at the Ge/Si Interface on Charge Transport in Ge-on-Si Photodetectors

Abstract

The performance of optoelectronic devices is affected by various noise sources. A notable factor is the 4.2% lattice mismatch at the Ge/Si interface, which significantly influences the efficiency of Ge-on-Si photodetectors. These noise sources can be analyzed by examining the impact of the Ge/Si interface and deep traps on dark and photocurrents. This study evaluates the impact of these charge traps on key photodetector performance metrics, including responsivity, photo-to-dark current ratio, noise equivalent power (NEP), and specific detectivity (D^*). The trapping effects on charge transport under both forward and reverse bias conditions are monitored through hysteresis analysis. When illuminated with an unmodulated 1550 nm laser, all the key performance metrics exhibit maximum variations at a specific reverse bias. This critical bias marks the transition from saturated to exponential charge transport regimes, where intensified electric fields enhance trap-assisted recombination and thus maximize metric fluctuations.

1. Introduction

Germanium-on-silicon (Ge-on-Si) photodiodes (PDs) are crucial components in Si photonics-based applications, such as sensing, communication, and optical interconnections. These devices are highly valued due to their low cost and compatibility with complementary metal-oxide-semiconductor (CMOS) technology, making them suitable for integration into modern electronic systems [1,2,3,4,5,6,7,8,9]. Furthermore, Ge-on-Si PDs, as CMOS-compatible devices, play an essential role in photonically-enabled application-specific integrated circuits (ASICs). Leading industry players, such as Intel and IBM, have successfully fabricated monolithic photonic integration modules and products featuring Ge-on-Si PDs, demonstrating their practical applicability in cutting-edge technologies [10,11,12,13,14].

Despite their advantages, Ge-on-Si PDs face a significant challenge due to the 4.2% lattice mismatch between Ge and Si [15,16,17]. This mismatch leads to the formation of high-density misfit dislocations at the Ge/Si interface, as well as threading dislocations within the Ge epitaxial layers [18,19,20]. As a result, in the early stages of development, the silicon layer was primarily used as a substrate, while PDs were fabricated exclusively within the Ge material, avoiding the Ge/Si material interface [21]. However, advancements in Ge epitaxial technology have enabled the development of Ge-on-Si heterojunction PDs that utilize the Si layer as a substrate and contact layer. These advancements have led to extensive research and widespread use of Ge-on-Si PDs [22,23,24,25,26].

Among various Ge-on-Si heterojunction PDs, the vertical p⁺(Ge)-i(Ge)-n⁺(Si) heterojunction structure has garnered significant attention. This configuration has been extensively studied and utilized in the development of high-speed PDs, demonstrating promising performance characteristics [27,28,29,30]. However, due to the high density of misfit dislocations at the Ge/Si interface, trap-assisted tunneling at the interface (J_int) significantly elevates the generation-recombination current. Additionally, the narrower bandgap of Ge amplifies the bulk Shockley–Read–Hall (SRH) process, further increasing the SRH-dominated generation-recombination current (J_SRH) in comparison with III–V PDs [31]. As a result, the dark current in a vertical p⁺(Ge)-i(Ge)-n⁺(Si) PD (44.1 mA/cm²) is significantly higher than that in commercial III–V PDs (15.2 µA/cm²) [32]. Similarly, the impact of interface effects on the dark current density has also been reported in vertical p⁺(Ge)-i(Ge)-n⁺(Si) PDs fabricated on silicon-on-insulator (SOI) substrates. To better understand the sources of dark current and identify major noise contributors, ideality factors and activation energies are employed in the analysis [33].

In Ge-on-Si PDs, trap activation is significantly influenced by the pulse rate of the applied electrical stress. Deep traps, located farther from the conduction and valence bands, contribute to recombination and dark current, degrading device performance, while shallow traps affect temporal response and efficiency. Higher pulsing rates increase the activation of deep traps, leading to reduced sensitivity and gain, whereas shallow traps introduce signal distortion and timing noise. Reverse bias alters the internal electric field, shifting trap energy levels and accelerating carriers, which can exacerbate trap-assisted recombination and dark current. The combined effects of pulsing rate and bias stress reduce device gain, linearity, and timing resolution, while increasing noise and jitter, underscoring the need for optimizing trap dynamics in Ge-on-Si PDs for high-speed, low-noise applications. Moreover, deep and surface traps in Ge-on-Si photodetectors can be purposefully utilized to improve performance in specific applications. Deep traps store charge for memory elements in neuromorphic computing, while surface traps modulate response time and sensitivity. Optimizing trap characteristics can enhance responsivity, reduce noise, and create novel architectures. However, careful engineering is required to avoid inefficiencies caused by excess traps. Applications include neuromorphic computing, high-speed imaging, and optical communication. Optimization methods involve trap engineering, surface passivation, temperature control, and tailored device geometries, supported by real-time feedback mechanisms. These affordable PDs can be integrated into silicon photonic platforms, making them ideal for applications needing high-sensitivity detectors at 1550 nm. These are adaptable for free-space sensing, LiDAR, adaptive optics, and imaging, and also meet the needs of autonomous driving and weak light detection.

This study focuses on the fabrication and characterization of a lateral Ge-on-Si PD with specific structural dimensions, namely, a multiplication width (W_M) of 1 µm and an absorption width (W_A) of 0.3 µm. This paper presents an experimental analysis of the effects of interface traps on charge transport within the device, while modelling of these effects has already been reported [34]. Key performance metrics such as responsivity, specific detectivity (D^*), normalized photo-to-dark current ratios, and noise equivalent power (NEP) are evaluated. These metrics provide clear insights into how interface traps influence charge transport under both dark and unmodulated illumination conditions using a 1550 nm wavelength laser.

The structure of this paper is organized as follows. Section 2 describes the fabrication processes utilized in developing the devices. Section 3 provides a detailed explanation of the measurement scheme and discusses the physical mechanisms that influence the results obtained from our lateral Ge-on-Si PD. In Section 4, we present the current-voltage (I-V) characteristics of the devices under varying bias conditions and continuous 1550 nm illumination, alongside an evaluation of key performance metrics. Finally, the conclusions of our study are summarized in Section 5.

2. Experimental Details

The structure of the employed lateral Ge-on-Si PD is shown schematically in Figure 1. The device is designed using separate-absorption-charge-multiplication (SACM) configuration. This design builds upon previously developed P-I-N PDs integrated within Si photonics platforms [35]. A key advantage of this approach lies in the monolithic integration of the PD with other optoelectronic components on the platform, supporting complex chip-scale optical circuits.

A p-type charge layer with a doping concentration of 1.0 × 10¹⁸ cm⁻³ is implanted in the Si layer to isolate the multiplication region from the Ge-absorber, while maintaining a low electric field profile in the Ge layer to prevent breakdown. Selective epitaxy of the Ge absorber is performed on the underlying p-implanted Si charge layer in a non-overlapping configuration. The absorber receives optical input from a Si end-fire waveguide. The Ge contact is formed by boron difluoride (BF₂) implantation, achieving a heavily doped p⁺⁺ layer with a doping concentration of 1 × 10²⁰ cm⁻³. The Si contact is fabricated via a heavily doped n⁺⁺ layer, implanted prior to Ge epitaxial growth. The Si-based multiplication regions (doped at 1 × 10¹⁵ cm⁻³) have a width of 1 µm. The doping concentrations in the p-Si and i-Ge regions were specifically chosen to engineer a sharp drop in the electric field at their interface. This controlled field profile is essential for enhancing and isolating the charge carrier trapping effects at the Ge/Si interface—the primary focus of this study—as it creates a localized region where carrier motion is slowed and confined, enhancing their interaction with interface trap-states. In this study, the resulting trapping behaviour is then quantified in Section 4 through hysteresis analysis in charge transport measurements. The device employs a symmetrical design with bilateral metal–Si contacts, which is significant for the electric field configuration.

The electrical circuitry for measuring the current (I) through the SACM-configured PD is also shown. A Keithley 4200A-SCS Waveform Analyzer provides the AC input signal (V) and records the corresponding current through the device. Testing was performed under low-bias conditions (−2 V to 1 V) using unmodulated illumination from a 1550 nm laser at various intensities. The inset depicts the ready-for-testing packaged module, which is prepared after the device fabrication to facilitate electrical measurement.

3. Physical Mechanisms

In a PD, deep traps can increase carrier recombination rates, reducing photocurrent at higher bias voltages. Surface traps, on the other hand, can introduce additional energy levels within the bandgap, impeding carrier transport and resulting in hysteresis or shifts in the I-V curve, especially during reverse bias sweeps. The presence of these traps typically leads to non-ideal device characteristics, such as reduced efficiency and increased dark current, which can be analyzed with changes in the slope and shape of the I-V curve. To mitigate these effects, various strategies such as careful material selection, surface passivation, device structure optimization, doping density tailoring, thermal management, and electric field engineering can be implemented.

The trapping sources and sites examined in this study are generated during the fabrication of the employed lateral Ge-on-Si PD. To specifically probe the dynamic charge trapping/detrapping behaviour, our measurement protocol (detailed in Section 2) employs deliberate forward (from −2 V to 1 V) and reverse (from 1 V to −2 V) bias sweeps at multiple illumination intensities. This bidirectional voltage scanning is designed to: (i) induce hysteresis loops by altering the filling states of traps during voltage ramping; (ii) reveal trap-dependent charge transport asymmetries between increasing and decreasing electric field conditions, particularly near the critical transition bias between exponential and saturated regimes; and (iii) quantify trap influence through maximum variations in key performance metrics. The resulting hysteresis signatures directly correlate with the density and response times of interface and deep traps, as will be shown in the analysis of I-V characteristics and figures of merit under varying illumination (Section 4). The epitaxial growth of a thin Ge film on less expensive and readily available Si substrates, as exemplified in this study, is primarily motivated by the need for a cost-effective solution for the integration of Ge into electronic devices. This Ge-on-Si solution is particularly crucial for enhancing the spectral performance of Si, especially given the anticipated co-integration of additional Si-based components—such as dynamic random-access memory and non-volatile memory—on the same chips. However, a major challenge in integrating Ge with Si is the significant lattice mismatch between the two materials, compounded by discrepancies in their thermal expansion coefficients. This lattice mismatch induces substantial strain energy accumulation within the Ge layers epitaxially grown on Si, which is primarily relieved through two mechanisms: (i) the formation of interfacial lattice dislocations (misfit dislocations) and (ii) elastic deformation of both the substrate and Ge islands formed on the surface during the initial growth stages, following the Stranski–Krastanow growth mode [36]. Typically, elastic deformation alone cannot fully accommodate the induced strain, leading to the nucleation of misfit dislocations at island edges [37]. Many of these dislocations tend to bend towards the growth direction, and propagate (or thread) to the surface during the growth process as illustrated in Figure 2a. The existence of these threading dislocations substantially degrades charge transport properties by reducing carrier mobility and shortening carrier lifetime. Consequently, it is necessary to develop strategies that can more effectively align the lattice constants of Ge and Si. Graded SiGe buffer layers effectively transition lattice constants, while thermal annealing promotes dislocation glide and annihilation. Optimizing epitaxial growth processes, such as low-temperature initiation and advanced techniques like molecular beam epitaxy, further improves crystal quality. Techniques like aspect ratio trapping confine dislocations within patterned trenches, and defect etching with passivation reduces active recombination centers. Multi-step growth processes and strain relaxation layers minimize defect propagation, while hydrogenation passivates threading-dislocation-related dangling bonds. Moreover, high-Ge-content virtual substrates or thick relaxed Ge buffers serve as pseudo-substrates, reducing threading dislocations density in the active layer. Combining these approaches can enhance PD performance while balancing application requirements and fabrication constraints [38,39,40,41,42,43,44,45,46,47].

For a specific APD, the total current (I) flowing through it comprises the dark current (I_dark) and the photocurrent (I_pc), so it can be expressed as I = I_dark + I_pc. Here, I_pc is attributed to photogenerated carriers, while I_dark is the cumulative result of six primary current components [33]: (i) diffusion current (I_dif), (ii) generation-recombination current governed by SRH (I_SRH), involving recombination within the bulk semiconductor, (iii) generation-recombination current enhanced by trap-assisted tunnelling at the Ge/Si layer interface (I_int), (iv) band-to-band tunnelling current (I_btb), (v) avalanche multiplication current (I_ava), occurring under high electric fields, and (vi) parasitic shunt resistance current (I_shunt).

It is important to note that I_btb and I_ava are generated at electric fields >3 × 10⁵ V/cm, which corresponds to a working voltage exceeding −21 V for the studied devices. Meanwhile, I_shunt is defined as I_shunt = V/R_s, where the shunt resistance (R_s) is typically around 10¹¹ Ω, rendering I_shunt negligible in this context [48]. Consequently, the dominant dark current components are I_dif, I_SRH, and I_int, as illustrated in Figure 2b,c. The principle of dissipative transition energy conservation further suggests that the electron capture rate into neutral electron traps increases for trap energy levels closer to the conduction band edge. Similarly, the hole capture rate into neutral hole traps is expected to be higher for trap energy levels closer to the valence band edge [49].

4. Results and Discussion

Threading dislocations and Ge/Si interface traps degrade the performance of Ge-on-Si PDs by impairing carrier generation, transport, and collection. Threading dislocations act as non-radiative recombination centers, reducing carrier lifetime and generation efficiency, while Ge/Si interface traps capture carriers, facilitating SRH recombination. Both defects impede carrier transport and collection through scattering, trap-state assisted leakage, and electric field distortion, leading to reduced quantum efficiency and increased dark current.

Figure 3 displays the dark and photocurrent characteristics of a lateral Ge-on-Si PD under unmodulated 1550 nm illumination. In low biasing regimes, the carrier multiplication is absent, and therefore responsivity is always less than 1. Across all illumination conditions, the I-V curves exhibit an open-circuit voltage (V_oc), a signature characteristic commonly observed in PDs and often enabling photovoltaic applications. Distinct hysteresis effects appear in both dark and photocurrent measurements during forward (−2 to 1 V) and reverse (1 to −2 V) bias sweeps, recorded at illumination powers of (0.668, 5.21, 10.55, 25.7, 47.6) mW/µm². These non-overlapping current signatures directly reflect the impact of traps on charge transport within the device, which is the core focus of this study. Specifically, the hysteresis arises from (i) asymmetric filling/emptying of interface trap states during voltage ramp directions, (ii) trap-induced delays in carrier release under reverse-bias conditions, and (iii) field-dependent modulation of trap occupancy at the interface. Although hysteresis persists throughout the entire bias range, the maximum current deviation occurs at specific reverse potentials, beyond which the photocurrent approaches saturation. The figures of merit presented in the subsequent discussions also show maximum changes at these potentials. The observed reverse potentials of −(0.32, 0.56, 0.71, 0.935, 1.235) V are inherently determined by the photogenerated charge density, electric field intensity, and charge release/trapping concentrations.

Another notable observation is the distinguishable photo-response in the forward-biased regime. Typically, PDs are probed under reverse bias to establish a space charge (depletion) region, which is essential for drifting photogenerated carriers and suppressing electron-hole recombination during charge transport. In this study, the forward-biased photo-response is attributed to the interaction between light-assisted carrier trapping/release (detrapping) and recombination rates. On one hand, photon energy promotes carriers trapped at interface states back into bands, increasing available charge carriers. On the other hand, the collapsed depletion region allows higher carrier density, accelerating SRH recombination via trap defects, reducing net photocurrent. Although the forward-biased photo-response exhibits both a direct correlation with illumination power (P) and hysteresis behaviour, it will not be utilized for quantifying changes in the PD’s figures of merit.

Figure 4 presents another important figure of merit, the normalized photo-to-dark current ratio (NPDR), which is obtained by normalizing the I_pc/I_dark ratio with respect to the input P. The NPDR is valuable for enabling direct comparison of responsivity and external quantum efficiency among different detectors under a given I_dark. Figure 4a plots the NPDR as a function bias voltage for both forward (−2 to 1 V) and reverse (1 to −2 V) sweeps, while the inset presents a closer view of the NPDR curves at minimum (0.668 mW/µm²) and maximum (47.6 mW/µm²) illumination intensities. The curves display hysteresis effects similar to those in responsivity and current. Figure 4b quantifies the maximum variations in NPDR (ΔNPDR), with values of (1.5, 1.126, 1.19, 1.14, 1.26) × 10⁵ W⁻¹ occurring at reverse bias voltages of −(0.365, 0.635, 0.77, 1.025, 1.25) V. Here, the maximum variation is defined as the maximum distance between forward and reverse biasing curves at identical voltage points, and the corresponding voltage at which this maximum occurs for the reverse bias points we mentioned above. It is the same way to define the maximum variations and the corresponding bias potentials for the other figures-of-merit with hysteresis in the subsequent contents. This hysteresis-induced ΔNPDR originates from the dynamic interplay among trap density, photogenerated carrier concentration, and established electric field distribution, which can be leveraged to modulate PD sensitivity for specific applications.

It is found that the NPDR curves at illumination intensities of (0.668, 5.21, 10.55, 25.7, 47.6) mW/µm² closely resemble the corresponding I_pc/I_dark curves in Figure 5. This similarity essentially stems from NPDR being the scaled form of I_pc/I_dark by P or equivalently, the transformation of R scaled by I_dark, as demonstrated by the following relationship:

$$NPDR={\displaystyle \frac{I_{\mathrm{p}\mathrm{c}}/I_{\mathrm{d}\mathrm{a}\mathrm{r}\mathrm{k}}}{P}}={\displaystyle \frac{I_{\mathrm{p}\mathrm{c}}/P}{I_{\mathrm{d}\mathrm{a}\mathrm{r}\mathrm{k}}}}={\displaystyle \frac{R}{I_{\mathrm{d}\mathrm{a}\mathrm{r}\mathrm{k}}}}$$

(1)

This metric quantifies the device sensitivity per unit dark current, and it enables direct comparison of responsivity between devices with different I_dark levels, isolating the impact of I_dark on signal-to-noise performance. Additionally, it provides a fundamental efficiency measure where higher NPDR values indicate superior ability to convert optical input into useful signal despite trap-induced dark current limitations.

In addition, we evaluate the noise-equivalent power (NEP) via $NEP= {\displaystyle \frac{\sqrt{2e{I}_{\mathrm{d}\mathrm{a}\mathrm{r}\mathrm{k}}}}{R}}$. This formulation assumes dark current shot noise is the dominant noise source in a 1 Hz noise-equivalent bandwidth, which holds for our low-bias conditions where I_btb, I_ava, and I_shunt are negligible. NEP defines the minimum detectable optical power for SNR = 1, with lower values indicating higher sensitivity. It is the reciprocal of detectivity and typically exhibits an inverse relationship with the other figures of merit analyzed in this study. Here, the NEP value is defined per unit bandwidth, and this normalization allows direct comparison of sensitivity across different detectors.

Figure 5a illustrates the NEP values under forward (−2 to 1 V) and reverse (1 to −2 V) bias sweeps. The inset provides a closer view of the NEP curves under 0.668 mW/µm² and 47.6 mW/µm² illumination intensities. The forward and reverse sweep curves display the same type of hysteresis observed in previous sections. The maximum variations in ΔNEP, occurring at reverse bias potentials of −(0.365, 0.645, 0.77, 1.025, 1.295) V, are shown in Figure 5b, with corresponding values of (1.727, 1.426, 1.204, 0.967, 0.687) × 10⁻¹¹ $\mathrm{W}/\sqrt{\mathrm{H}\mathrm{z}}$.

For the studied Ge-on-Si PD, although the NEP decreases (i.e., improves) with enhanced illumination—indicating an increase in the SNR—the minimum NEP of ~10⁻¹¹ $\mathrm{W}/\sqrt{\mathrm{H}\mathrm{z}}$, achieved at a maximum illumination of 47.6 mW/µm², remains higher than contemporary state-of-the-art PDs. This elevated NEP can be attributed to the presence of excessive noise sources, particularly deep-level and interface traps, which induce hysteresis in the charge transport dynamics showing non-overlapping current curves during the forward and reverse bias sweeps.

A high specific detectivity (D^*) is desirable for an effective PD, and it is plotted in Figure 6. For a specific I_dark, D^* is calculated using the formula $D^{*}=\sqrt{A∆f}D={\displaystyle \frac{\sqrt{A∆f}R}{\sqrt{2e{I}_{\mathrm{d}\mathrm{a}\mathrm{r}\mathrm{k}}}}}={\displaystyle \frac{\sqrt{A∆f}}{NEP}}$, where A is the PD area (50 μm × 50 μm). The unnormalized detectivity D is directly related to other figures of merit such as R, NPDR, and I_pc/I_dark. Particularly, it can be derived by scaling the NPDR with $\sqrt{{\displaystyle \frac{I_{\mathrm{d}\mathrm{a}\mathrm{r}\mathrm{k}}}{2e}}}$ or translating R through $\sqrt{{\displaystyle \frac{1}{2e{I}_{\mathrm{d}\mathrm{a}\mathrm{r}\mathrm{k}}}}}$. In Figure 6, specific detectivity exhibits a sub-linear direct relationship with P. This behaviour is attributed to the saturation effects and the lack of internal gain (carrier multiplication) owing to the low biasing condition of our lateral Ge-on-Si PD. Furthermore, internal trapping mechanisms show impact on D^*, as evidenced by the hysteresis observed in both forward and reverse bias sweeps in Figure 6a. The maximum variations in specific detectivity (ΔD^*) achieved under unmodulated illumination intensities of (0.668, 5.21, 10.55, 25.7, 47.6) mW/µm² are presented in Figure 6b, with values of (3.49, 3.014, 3.322, 3.415, 4.08) × 10¹² Jones measured at reverse bias potentials of −(0.365, 0.645, 0.77, 1.025, 1.295) V. The interplay between the electric field and photocharge density defines the voltage range within which the charge transport exhibits saturation in current values.

Finally, Figure 7 illustrates the interplay between deep and interface trap effects on the overall photo-response of the studied Ge-on-Si PD. Figure 7a shows the differential current (evaluated by subtracting the dark current from the total measured current) under a fixed reverse bias of −2 V and pulsed 1550 nm laser illumination (intensity = 1 mW/µm², on/off frequency = 100 kHz). A mechanical chopper modulating (blocking or allowing) the laser beam was maintained at 4 kHz for these measurements. The laser pulses were separated by a duration of 10 µs for all the implemented chopper frequencies (0.1, 0.5, 1, 2, 3, and 4 kHz).

The decay rate of the fast component (cyan background) can be expressed as a function of intrinsic device parameters, while the slower decay trend (green background) is attributed to interface traps. These traps cause signal jitter and noise due to their relatively rapid trapping and detrapping dynamics. The inset depicts a good fitting of the device transient photo-response during the laser off-time, employing a double exponential decay function:

$$y=y_0+A_1\mathrm{e}\mathrm{x}\mathrm{p}(-(x-x_0)/t_1)+A_2\mathrm{e}\mathrm{x}\mathrm{p}(-(x-x_1)/t_2)$$

(2)

The transient differential photo-response obtained from the device against all chopper frequencies follows the same curve fitting formulation, with fitting parameters (y₀, A₁, A₂, t₁, and t₂) showing clear dependence on chopper frequency. Based on the fitting results and the observation in Figure 7b, the surface traps stochastically capture and release carriers on microsecond timescales, introducing uncertainty in carrier transit time; this fluctuation in trap occupancy delay carrier collection, causing temporal variations in photocurrent rise/fall edges (signal time jitter), is also shown by Figure 7c. Meanwhile, the continuous and random capture/release process via interface traps generates generation-recombination noise, especially at higher chopper frequencies. The differential current trace in Figure 7a exhibits a quasi-sinusoidal modulation, originating from the activation of deep traps that perturb the current signature over timescales longer than the individual laser pulses. This behaviour arises because the pulsed illumination duration is shorter than the time required for the device to reach full saturation after each pulse.

Figure 7c shows the differential current as a function of normalized time across various chopper frequencies. The slow transient decay region (highlighted by green background in the inset of Figure 7b) is crucial for evaluating the contribution of interface traps, which influence both the speed and frequency response of the device. The interface (surface) traps with their faster (μs timescale) trapping/detrapping dynamics act as the shot noise source. On the other hand, deep traps exhibit much slower response due to long carrier emission times (ms timescale). The quasi-sinusoidal modulation observed in Figure 7a,c corresponds to the effect of deep traps, which reduce the photocurrent through enhanced electron-hole recombination, thereby compromising the device photosensitivity. Notably, the differential current at 0.1 kHz chopper frequency is three to four times smaller than that observed at 4 kHz. This difference arises because deep traps, characterized by slower detrapping dynamics, become increasingly significant at lower chopper frequencies.

Figure 7d presents the power spectral density (PSD) derived by applying a fast Fourier transform (FFT) to the curves of differential current versus time. The observed increase in PSD with increasing chopper frequency stems primarily from the growing contribution of interface traps. At higher chopper frequencies (>1 kHz), the short laser pulse intervals prevent the device from reaching saturation due to insufficient time, and suppresses the effects of deep traps that require longer timescales to fully activate. Therefore, the interface (surface) traps are the primary noise source, generating high-frequency noise via random carrier capture/release, directly increasing PSD. Conversely, at lower frequencies (<0.5 kHz), the activation of deep traps enhances the non-radiative SRH recombination and depletes photogenerated carriers, degrading the overall device photo-response. Interface traps contribute less to integrated noise as their fast dynamics are averaged out over low-frequency cycles. Therefore, the decreased current activity and associated scattering result in lower PSD values.

5. Conclusions

The Ge/Si interface traps are incorporated into the Ge-on-Si PD during the Ge absorber’s epitaxial growth onto the Si substrate, requiring mitigation via implementation of various techniques. These are fundamentally activated via electrical bias stress applied in the form of sharp transient pulses. In this study, we alternatively observe the reflection of these trapping sources via hysteresis in the current-voltage characteristics of the device. This involves probing the impact of trap-induced effects on charge transport under low-bias conditions. When exposed to an unmodulated 1550 nm laser, the most significant variations in performance metrics are observed at a specific reverse bias, marking the transition between saturated and exponential charge transport regimes.