Effective 8T Reconfigurable SRAM for Data Integrity and Versatile In-Memory Computing-Based AI Acceleration

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

This paper presents a highly relevant investigation into SRAM-based in-memory computing (IMC), addressing the critical von Neumann bottleneck with a novel 8T SRAM design. The research is significant for low-power AI, edge computing, and cryptography. The proposed design claims substantial performance and efficiency gains (74.81% latency reduction, 31.54% energy efficiency increase) supported by Monte Carlo simulations. The work demonstrates technical merit and tackles an important problem. The paper shows potential but necessitates major revisions to enhance its clarity, systematic structure, logical coherence, and the substantiation of its findings before it can be considered for acceptance.

 

1. In the Introduction, the authors mention that novel memory devices can serve as ideal hardware platforms for in-memory computing. The reviewer suggests that the authors appropriately expand the introduction related to memristors, as memristors demonstrate greater potential for in-memory computing comparatively. Additionally, please supplement this section with key references （ Mater. 2024, 36, 2405145）.
2. Could the authors clarify why SRAM remains the preferred IMC platform over higher-density DRAM for latency-sensitive applications, despite DRAM's 6× density advantage per transistor?
3. Given 6T SRAM's significant area overhead (6T/bit), how does its density limitation impact scalability for large-scale IMC implementations compared to denser alternatives?
4. Given the 25% transistor increase (8T vs. 6T), how does the area overhead impact cost-effectiveness in large-scale IMC deployments despite its functional advantages?
5. How was the optimal sense amplifier topology selected for this IMC implementation, considering the trade-offs between logic capability, speed, and power across the various designs presented?

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

This work is well-motivated and addresses significant bottlenecks in conventional von Neumann architectures by proposing a novel multi-logic sense amplifier (MLSA) design capable of supporting a diverse range of Boolean and arithmetic operations. The incorporation of configurable-precision MAC units, binary/ternary neural network support, and integrated error correction mechanisms is particularly innovative. Here are some points to increase the manuscript quality.

1. While the proposed design supports a wide range of operations, what is the total area overhead introduced by the multi-logic sense amplifier (MLSA) compared to standard 8T SRAM arrays, especially when integrating error correction and variable-precision MAC units?

2. The proposed design exhibits increased delay (6.05 ns) despite energy efficiency gains. Could the authors elaborate on the implications of this delay for real-time edge AI workloads, and whether dynamic frequency scaling or pipelining could mitigate this?

3. The entire evaluation is simulation-based using Cadence Virtuoso at 45nm technology. Are there plans for silicon implementation or FPGA prototyping to verify practical constraints such as thermal stability, IR drop, and layout-driven parasitics?

4. The manuscript compares against other digital SRAM-based IMC designs. How does the proposed approach fare against state-of-the-art analog IMC (e.g., RRAM and PCM-based) in terms of density, linearity, and scalability for MAC operations? I would recommend to compare the achieved results with [1] and [2].

5. The integrated Hamming-based ECC is validated with a synthetic bit error rate (BER) of 10⁻³. Have the authors considered non-uniform error distributions or burst errors, which are more likely in scaled SRAM, and how resilient is the system in such cases?

[1] 10.1109/OJSSCS.2024.3432468

[2] 10.1109/EDTM58488.2024.10511694

Author Response

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Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

This paper presents a 8T reconfigurable SRAM architecture for in-memory computing. It suffers from many drawbacks as listed below. In particular, the novelty is limited, and the presentation requires significant improvement.

1. Paragraphs are too long, degrading the readability. They need to be properly divided into multiple paragraphs.
2. It would be good to summarize the organization of the paper at the end of Section 1.
3. The fundamentals would be better to be explained with figures. Most explanations resort too much to plain texts.
4. Tables are of low readability. Adding some lines may resolve the problem.
5. 16, 17, 18, 20, 21 are not easy to read. They need to be magnified.
6. The list of references does not include old yet important works before 2020. The literature review must be enhanced.
7. It is not clear how the Hamming code is implemented. The specification of the code needs to be specified, and the details of the corresponding circuit should be disclosed.
8. Too many parts are dedicated to enumerating the prior arts. In the meantime, the proposed scheme is not clearly described and does not seem to have enough novelty.
9. The performance metrics of the proposed scheme must be extensively compared with the state-of-the-art arts in the literature.
10. The transient responses of the prior arts can be presented as well and contrasted to those of the proposed one.
11. The top-level diagram in Figs. 7 and 8 look almost the same. Should they be drawn separate?
12. More details of the AI used to improve the scheme must be given.

Author Response

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Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

Comments and Suggestions for Authors

I wish to thank the Authors for their effort in addressing all the previously raised points.

Author Response

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Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

Paragraphs need to be indented. Figures are not easy to read yet. The letters therein need to be magnified.

Author Response

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Author Response File: Author Response.pdf