A CMOS Current Reference with Novel Temperature Compensation Based on Geometry-Dependent Threshold Voltage Effects

Abstract

Next-generation smart sensing devices necessitate on-chip integration of power-efficient reference circuits. The latters are required to provide other circuit blocks with highly reliable bias signals, even in the presence of temperature shifts and supply voltage disturbances, while draining a small fraction of the overall power budget. In particular, it is especially challenging to design current references with enhanced robustness and efficiency; hence, thorough exploration of novel architectures and design approaches is needed for this type of circuits. In this work, we propose a novel CMOS-only current reference, achieving temperature compensation by exploiting geometry dependences of the threshold voltage (specifically, the reverse short-channel effect and the narrow-channel effect). This allows reaching first-order temperature compensation within a single current reference core. Implemented in 0.18 µm CMOS, a version of the proposed current reference designed to deliver 141 nA (with 377 nW of total power consumption) achieved an average temperature coefficient equal to 194 ppm/°C (from −20 °C to 80 °C) and an average line sensitivity of −0.017%/V across post-layout statistical Monte Carlo simulations. Based on such findings, the newly proposed design methodology stands out as a noteworthy solution to design robust current references for power-constrained mixed-signal systems-on-chip.

1. Introduction

In the last decade, the Integrated Circuit (IC) research community has devoted increasingly greater efforts to developing novel system-on-chip (SoC) solutions for smart sensing, biomedical monitoring, and Internet-of-Things (IoT) applications [1,2,3,4]. In this respect, recent SoC designs feature a high degree of integration between analog and digital circuits, to deploy accurate sensing, in situ data processing, and wireless communication capabilities. To enable the production of miniaturized wearable/implantable devices and sensor nodes, often supplied by ultralow-capacity batteries or energy-harvesters [5,6], minimization of power consumption has emerged as a crucial need [7,8,9,10,11,12,13]. In addition, to enable reliable operation under a variety of operating conditions, strong interest has arisen in developing low-power, robust reference circuits [14,15,16,17,18,19,20]. Correct biasing of all circuit blocks within an SoC usually relies on voltage references (VRs) and current references (CRs) integrated on the same chip.

Development of VRs began very early in the history of electronics, driven by the need for stable power supplies. Furthermore, they are routinely used with non-ratiometric voltage-mode Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs). Similarly, CRs play the same role for current-mode data converters, mainly employed in telecommunication [21] and Electrical Impedance Spectroscopy (EIS) systems [22]. Moreover, the usefulness of CRs extends to a much wider category of analog cells [23]. Indeed, the thermal noise and bandwidth performances of amplifiers are strictly related to the bias current of active devices, which can be easily derived by a single accurate reference current. In addition, relaxation oscillators based on the charging and/or discharging of capacitors by means of constant currents [24,25] are receiving an increasing interest for low-power applications, where traditional RC oscillators have become unfeasibly large. It is worth noting that, in a CMOS technology, adjusting current sources can be easily accomplished by means of digitally programmable current mirrors, avoiding the use of resistors. This property allows compensation for process spread in CRs in an arguably easier way than in VRs, while low sensitivity to temperature and supply voltage variations remain a key specification.

Compared to the VR case, temperature stabilization of CRs is currently more challenging. In both cases, the general strategy implies combining Positive-Temperature-Coefficient (PTC) and Negative-Temperature-Coefficient (NTC) quantities to accomplish first-order temperature compensation. However, in the current domain, quantities available for this purpose generally show much worse linearity with respect to temperature, typically featuring power-law behaviors (i.e., $I\propto T^{\alpha }$). Voltage-to-current conversion might be an effective solution, but resistor-based implementations are generally inconvenient, due to the large areas needed to reach low power levels and because of the typically large global process variations of integrated resistors. All things considered, the best-performing CRs presently achieve temperature coefficient (TC) values that are 1–2 orders of magnitude larger than state-of-the-art VRs. Thereby, novel temperature stabilization approaches, compliant with low-power specifications, are continuously sought for CRs.

In this work, we present a novel CMOS-only CR circuit, achieving minimal sensitivity to temperature and supply voltage variations with low area occupation. A modified Beta-Multiplier (BM) structure is proposed, improving an architecture previously reported in [26] through the addition of a new temperature compensation and a line sensitivity (LS) minimization technique. Specifically, to achieve temperature compensation, we propose exploiting dependences of the threshold voltage ($V_{th}$) to geometrical dimensions of MOS transistors to derive an NTC effect, which is useful for shaping the temperature behavior of the reference current, $I_{REF}$. Prior works mostly proposed combining the outputs of separate PTC and NTC current generators [26,27] and/or leveraged body effects [26,28,29,30,31] to modulate the temperature trend of $I_{REF}$.

Ref. [26] presented CRs based on modified BM structures where temperature dependence is shaped by means of asymmetric body effects acting on transistors of a p-type non-linear current mirror (i.e., one transistor is not affected by body effects, being biased with zero body-source voltage, $V_{BS}=0$, while the other has $V_{BS}>0$). In [30], this concept has been extended by introducing, on one branch of the non-linear mirror, transistors with and without body effects, connected in parallel, to allow for fine tuning of the temperature dependence by acting on the ratio between their transconductance factors. Forward Body-Biasing (FBB) has also been used in [29], demonstrating temperature compensation capabilities by linking the reference current to a diode-connected NMOS transistor with gate, drain, and body terminals all shorted together; however, this topology necessitates an auxiliary amplifier to close the feedback loop. The authors of [31] again relied on FBB, by biasing the body terminal of an NMOS device within a peaking CR topology using the output of a two-transistor VR; nevertheless, access to body terminals of NMOS devices is feasible only in triple-well CMOS processes.

The option of exploiting geometry-dependent threshold voltage effects in CRs has been scarcely explored, with [32] being the only reference, to the best of our knowledge, optimizing single transistor dimensions to improve the performance of a CR. In [32], a Proportional-To-Absolute-Temperature (PTAT) CR is presented, implemented as a BM structure using a triode-biased transistor as a source-degeneration element. To generate the gate voltage of the triode transistor, the authors used VR cells comprising long-channel and short-channel devices coupled together, with the aim of exploiting the geometry-related $V_{th}$ difference as a tracking factor of global process variations. Furthermore, in the context of VR design, seminal works such as [33,34] have recently introduced the concept of optimizing device ratios within Self-Cascoded MOSFETs (SCMs) to tune not only temperature dependence but also sensitivity to global process variations. Specifically, temperature dependence can be adjusted by acting on the aspect ratios, as in standard SCM-VR designs, while process sensitivity is minimized by separately optimizing channel length values. However, these approaches fundamentally differ from the one herein proposed, which aims to minimize the temperature sensitivity of a BM-CR by introducing an NTC voltage term consisting of a threshold voltage difference due to width and length imbalances within a pair of transistors; by combining this term with a PTC voltage quantity and adopting optimal weights, the temperature sensitivity of the current within the BM loop can be ultimately minimized.

Regarding LS, we introduced a technique relying on an additional circuit branch, which is able to stabilize $V_{DS}$ voltages through a negative feedback. This solution has been inspired by techniques recently used in VRs [35,36] and shares similarities with the approach used in [37] for a resistor-based peaking CR. While other works simply implemented BM structures with cascode current mirrors [32,38,39,40,41,42] or amplifier-assisted regulated mirrors [43,44], the presented solution shows great potential for enhancing immunity against $V_{dd}$ variations at the cost of a reasonably small increase in power consumption, around 12.5%.

The remainder of this paper is organized as follows: In Section 2, we introduce the proposed CR architecture and a detailed analytical model to prove its temperature compensation capability. Then, in Section 3, we validate the presented circuit techniques by means of accurate electrical simulations of a 0.18 µm CMOS design. Finally, Section 4 compares our findings with those of prior works.

2. Proposed Architecture

2.1. Current Reference Core

Figure 1 shows a simplified version of the proposed CR, including only the core circuit needed to perform temperature compensation. The complete CR architecture, comprising also auxiliary circuits for LS correction and start-up purposes, is later discussed at the end of this section. The modified BM structure of Figure 1 was first introduced in [26], with transistors $M_{3,4}$ and $M_{5,6}$ biased in strong inversion and weak inversion, respectively. In addition, in [26], transistor pairs $M_{1,2}$, $M_{3,4}$, and $M_{5,6}$ were designed with matched channel widths and lengths, while the ratios between their aspect ratios, $k={\rho }_2/{\rho }_1$, $h={\rho }_3/{\rho }_4$, and $u={\rho }_6/{\rho }_5$, were imposed by acting only on the multiplicity factors (we assume the aspect ratio of each transistor to be defined as ${\rho }_i=m_i{W}_i/L_i$, where $m_i$, $W_i$, and $L_i$ stand for the multiplicity factor, the channel width, and the channel length of $M_i$)—regarding the choice of parameters k, h, and u, the existence of a stable dc operating point of the considered circuit is ensured by the following condition: $k>\max (\sqrt{h/u},1/u)$ [26].

It is worth noting that, as far as the geometry dependences of the threshold voltage are concerned (i.e., dependences of $V_{th}$ on W and L), setting k, h, and u by only acting on the multiplicity factors implies $V_{th1}=V_{th2}$, $V_{th3}=V_{th4}$, and $V_{th5}=V_{th6}$. In these conditions, it has been shown that the branch currents have temperature trends $I\propto \mu U_T^2$, where $\mu$ is the carrier mobility of $M_{3,4}$ and $U_T$ is the thermal voltage. According to well-established models [45], the mobility temperature dependence can be expressed as $\mu \left(T\right)={\mu }_0{(T_0/T)}^{{\alpha }_{\mu }}$, where T is the absolute temperature, $T_0$ is a reference temperature, and the exponent ${\alpha }_{\mu }$ is a process-dependent parameter, typically ranging between 0.8 and 1.5 in 0.18 µm CMOS. Hence, if the CR of Figure 1 is designed with device pairs matched in terms of W and L, PTC currents are obtained. Body-effect-based techniques were introduced in [26,30] to mitigate temperature sensitivity, but such solutions would be ineffective in modern FD-SOI or FinFET technologies, often showing negligible body effects [46]. As an alternative, in this paper we show how first-order temperature compensation may be achieved also by introducing geometrical mismatch within the $M_{3,4}$ and/or $M_{5,6}$ device pairs, in the form of different W and/or L values, causing unequal threshold voltages.

2.2. Proposed Temperature Compensation

In the following, the temperature analysis of the circuit of Figure 1 is expanded to the case where $V_{th3}\ne V_{th4}$ and $V_{th5}\ne V_{th6}$. The Enz–Krummenacher–Vittoz (EKV) model [47,48] is used to model transistor behavior in both the strong-inversion (SI) and the weak-inversion (WI) regions. Assuming forward saturation conditions, we employed the following basic equations:

$$I_D=\left\{\begin{array}{cc}{I}_S\exp \left({\displaystyle \frac{|V_{GB}|-n|V_{SB}|-|V_{th}|}{n{U}_T}}\right)\hfill & \left(\mathrm{WI}\right),\hfill \\ {\displaystyle \frac{\beta }{2n}}{\left(|V_{GB}|-n|V_{SB}|-|V_{th}|\right)}^2\hfill & \left(\mathrm{SI}\right),\hfill \end{array}\right.$$

(1)

where n is the subthreshold slope factor, $\beta =\mu C_{ox}mW/L$, and $I_S=2n\mu C_{ox}{U}_T^{2}mW/L$, with $C_{ox}$ indicating the oxide capacitance per unit area. The use of the absolute values in (1) makes such equations valid to model both NMOS and PMOS. By means of straightforward calculations, hereby omitted for greater conciseness, the following relationship can be found to express current $I_1$, flowing in the left circuit branch of Figure 1:

$$I_1={\displaystyle \frac{{\beta }_3}{2n_3}}{\left[{\displaystyle \frac{|V_{th3}|-|V_{th4}|+V_{SG5}-V_{SG6}}{\sqrt{h/k}-1}}\right]}^2={\displaystyle \frac{{\beta }_3}{2n_3}}{\left[{\displaystyle \frac{\Sigma V_{th}+n_5{U}_T\ln \left(ku\right)}{\sqrt{h/k}-1}}\right]}^2,$$

(2)

$$\Sigma V_{th}=|V_{th5}|-|V_{th6}|+|V_{th3}|-|V_{th4}|.$$

(3)

In these relationships, only systematic threshold voltage differences due to geometry-dependent effects are taken into account, while random mismatch errors are not included in the analysis. Referring to (2), it is worth noting that, if $\Sigma V_{th}=0$, the aforementioned $\propto \mu U_T^2$ trend is indeed obtained for $I_1$. Conversely, if $M_3$ and $M_4$ (and/or $M_5$ and $M_6$) have unequal threshold voltages, such that $\Sigma V_{th}$ is positive and decreasing with temperature, first-order temperature compensation is made possible after optimization of the slope of $n_5{U}_T\ln \left(ku\right)$. To generate the required $V_{th}$ differences, we propose leveraging geometry dependences of $V_{th}$, as explained later. However, prior to presenting more detailed theoretical analyses, a qualitative illustration of the proposed temperature compensation is given in Figure 2. Once transistor pairs $M_3$-$M_4$ and/or $M_5$-$M_6$ are sized to achieve positive $\Sigma V_{th}$, the slope of the PTAT term $n_5{U}_T\ln \left(ku\right)$ can be adjusted by acting on the k or u ratio between the aspect ratios of matched transistors. By reaching an optimal slope value for the overdrive voltage of $M_3$, [proportional to $V_{od3}=\Sigma V_{th}+n_5{U}_T\ln \left(ku\right)$], the temperature behavior of mobility, appearing within the transconductance factor ${\beta }_3$ in (2), can be compensated, leading to $I_{REF}$ with first-order temperature compensation.

Moving the discussion to the method used to generate the $\Sigma V_{th}$ term, Figure 3 illustrates the variation of $|V_{th}|$ as a function of W and L for a PMOS transistor of a commercial 0.18 µm CMOS process. The reported trends were obtained by means of Spectre simulations of device models provided by the silicon foundry. After initial non-monotonic behavior around small device dimensions, $|V_{th}|$ undergoes considerable reduction as both W and L increase, due to the narrow-channel effect (NCE) [49] and the reverse short-channel effect (RSCE) [50]. While many concurrent factors may contribute to determine such trends, which are highly dependent on the specific transistor type and manufacturing process, NCE is generally due to the fact that, as channel width narrows, the depletion region partially extends beyond the gate edges, particularly where the gate crosses the field oxide, increasing the threshold voltage at small W values. On the other hand, the RSCE is a consequence of halo implants, performed in several CMOS processes to counteract the short-channel effect (SCE) [51]. Halo implants create localized increases in dopant concentration near the source and drain regions, causing increased $V_{th}$ as L decreases [50]. Then, referring to (2)−(3), $\Sigma V_{th}>0$ may be achieved by designing $M_3$ (and/or $M_5$) with short and/or narrow channels, while $M_4$ (and/or $M_6$) should be sized with long and/or wide channels.

Concerning the temperature dependence of $\Sigma V_{th}$, its TC can be expressed as follows:

$${\alpha }_{\Sigma V_{th}}={\alpha }_{Vth5}-{\alpha }_{Vth6}+{\alpha }_{Vth3}-{\alpha }_{Vth4},$$

(4)

where ${\alpha }_{Vth3–6}$ are the TCs of $|V_{th3–6}|$, according to the following temperature model [45]:

$$|V_{th}\left(T\right)|=|V_{th}\left(T_0\right)|+{\alpha }_{Vth}(T-T_0).$$

(5)

The threshold voltage of MOS transistors notoriously decreases with temperature (${\alpha }_{Vth}<0$), due to increased minority carrier concentration at higher temperature, reducing the required gate voltage to invert the channel. Nevertheless, given two transistors $M_A$ and $M_B$, designed with short/narrow and long/wide channels, respectively, predicting the sign of ${\alpha }_{VthA}-{\alpha }_{VthB}$ is not straightforward. However, referring specifically to the RSCE, it should be noted that it is a consequence of the average dopant concentration in the channel increasing as L decreases (with small L, the highly doped halo regions play a more significant role). As implied by device physics models [52], higher doping of the channel implies greater $V_{th}$ sensitivity to temperature, suggesting ${\alpha }_{Vth}$ to be smaller (more negative) for short-channel devices.

The latter assumption is confirmed by the simulation results of Figure 4: $|V_{thA}|-|V_{thB}|$ is plotted as a function of temperature in the case where transistor $M_B$ is sized with both W and L twice as large as those of $M_A$. For different sizing choices of $M_A$, the temperature trend of the threshold voltage difference remains NTC, with a slope around −0.5 mV/°C.

Resuming the analysis of the CR core of Figure 1, differentiating both terms of (2) with respect to temperature leads to the following result:

$${\displaystyle \frac{1}{I_1}}{\displaystyle \frac{\partial I_1}{\partial T}}={\displaystyle \frac{1}{T}}\left[-{\alpha }_{\mu }+{\displaystyle \frac{2{\alpha }_{\Sigma Vth}T+2n_5{U}_T\ln \left(ku\right)}{\Sigma V_{th}+n_5{U}_T\ln \left(ku\right)}}\right].$$

(6)

In the case where $\Sigma V_{th}=0$ (i.e., if devices within pairs $M_{3,4}$ and $M_{5,6}$ are designed with matched W and L), (6) evidently simplifies into ${\displaystyle \frac{1}{I_1}}{\displaystyle \frac{\partial I_1}{\partial T}}={\displaystyle \frac{2-{\alpha }_{\mu }}{T}}$. In this case, unless the mobility temperature exponent, ${\alpha }_{\mu }$, is exactly equal to 2, first-order temperature compensation cannot be performed. On the other hand, by introducing the $\Sigma V_{th}$ term with negative TC (${\alpha }_{\Sigma V_{th}}<0$), first-order temperature compensation is made possible. Specifically, the value of $\Sigma V_{th}$ should be optimized by imposing proper ratios between the channel widths and lengths of $M_4$ and $M_3$ (and/or $M_6$ and $M_5$), so that the following condition is met at the temperature $T_0$, where a zero temperature derivative is desired:

$$\Sigma V_{th}\left(T_0\right)={\displaystyle \frac{2{\alpha }_{\Sigma Vth}{T}_0}{{\alpha }_{\mu }}}+\left({\displaystyle \frac{2}{{\alpha }_{\mu }}}-1\right)n_5{U}_{T0}\ln \left(ku\right).$$

(7)

In this relationship, $U_{T0}$ indicates the value assumed by the thermal voltage at temperature $T_0$. If (7) holds true, the expression of $I_1$ can be rearranged into the following:

$$I_1\left(T\right)=I_1\left(T_0\right){\left({\displaystyle \frac{T_0}{T}}\right)}^{{\alpha }_{\mu }}{\left[1+{\displaystyle \frac{{\alpha }_{\mu }}{2T_0}}(T-T_0)\right]}^2,$$

(8)

which is a parabolic-like function of temperature, with its minimum point located at $T=T_0$.

In future research, the proposed temperature compensation approach might be also extended to emerging non-CMOS technologies, such as Carbon NanoTube Field-Effect Transistors (CNTFETs). Implementing a CR in this technology would be a pivotal addition to recently proposed Operational Transconductance Amplifier (OTA) solutions [53], yielding a compact reference circuit with low quiescent consumption, but careful consideration of CNTFET variability, temperature dependence, and matching properties would be needed.

2.3. Complete Current Reference Design

In Figure 5, the complete architecture of the proposed CR is shown at the transistor level.

In addition to the previously discussed CR core, a feedback branch was included, made up of transistors $M_{7–9}$, to minimize sensitivity to supply voltage variations. An auxiliary start-up circuit is also present, composed of $M_{s1–4}$. Moreover, since specific values of W and L are needed in order to apply the above-discussed temperature compensation, stacked configurations were used to implement $M_3$, $M_4$, and $M_8$, to reduce current consumption down to a few hundred nA without acting on individual channel lengths. Within each stack of transistors, all of the body terminals of individual devices were connected to the source terminal of the upper device, allowing all transistors to share the same N-well. This choice avoids the need for inter-well spacing, leading to smaller area occupation.

Concerning the LS correction, we adopted a technique inspired by [35,36] and adapted to the proposed architecture. In the basic CR version of Figure 1, the $V_{DS}$ differences between transistors $M_1$-$M_2$ and $M_3$-$M_4$ directly follow $V_{dd}$ variations (i.e., $\Delta V_{DS2,1}=V_{DS2}-V_{DS1}=V_{dd}-V_{SG5}-V_{SG6}-V_{GS1}$). This may cause relatively large LS due to finite output impedances of the current mirrors. Conversely, in the circuit of Figure 5, the addition of the $M_{7–9}$ circuit branch reduces the magnitude of the $V_{dd}$-to-$\Delta V_{DS2,1}$ sensitivity by a factor roughly equal to the intrinsic gain of $M_7$. Intuitively, it can be noted that, if ${\rho }_8/{\rho }_3={\rho }_9/{\rho }_5=\gamma$, a linear proportionality relationship exists between the currents flowing in the two considered branches (i.e., $I_{D8}=\gamma I_{D3}$). Thereafter, if ${\rho }_7/{\rho }_2=\gamma$, transistors $M_7$ and $M_2$ result in the same gate-source voltages, forcing $V_{DS1}=V_{GS7}=V_{GS2}=V_{DS2}$. To ensure loop stability, $M_2$ has to take the role previously played by $M_1$ as the input device of the n-type current mirror, while $M_8$ acts as the input device of the p-type current mirror. In addition, to strengthen stability, we applied Miller compensation between the branches $M_{1,4,6}$ and $M_{7,8,9}$. At start-up, exploiting the pull-up effect from $M_{8,9}$, capacitor $C_C$ also assists in streamlining the turn-on process of the circuit.

In

Table 1. Device sizes.

Device	Width (µm)	Length (µm)	Multiplicity	Stack
$M_1$, $M_2$, $M_7$	5	3	16, 16, 4	1
$M_3$	2	1	2	16
$M_4$	7.52	3.76	1	16
$M_5$, $M_6$, $M_9$	5	0.5	16, 48, 4	1
$M_8$	1	1	1	16
$M_{s1}$, $M_{s2}$, $M_{s3}$	1	0.3	1, 1, 8	1
$M_{s4}$	0.25	5	1	2

, we summarize the device sizes selected to implement the proposed CR.

For greater simplicity, we chose to exploit $V_{th}$ geometry dependences only in the $M_{3,4}$ transistor pair, while $M_5$ and $M_6$ were sized with equal widths and lengths. The dimension ratios $W_4/W_3$ and $L_4/L_3$ were chosen based on parametric simulations aimed at TC minimization. For the parameters previously introduced to express ratios between the aspect ratios of different transistors, the following values were selected: $k=1$, $h=2$, $u=3$, and $\gamma =1/4$. The passive devices used for frequency compensation, set equal to $C_C=530$ fF and $R_C=620$ kΩ, were implemented as a Metal–Insulator–Metal (MIM) capacitor and a high-resistivity polysilicon resistor, respectively.

The layout view of the proposed CR is shown in Figure 6. It occupies an area of 70 × 45 µm².

3. Simulation Results

In this section, the results of post-layout electrical simulations are reported to validate the proposed CR. Simulations were executed with the Spectre simulator, using device models of a commercial 0.18 µm CMOS process and models of layout parasitic components obtained from parasitic extraction procedures. Unless otherwise specified, simulations were performed in the typical process corner at room temperature ($T=27$ °C), with the supply voltage set equal to $V_{dd}=1.2$ V.

Figure 7 illustrates the temperature behavior of the reference current $I_{REF}$ (defined as the current flowing through $M_1$ in Figure 5). Multiple traces are shown, related to the following process corners: Typical (TT), Slow (SS), Fast (FF), Slow-NMOS–Fast-PMOS (SNFP) and Fast-NMOS–Slow-PMOS (FNSP). In the typical corner, $I_{REF}=140.7$ nA is achieved at room temperature, with a total consumption of $I_{sup}=314.2$ nA and $\mathrm{TC}=152.8$ ppm/°C from −20 °C to 80 °C. Across the other corners, the worst-case TC is equal to 242.2 ppm/°C, obtained in SS conditions.

It is worth noting that the highest reference current value is achieved in the SS corner, while the FF corner features the lowest $I_{REF}$. This behavior seemingly contradicts the practical results achieved in other types of CRs [37,43], which show highest $I_{REF}$ in the FF corner due to decreased threshold voltage and increased mobility. Such behaviors of $V_{th}$ and $\mu$ also exist in the CMOS process employed in this work; however, the proposed CR operates such that the overdrive voltage of transistors $M_3$ and $M_4$ also changes across process corners, contributing to the overall process corner variations of $I_{REF}$. In Figure 8a–d, we illustrate the process corner variations of all the device parameters appearing in the first formulation of (2), namely $|V_{th3}|-|V_{th4}|$, $V_{SG5}-V_{SG6}$, ${\beta }_3$, and $n_3$. Furthermore, in Figure 8e, the $I_{REF}$ values obtained from electrical simulations are compared with those predicted by computing (2) using the simulated device parameters. A Complementary To Fast-skewed Process corner (CTFP) behavior is confirmed for $I_{REF}$, evidently determined by the reduction in $|V_{th3}|-|V_{th4}|$ and the increase in $n_3$ in the FF corner. The small discrepancies between the two traces of Figure 8e are arguably due to second-order effects not taken into account in the simplified analytical model leading to (2) (e.g., use of an approximated form of the EKV model, $V_{DS}$ effects, and modeling the stacks of N devices, used to implement $M_3$ and $M_4$, as single devices with length equal to $N{L}_0$, where $L_0$ is the length of the individual stacked devices). The CTFP behavior of $I_{REF}$ has also been assessed in [38], even though for a different CR topology.

Figure 9 shows the reference current as a function of the supply voltage, again plotted for various process corners. Based on such results, the minimum supply voltage is assumed to be equal to $V_{dd,min}=1.2$ V. For $V_{dd}\in [1.2\mathrm{V},2\mathrm{V}]$, the LS is equal to −0.0251%/V in the typical corner, while a worst-case value of 0.171%/V is obtained in the FF corner.

Table 2. Process corner variations.

	TT	SS	FF	SNFP	FNSP
${\mathit{I}}_{\mathit{REF}}$ (nA)	140.7	160	129.3	135.1	150.8
${\mathit{I}}_{\mathit{sup}}$ (nA)	314.2	355.8	290.2	301.9	336.2
TC (ppm/°C)	152.8	242.2	219.6	157.8	208.7
LS (%/V)	−0.0251	−0.0999	0.171	−0.0801	0.0375

summarizes the main CR performances evaluated across process corners.

To characterize the sensitivity of the proposed circuit to random process variations, sets of 1000 Monte Carlo runs were executed, employing the statistical model files provided by the silicon foundry to simulate both global process variations and local mismatch errors. Figure 10 shows the process spread of $I_{REF}$, TC, and LS. $I_{REF}$ has a relative standard deviation of 6.7%. The average TC value is equal to 194.2 ppm/°C, while its 95% quantile is equal to 291.5 ppm/°C. As for the LS, an average value and a standard deviation equal to −0.0172%/V and 0.0584%/V, respectively, were assessed.

In Figure 11, the Power-Supply Rejection Ratio (PSRR) is shown as a function of frequency. This quantity is herein defined as the rejection ratio of $V_{dd}$ variations towards $I_{REF}$, assuming the dimension of a conductance. It is equal to −199.3 dB${\Omega }^{-1}$ at 1 Hz, −170.2 dB${\Omega }^{-1}$ at 1 kHz, and −125.2 dB${\Omega }^{-1}$ at 1 MHz.

The noise current spectrum is illustrated in Figure 12, evaluated at the drain terminal of $M_1$. At room temperature, the broad-band noise floor and the flicker corner frequency are equal to 1.1 $\mathrm{pA}/\sqrt{\mathrm{Hz}}$ and 410 Hz, respectively. The integrated noise is equal to 43.31 pA_RMS from 0.1 Hz to 10 Hz and 1.22 nA_RMS from 0.1 Hz to 100 MHz.

4. Conclusions

In this work, we presented a CMOS-only CR based on a novel temperature compensation approach, exploiting geometry-dependent threshold voltage effects. We demonstrated how the temperature behavior of BM-CRs can be beneficially shaped by introducing width- and/or length-dependent threshold voltage differences within specific pairs of transistors. Accurate post-layout simulations were executed to validate the proposed design, including process corner analyses and statistical Monte Carlo simulations.

In

Table 3. State-of-the-art performance summary.

	This Work	[55] TCAS-II 2024	[37] AEÜ 2021	[38] ISCAS 2014	[27] ISCAS 2019	[39] TCAS-II 2016	[43] TCAS-II 2020	[40] JSSC 2020	[41] TCAS-II 2021	[31] JSSC 2024	[44] ISCAS 2023	[42] TCAS-II 2023	[56] JSSC 2024
Techn. (nm)	180	180	180	180	180	180	180	180	180	22	28	180	180
Results type	Sim.	Sim.	Sim.	Sim.	Sim.	Meas.	Meas.	Meas.	Meas.	Meas.	Sim.	Meas.	Meas.
Approach	BM+ RSCE	BM+ SCC	BM	BM	BM+ ZTC	BM	BM	Auto calib.	BM+ BJT	BM	SC	BM	BJT+ DEM
CMOS only	Yes	Yes	No	No	Yes	Yes	Yes	Yes	No	No	Yes	Yes	No
Trimming	No	No	No	Yes	No	No	Yes	Yes	Yes	Yes	Yes	No	Yes
${\mathit{V}}_{\mathit{dd},\mathit{min}}$ (V)	1.2	1.4	0.6	1.2	1.2	1.25	0.8	1.5	2	0.75	0.5	2	1.3
${\mathit{I}}_{\mathit{sup}}$ (nA)	314.2	1916	345	1650	684	372	60.8	N/A	96	3.8	103	71.1·103	43.5·103
${\mathit{I}}_{\mathit{REF}}$ (nA)	141 *	469	115	500	142	92.3	11.6	1	51	1.5	78.5	8.5·103	10.3·103
$\sigma /\mu$ (%)	6.7	0.78	5.46	0.43	3.16	6.12	4.65	0.06	1.15	0.61	3.45	2.13	0.54
$\mathit{T}$ range (°C)	−20, 80	−20, 80	−20, 120	−40, 120	−40, 85	−40, 85	−40, 120	−20, 80	−45, 125	−40, 85	−20, 60	−35, 125	−20, 125
TC (ppm/°C)	194 *	114 *	15.7 #	119 †	56.4 *	177 *	169 *	289 *	89 *	89 *	115 ‡	2740	11.4
LS (%/V)	−0.017 *	3.61	0.04	6.91	1.45	7.5	1.08	1.4	1.76	0.51	1.2	0.3	0.036
RMS noise (pARMS)	43.31 (0.1–10 Hz)	N/A	14.7 (0.1–10 Hz)	N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A	2750 (10–50 kHz)	38.9 (0.01–10 Hz)
Area (mm2)	0.00315	0.080	0.008	N/A	N/A	0.001	0.054	0.332	0.063	0.002	0.002	0.11	0.08
FoM $\left({\displaystyle \frac{{\mu \mathrm{m}}^2}{{°\mathrm{C}}^2\mathrm{V}}}\right)$	0.00231	13.5	0.001	N/A	N/A	0.428	3.23	N/A	1.09	0.0184	0.0453	47.3	0.00956

BM: Beta-Multiplier; RSCE: reverse short-channel effect; SCC: Segmented Curvature Compensation; ZTC: Zero Temperature Coefficient; SC: Switched-Capacitor; DEM: Dynamic Element Matching. * Average value (across Monte Carlo runs including both global variations and mismatch errors, if simulation results are reported, or across multiple chip samples, if measurement results are reported). ^# Average value across Monte Carlo runs including only mismatch errors. The worst-case reported TC across process corners is 92.1 ppm/°C. ^† TC evaluated in process corner simulations without mismatch errors. ^‡ TC evaluated in nominal process corner without mismatch errors.

, the attained performances are compared to prior art. In addition to the main circuit performances, we also indicated the specific design methods employed in the selected designs, the presence/absence of other types of devices besides MOS transistors and the use of trimming. Furthermore, a Figure of Merit (FoM) is also introduced, to allow more immediate comparisons among various works. As of today, in the context of CRs, little emphasis has been devoted to proposing and validating FoMs encompassing the main circuit performances. Among the references considered in this work, FoMs are proposed in [27,31], but such quantities only take into account TC, temperature range, power consumption, and area occupation, while neglecting LS. Nevertheless, depending on the considered application, resilience against supply voltage variations may represent a crucial concern. That is the case, for instance, of electronic devices supplied by energy-harvesters, often including charge-pump-based up-shifting of the supply voltage provided by the harvester [54], at the cost of non-negligible fluctuations being superimposed onto the final $V_{dd}$ level. In such scenarios, minimal LS is indeed required. According to such motivations, we hereby introduce an FoM focusing on supply and temperature immunity, as well as power and area efficiency. Specifically, we employ the FoM previously proposed in [31] with the addition of LS as a multiplying factor, leading to the following definition:

$$\mathrm{FoM}={\displaystyle \frac{\mathrm{TC}}{T_{max}-T_{min}}}·{\displaystyle \frac{I_{sup}}{I_{REF}}}·\mathrm{LS}·\mathrm{Area}.$$

(9)

Designs characterized by lower FoM values deliver better performance in terms of $I_{REF}$ stability and efficiency.

The LS accomplished by this work is the smallest among the reported references, proving strong effectiveness of the employed LS correction technique. The achieved LS reduction comes at the cost of increased power consumption, due to the additional circuit branch; however, in the presented design, the additional transistors have been sized to limit the efficiency loss to around 12.5%. Acting only in terms of $V_{DS}$ stabilization, the proposed method does not modify the temperature compensation approach with respect to the original six-transistor CR. Among the works operating at similar current levels (hundreds of nA), [37] is the only one achieving an LS of the same order of magnitude as our work. A different BM structure is employed (resistor-based peaking CR, placing the resistor on top of a diode-connected transistor in the non-linear mirror, rather than in series to its source terminal), but the authors of [37] also apply an LS improvement method based on an additional circuit branch introducing negative feedback. On the other hand, [38,39,40,42] attempt to reduce LS by implementing the BM structure using standard cascode current mirrors, while [41] uses a pseudo-cascode current mirror, and [43,44] include mirrors assisted by auxiliary amplifiers for $V_{DS}$ control, but all of these works ultimately achieve LS values higher than 0.3%/V.

The TC obtained in this work is also in line with previously demonstrated CRs designed for similar current ranges. Among such works, refs. [27,37] reported significantly lower TC; however, for the design presented in [37], the area occupation is more than two times higher than in our design, partly due to the use of a resistor in this CR, while the small TC achieved in [27] is traded off with an LS metric about 80 times higher than the result obtained in this work. In future research, the TC of the proposed CR may be further reduced by adding trimming schemes and Segmented Curvature Compensation (SCC) strategies [55,56,57], to apply effective high-order temperature compensations.

Concerning the effects of random process variations, the relatively large standard deviation of $I_{REF}$ assessed for the proposed CR (indicated in relative terms in Table 3, as $\sigma /\mu$) is a consequence of the small area budget (third-smallest area in Table 3) adopted in this work to enhance suitability for low-cost and low-size ICs. In this respect, it is worth noting that [39], reporting a CR designed with an analogous current level and area occupation, and, like our work, without trimming approaches, is characterized by a similar $\sigma /\mu$ value. However, for applications imposing more stringent yield requirements, the proposed CR design can be complemented by various well-established accuracy improvement techniques. In the first place, in system architectures presenting only one CR core, serving all of the other blocks instantiated on-chip, larger area occupation is arguably tolerable, allowing reduction in the variance of mismatch errors. Moreover, layout techniques enhancing symmetry and matching of the three main device pairs ($M_1$-$M_2$, $M_3$-$M_4$ and $M_5$-$M_6$) can be adopted, including bidimensional common-centroid layouts, minimizing the effects of on-chip gradients on the device parameters. In addition, resilience to both mismatch and gradient errors may be enhanced by implementing Dynamic Element Matching (DEM) strategies [36,56,58,59], allowing the trade off of operating frequency for accuracy, rather than sacrificing area. On the other hand, concerning global process variations, batch-trimming approaches can be implemented (i.e., trimming one chip per fabrication run, to correct $I_{REF}$ against the occurred process corner, and then apply the same trimming code to all chips). This is commonly performed both in VR- and CR MOSFET-based solutions. In the specific case of the proposed CR, a simple programmable current mirror can be added within an output branch replicating the $I_{REF}$ current towards the supplied circuits. This type of correction, acting on the value of $I_{REF}$, is feasible in the form of one-point calibration (i.e., performed at a single temperature). In addition, TC calibration may also be performed relying on two-point trimming of the multiplicity of $M_6$, which affects the slope of the PTAT voltage term $n_5{U}_T\ln \left(ku\right)$ appearing within square brackets in (2). This would allow the recovery of TC errors possibly occurring in fabricated prototypes, due to either inaccurate modeling of temperature effects in the employed device models, or mismatch errors affecting device geometry. Another promising approach for process corner compensation has been recently proposed in [33,34] for VRs, exploiting geometry-dependent threshold voltage effects to control not only temperature dependence but also sensitivity to global process errors. Adapting this approach to BM-CRs, such as the herein proposed circuit, entails interesting perspectives for future research.

Noise performances have been often omitted in previous articles on CRs, hindering the possibility of a clear and extensive overview. Compared to the other works offering noise characterizations, this work achieves RMS noise of the same order of magnitude. Due to the small area of our design and the absence of dynamic noise compensation techniques, such as DEM or chopping, flicker noise is arguably more dominant compared to other published CRs. In future studies, compensation techniques tackling both mismatch and noise might be developed. Furthermore, for the specific case of noise, current-mode low-pass filtering, such as the approach recently presented in [60], might also be promising.

Finally, in terms of the proposed FoM, our work achieves the second-best value among the works compared in Table 3, smaller by about an order of magnitude or more, compared to the other references except [37]. The FoM value achieved by this work is mainly determined by the remarkably low LS and area results, even lower than those reported in [37], which features the best FoM within Table 3.

In conclusion, the reported findings validate the proposed CR architecture as an effective solution to achieve enhanced robustness against supply noise and temperature variations under strict power and area constraints. Thereafter, the proposed solution appears as a good candidate for the integration of CRs within versatile low-cost and low-power ICs for IoT and smart sensing applications.