Reduced ΔCTE and Galvanic Corrosion Failures in Mass Production by Using a Robust Design for Medium to Large Display Panels

Abstract

Flat panel displays for large applications (monitors and TVs) have structural weaknesses in improving the yield of mass-produced products due to large panels: the yield is defined by ratio of output quantity to input into panel fabrication process. From a panel manufacturing point of view, low-cost production should be achieved through improved yield of mass production (Samsung Display’s quantum dot display backplane panel). So, we set the target yield at an extreme value, over the golden yield (90%) at the beginning of new mass products. The main factors contributing to the yield loss were “lifted insulator and etched active pattern defects”. To reach the target yield, we focused on these two main defects. The root causes of these defects (delta coefficient of thermal expansion and galvanic corrosion) are explained, and a defect generation mechanism is proposed (the size of the separated large power line in relation to the defect rate). The power lines are defined based on an Electroluminescent Voltage at the Drain (ELVDD) and Electroluminescent Voltage at the Source (ELVSS). We developed a separated large power line design to reduce defect rates. This design plays a role in preventing these two defects during the mass production of medium to large display panels for use in TVs by ensuring that the large power line area is less than the optimum value (<0.44 cm²).

1. Introduction

Flat panel display technology has changed from voltage-driven liquid crystal displays (LCDs) in the 1990s to current-driven organic light emitting diodes (OLEDs) in the 2000s [1,2,3,4,5,6,7,8,9,10,11,12,13]. For reference, voltage-driven LCDs mean that the brightness of LCDs is controlled by the delta voltage between positive and negative electrodes, and current-driven OLEDs mean that the brightness of OLEDs is controlled by the OLED current of the driving transistor, which supplies current from ELVDD to OLED. In order to supply a constant current to each pixel of the panel, it is important to supply the power signal evenly within the panel from the aspect of panel design. Therefore, a relatively large power line design with thick line width and metal thickness is inevitably required. As the panel size moves beyond the monitor to home applications, the power line design is also bound to grow. Due to this structural vulnerability, particles generated in the manufacturing process have become a key item in yield improvement activities.

During mass production, rapid yield ramp-up is key to high profits early in the product’s lifetime. Therefore, we set the target yield at an extreme value, over the golden yield (90%). Generally, the main factors affecting yield loss, lifted insulators, and etched active pattern defects need to be improved to meet this extreme target yield.

Previous methods of reducing process particles have been to develop equipment and add one process to the manufacturing process: (1) Developing sputtering targets (rotation target arrays) that provide less material redeposition and nodule formation, gradually reducing the number of particles, improving device performance, yield, and product value [14]. (2) The sacrificial layers that operated to reduce panel failures due to particles [15]. However, such cases require huge investment and additional layers in the equipment and take a long time to set up the equipment and build new processes. Otherwise, design changes for mitigation are relatively inexpensive, fast, and have a better impact on reducing defect rates.

In this paper, we focused on defining the root causes of “lifted insulator and etched active pattern defects” and providing a new design with a large power line to prevent defects in advance. For reference, large power lines are composed of an ELVDD, supplying high (positive) voltages to the panel, and an ELVSS, providing low (negative) voltages.

2. Results and Discussion

2.1. Phenomenon Analysis

A lifted insulator (SiOx) defect is circular and has a submicron particle at its center (Figure 1a). An active (Indium Gallium Zinc Oxide, IGZO) pattern defect is etched starting from a lifted insulator defect, especially from a submicron defect (Figure 1b). One can say that a submicron defect is the origin of both of these defects. An etched active pattern defect makes the source–drain pattern of the driving transistor open or thinning so that an on-state dark dot occurs in a display panel due to decreased current from the driving transistor.

2.2. Step-by-Step Defect Review to Search for the Processes That Cause These Defects

To determine the processes in which defects occur, we adopted a step trace method that reviews defects on the glass right after each process with optical inspection equipment. We made three conclusions: (1) a submicron defect occurs in a particle before or during insulator deposition (no defect before insulator deposition and defects were found right after insulator deposition); (2) a lifted insulator defect is generated after insulator deposition but during active deposition (no defect before active deposition and defects were found right after active deposition); and (3) an etched active pattern defect is generated during the active chemical wet etch process (no defect before active chemical wet etch process and defects were found right after active chemical wet etch process).

Figure 1. (a) A submicron particle on the large power line that is metal 1, Cu in the top view, (b) the insulator lifted at the center of a submicron particle (vertical view), (c) active pattern in driving transistor, and (d) etched active pattern (source–drain open).

Figure 1. (a) A submicron particle on the large power line that is metal 1, Cu in the top view, (b) the insulator lifted at the center of a submicron particle (vertical view), (c) active pattern in driving transistor, and (d) etched active pattern (source–drain open).

2.3. Process Condition Changing Test

After we changed the active material from IGZO to the transparent conductive oxide (TCO, Indium Tin Oxide), etched pattern defects were not found in any part of the glass because ITO deposition gas has no H₂O, including OH- having weaker bonding energy than that of O₂ in ITO deposition. It means that the active deposition gas causes defects. Decreasing the flow rate of the suspicious gas (oxygen in H₂O) to zero during active deposition reduced the lifted insulator defect rate to zero (no defect in dozens of glasses). Additionally, conditions decreasing the deposition time reduced the number of defects. Therefore, the reaction that creates these defects occurs at the beginning of IGZO deposition. In summary, lifted insulator defects are generated during active deposition due to one of the deposition gases (

Table 1. Process condition changing test during active deposition.

Item	Ref.	Test	Defect Reduction Rate
Material	IGZO	ITO	100%
O2 Gas Flow Rate (Normalized)	1	0	100%
Process Time (Normalized)	1	0.34	84.2%

).

Additionally, we determined the relation between lifted insulators and etched active pattern defects.

2.4. Defect Generation Mechanism

Based on a step-by-step defect review, we could infer the relation between lifted insulators and etched active pattern defects. First, a submicron particle from the equipment of insulator deposition was dropped on metal 1 before insulator deposition and covered with an insulator that has a weak step coverage around submicron particles due to its intrinsic chemical vapor deposition (CVD) film growth characteristics (Figure 2): a micro-crack in the insulator is called a “seam”, which is from the columnar grains due to anisotropy in the growth rate of nuclei on the substrate [16].

(a)

Lifted Insulator Defects

During active (IGZO) deposition, oxygen (O) dissociates from water vapor (H₂O) in the plasma in the sputtering chamber (Equation (1)). Negatively charged oxygen ions (O-) can result from the ionization of oxygen atoms in the plasma and strike the insulator from the beginning of active deposition because of metal 1 with a positive polarity relatively. These striking supplies bombard energy to the surface of the insulator on the metal and act as a large capacitor attracting negatively charged oxygen ions. The surface temperature of the insulator increased to create the insulating gap in Figure 1b. This thermal energy was then transferred to the insulator and metal 1, which have different coefficients of thermal expansion (CTEs), as shown in

Table 2. CTE of the insulator and metal 1.

	Insulator	Metal 1
CTE (μm/m°C)	0.7	16.7

. In Figure 1b, the lifted insulator gap is about 0.2 μm. Since horizontal thermal expansion was reflected in the vertical direction, we could calculate the surface temperature of the insulator during IGZO deposition to be about 630 °C (with a power line width of 20 μm, ΔCTE = 16 μm/m), which is not much different from substrate temperature in [17]. Additionally, an insulator gap was created at the defect due to the non-continuous surface causing thermal stress concentration. According to the defect generation mechanism, larger power lines attract negative oxygen ions. We propose the design of a new, smaller power line later, as follows:

H₂O (gas) → 2H (atom) + O (atom)

(1)

(b)

Etched Active Pattern Defects

Phenomenologically, an active pattern was etched starting from a micron particle centered on the lifted insulator and was rapidly etched into a round shape due to electrons lost to metal 1 through micro-cracks during active etching because of the standard electrode potential (SEP) difference between the active pattern (IGZO) and metal 1 (

Table 3. Standard electrode potential (SEP).

	In	Zn	Ga	Metal 1
SEP (V)	−0.34	−0.76	−0.56	0.34

). This is a kind of galvanic corrosion due to the micro-scale distance from the lifted insulator defect to the active pattern. Galvanic corrosion can be represented by the galvanic current (I), the integrated current of the cathodic (IGZO) to the anodic (metal 1). Another factor in galvanic corrosion is the large power line area per line (Ap), which attracts negatively charged components from the IGZO to its large capacity (Figure 2) [18,19]. The second factor (the large power line area per line, Ap) is more significant than the first one (I) because Ap determines the amount of current in galvanic corrosion as Figure 3.

2.5. Design Modification

The insulator lifting defect rate (the number of defects in one glass/cell number) increases exponentially as the panel size becomes larger. As shown in Figure 3, the lifted insulator defect rate of the largest panel F decreased to an acceptable rate by downsizing the large power line (C, the separated large power line). The large power line area of panel C is the optimum value (<0.44 cm²) that can be used to check the design of new products before they are photo-masked with tape. It will be referenced in detail later.

2.6. Design Verification

Before separating the large power lines, we checked the side effects: luminance uniformity, power consumption due to increased line resistance (17% ↑), and image sticking. The luminance uniformity and power consumption were not different from those used in conventional single power line designs (normalized luminance uniformity: Ref. normalized value 1 → separated design 0.996; normalized power consumption: 1 → 1.009). However, image sticking (OLED lifetime) decreased by up to 75% because of the increased resistance (17% ↑) of the separated power line, which decreased the amount of compensated pixel current for a long operation. In the pixel circuit (Figure 4), the resistance components of the power line were increased, Ra to 2Ra, and Rc was added.

To overcome the increased resistance of power lines, we increased the thickness of metal 1 to reduce the resistance of the separated power line to that of the conventional single power line. The increased thickness of metal 1 had no side effects like the step opening of metal lines on metal 1.

2.7. Design Rule

As mentioned before, we can determine the golden value for large power line areas per line (normalized) to obtain stable yield when manufacturing panels in exponential relation to the lifted insulator defect rate. Additionally, for our next new product, we implemented a rule to check large power lines to prevent lifted insulators and etched active pattern defects based on the line area size and the use of a separated power line for medium-sized panels (that is, larger than panel C). In principle, this design can be applied to every medium-sized panel.

3. Conclusions

Based on a hypothesis from the defect phenomenon analysis, we investigated the mechanism behind lifted insulators and etched active pattern defects through experiments. Moreover, we devised a new design to suppress fundamental occurrences and applied it to mass production. In addition, we found the optimum value (<0.44 cm²) that can be used to check the large power line area per line of new products before fixing the panel design. Through this research, we proposed the mechanism behind defect generation and a novel design rule that can be used for medium-sized home displays.

4. Patents

Patent applications have been submitted in the US, China, and South Korea.