A Remote Temperature-Sensing Chip Adaptive to Parasitic and Discrete Transistors with an Inaccuracy of ±0.25 °C from −55 °C to 125 °C

Abstract

This paper presents a high-precision remote temperature-sensing chip designed for advanced computing systems that require high-precision thermal management. The parasitic resistance, beta compensation, and early voltage compensation are proposed to achieve accuracy compensation of remote temperature sensing, whether using discrete transistors or parasitic transistors. The chip completed the circuit and layout design in a 0.18 μm CMOS process, with a chip area of 0.33 mm² and a supply voltage of 1.8 V. Post-layout simulation results showed that the chip achieves a temperature-sensing accuracy of ±0.25 °C within the temperature range of −55 °C to 125 °C when adopting discrete transistors and parasitic transistors for remote temperature measurement.

1. Introduction

The integrated circuit industry has experienced significant advancements in recent years. Continuous enhancements in chip design and manufacturing processes have led to improvements in the accuracy and measurement range of temperature-sensing chips. Presently, these chips are extensively utilized in various sectors, including the Internet of Things (IoTs), automotive electronics, and healthcare [1,2,3,4,5,6]. As Moore’s Law progresses, the number of transistors within increasingly complex electronic systems continues to rise, resulting in higher levels of integration that enable a single chip to accommodate tens of billions of transistors. However, this escalation in integration density is accompanied by a corresponding increase in heat flow density within electronic systems, which poses substantial heating challenges. These thermal issues have emerged as critical factors limiting computational performance and reliability [7,8,9,10,11]. Consequently, effective thermal management is essential to optimize the performance of integrated circuits, particularly in advanced computing systems [12,13,14,15,16,17].

Advanced computing systems generally comprise several high-heat critical components, including central processing units (CPUs) and field-programmable gate arrays (FPGAs), necessitating individual monitoring of temperature for each critical component. Furthermore, to maintain stable operation within the designated temperature range, it is essential to monitor both the ambient temperature and the package shell temperature of these critical components [18]. Presently, a prevalent approach for thermal management in advanced computing systems involves the utilization of remote temperature-sensing chips [18,19,20,21,22].

A typical system management controller (SMC), as illustrated in Figure 1, serves as a crucial element for thermal management in contemporary electronic systems. Conventional thermal management strategies predominantly depend on the processing of temperature data via an embedded microcontroller unit (MCU), which subsequently implements appropriate thermal regulation measures. Within this framework, a remote temperature-processing chip relays temperature data to the MCU. The MCU, in turn, controls the operation of various thermal management devices within the system based on the temperature readings received, which may include activating fans, adjusting heat sinks, or initiating other cooling interventions. Moreover, the MCU possesses the capability to dynamically adjust the system’s operational parameters, such as the processor’s clock frequency and voltage supply, in response to fluctuations in temperature. By fine-tuning these parameters, the system can effectively mitigate power consumption and heat generation, thereby ensuring that the processor functions within optimal temperature ranges and preventing performance degradation or hardware failure due to overheating [17,18,23,24,25].

To further improve the responsiveness and efficiency of the thermal management system, particularly in minimizing delays within the thermal control loop, certain processors or FPGA devices will be able to extract the internal parasitic bipolar junction transistors (BJTs) through the pin. The remote temperature-sensing chip is connected to these parasitic BJTs via wiring, facilitating the monitoring of temperature in both the processor and the FPGA. This approach not only diminishes the reliance on external temperature sensors but also enhances the accuracy and immediacy of temperature data collection [18]. Additionally, to assess the environmental temperature of critical components and the package shell, multiple discrete BJTs can be strategically placed on the printed circuit board (PCB). The remote temperature-sensing chip can interface with these discrete transistors to monitor temperature distribution across various locations, thereby enabling the system to acquire more comprehensive temperature data and execute more precise thermal regulation for each critical component. To sum up, advanced computing systems can attain enhanced thermal management through the utilization of remote temperature-sensing chips, which allow the system to maintain stable operation in complex thermal environments, optimize system performance, prolong device lifespan, and ensure the long-term stability and reliability of the system.

To ensure that advanced computing systems can effectively respond to temperature fluctuations in real time and maintain operational efficiency, the accuracy of temperature sensing in remote temperature-sensing chips is a critical parameter that significantly influences the system’s energy efficiency and safety margin. The higher the accuracy of the temperature sensors, the smaller the safety margin required by the system, resulting in less overall energy consumption. Research indicates that an improvement of 1 °C in temperature measurement accuracy can yield energy savings of up to 2 W [26]. As the demand for precision and stability in data processing systems escalates, there is an urgent need for high-precision temperature-sensing capabilities, specifically with an accuracy of less than ±0.5 °C within the temperature range of −55 °C to 125 °C [5,27,28,29].

With the increasing demand for precision and stability in data processing systems, the need for high-precision temperature sensing has become increasingly critical. Specifically, temperature sensing with an accuracy of less than ±0.5 °C within the temperature range of −55 °C to 125 °C is highly desirable.

In an effort to improve the accuracy of remote temperature sensing in thermal management systems, numerous scholars have engaged in research focused on this area [18,19,20,21,22,30]. Various methodologies have been employed, including the elimination of parasitic resistance, dynamic component matching, chopping, and correlated double sampling in remote temperature-processing chips. These approaches have successfully achieved a remote sensing accuracy of ±0.4 °C when interfaced with discrete bipolar junction transistors (BJTs), thereby satisfying high-precision requirements [18]. Nevertheless, there remains considerable potential for further enhancement of remote sensing accuracy in temperature-sensing chips when interfaced with parasitic BJTs. Current investigations by researchers are exploring techniques such as beta compensation, parasitic resistance elimination, and current mode-based hybrid architectures, which have improved remote sensing accuracy to within ±1.5 °C; however, this still does not meet the stringent requirements for high-precision temperature sensing [18,20,22]. In light of these challenges, this paper proposes the development of a high-precision remote temperature-sensing chip that incorporates an innovative compensation structure alongside parasitic resistance elimination technology. This design aims to achieve compensation for remote sensing accuracy in both discrete and parasitic transistor configurations, thereby fulfilling the high-precision remote sensing requirements essential for advanced systems thermal management.

The structure of the subsequent sections of this article is delineated as follows. Section 2 elucidates the operational principles of the remote temperature-sensing chip, identifies the critical factors influencing the accuracy of remote temperature measurements, and proposes relevant solutions. Section 3 introduces the specific circuit details of the remote temperature-sensing chip. Section 4 presents the performance characteristics of the remote temperature-processing chip through post-layout simulation results. Finally, Section 5 summarizes the conclusions derived from this research endeavor.

2. Operating Principle

2.1. The Principle of Remote Temperature Sensing

Figure 2 describes the temperature measurement principle of the remote temperature-sensing chip [18]. This principle is based on the exponential relationship between the base–emitter voltage (V_BE) and the collector current (I_C) of the transistor, and the relationship between V_BE and I_C is as follows:

$$V_{\mathrm{BE}}={\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}\ln {\displaystyle \frac{I_{\mathrm{C}}}{I_{\mathrm{S}}}}$$

(1)

where k is the Boltzmann constant, q is the electron charge, T is the absolute temperature, I_C is the collector current, and I_S is the reverse saturation current.

To measure the remote temperature, the remote temperature-sensing chip consistently applies two different proportions of current to the remote temperature-sensing BJT, respectively I_bias and NI_bias. It subsequently calculates the difference in base–emitter voltage (ΔV_BE) by subtracting the V_BE produced by these two currents.

$$\Delta V_{\mathrm{BE}}={\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}\ln N$$

(2)

From Equation (2), it is evident that a linear correlation exists between ΔV_BE and the absolute temperature T, allowing for the determination of the remote ambient temperature based on ΔV_BE The bandgap reference module within the remote temperature-sensing chip depicted in Figure 2 supplies the reference voltage V_REF for the analog-to-digital converter (ADC). The ADC will sample the ΔV_BE with V_REF as the reference. Through quantization, an output Y is obtained that exhibits a linear relationship with temperature. The corresponding expression is as follows:

$$Y={\displaystyle \frac{\Delta V_{\mathrm{BE}}}{V_{\mathrm{REF}}}}$$

(3)

A digital temperature reading D_out in degrees Celsius is then obtained by linear scaling of Y:

$$D_{\mathrm{out}}=A•Y+B$$

(4)

where A and B are process-dependent constants [31].

According to the principle of remote temperature sensing, any factor that influences the remote measurement voltage ΔV_BE or the reference voltage V_REF may significantly affect the remote temperature-sensing accuracy. Within the chip, the temperature drift of V_REF can compromise its precision; therefore, the bandgap reference module must adopt a low-temperature-drift structure to ensure stability. However, in the remote BJT, there are nonidealities of the I_E-V_BE, the Early effect, and parasitic resistance [31]. These nonideal factors introduce error terms into Equation (1), thereby degrading the accuracy of ΔV_BE and consequently affecting the remote temperature-sensing accuracy. The following sections will analyze these influencing factors in detail.

2.2. Early Effect

There is an Early effect in BJT, which also causes the ∆V_BE,actual to deviate from the theoretical value. Therefore, Formula (2) is modified to reflect this deviation:

$$\Delta V_{\mathrm{BE},\mathrm{actual}}=(1+{\displaystyle \frac{\mathrm{k}T}{\mathrm{q}{V}_{\mathrm{AR}}}}){\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}\ln N$$

(5)

where V_AR is the reverse Early voltage.

From Equation (5), it is evident that the Early effect mainly introduces the influence of inverse Early voltage V_AR into ∆V_BE, thereby resulting in the generation of a product factor denoted as α_VAR.

$${\alpha }_{\mathrm{VAR}}=1+{\displaystyle \frac{\mathrm{k}T}{\mathrm{q}{V}_{\mathrm{AR}}}}$$

(6)

From the above equation, it can be seen that the product factor α_VAR will change with temperature, which will also cause a large secondary temperature characteristic influence in the generated temperature signal ∆V_BE, thus affecting the remote temperature-sensing accuracy. Therefore, in order to reduce the influence of the Early effect, a compensation structure can be designed, which can detect the magnitude of V_AR so that the product compensation factor 1/α_VAR can be calculated, which can digitally compensate the secondary temperature characteristics of ∆V_BE,actual and reduce its impact on the remote temperature measurement accuracy.

2.3. The Nonideality of the I_E-V_BE

The nonideality of the I_E-V_BE in the remote BJT will affect the accuracy of ΔV_BE, resulting in ∆V_BE,actual deviating from the theoretical value; Equation (2) becomes:

$$\Delta V_{\mathrm{BE},\mathrm{actual}}={\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}\ln ({\displaystyle \frac{{\beta }_1(1+{\beta }_2)}{{\beta }_2(1+{\beta }_1)}}N)$$

(7)

where β₁ and β₂ are the direct current (DC) amplification factor of the bias current of I_bias and NI_bias, respectively.

It can be seen from Equation (7) that the nonideality of I_E-V_BE mainly introduces the influence of the DC amplification factor β into ∆V_BE,actual, that is, an addition factor γ is generated.

$$\gamma ={\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}\ln ({\displaystyle \frac{1+\frac{1}{{\beta }_1}}{1+\frac{1}{{\beta }_2}}})={\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}\ln \left(1+{\displaystyle \frac{{\beta }_2-{\beta }_1}{{\beta }_1\left(1+{\beta }_2\right)}}\right)$$

(8)

The above equation indicates that when the DC amplification values (β₁ and β₂) of the remote transistor exhibit low values under varying bias currents, coupled with a significant difference between them, the error term introduced by the additive factor γ in ∆V_BE,actual becomes substantial. This error term is positively correlated with temperature, which can severely affect the remote temperature measurement accuracy. Consequently, to mitigate the impact of beta error on remote temperature measurement accuracy, it is imperative that the β₁ and β₂ of the remote triode at different bias values are as large as possible and that β₂-β₁ are as small as possible.

There exist two categories of remote BJT: discrete BJT and parasitic BJT. Currently, the 2N3904/3906 transistors are commonly employed as remote temperature-sensing BJT within the discrete BJT category. These transistors exhibit a DC amplification factor exceeding 100 at microampere (μA) bias currents, with a typical variation of approximately 30. The bias current range provided by the remote sensing chip typically spans from 5 to 160 μA. It is noteworthy that beta error can significantly influence the accuracy of remote temperature sensing, potentially resulting in an error margin of approximately 0.3 °C. Conversely, when utilizing parasitic BJT found within processors or field-programmable gate arrays (FPGAs) for remote temperature sensing, the situation is markedly different. The DC amplification at μA bias currents is considerably low (often falling below 1 in many advanced fabrication processes) and varies with different bias currents. Consequently, the impact of beta error on the accuracy of remote temperature sensing is exacerbated. For instance, if the difference between β₁ and β₂ is 0.1, the beta error could lead to a minimum deviation in temperature-sensing accuracy of approximately 3 °C.

Hence, meeting the requirements for high-precision temperature measurement necessitates the mitigation of beta error’s impact on the accuracy of temperature sensing. It is essential to develop a compensation structure within the remote temperature-sensing chip. This structure should be capable of detecting the variations in beta values associated with different temperatures and bias currents so that the product compensation factor γ can be calculated and the beta error in ∆V_BE,actual can be digitally compensated to reduce the impact of beta error on the temperature measurement accuracy.

2.4. Parasitic Resistance Effect

Parasitic resistance significantly influences the accuracy of remote temperature sensing. This parasitic resistance primarily comprises two components: (1) a series resistance in each pole of the BJT, in which the base resistance affects the remote temperature-sensing accuracy; and (2) the connection between the remote sensing chip and the remote temperature-sensing BJT via a long lead, which typically introduces substantial series resistance that further impacts measurement accuracy. For analytical purposes, these two resistance components can be represented as an equivalent parasitic resistance (R_P) in series with the emitter of the remote BJT, as illustrated in Figure 3.

When a continuous current ratio of N:1 is applied to the remote BJT twice, the actual base–emitter voltage difference (∆V_BE,actual) will diverge from the theoretical base–emitter voltage difference (∆V_BE,ideal), as delineated in Equation (2), due to the existence of parasitic resistance R_P. Consequently, the magnitude of the error (∆V_BE,error) arising from the theoretical value can be expressed as follows:

$$\Delta V_{\mathrm{BE},\mathrm{error}}=\Delta V_{\mathrm{BE},\mathrm{actual}}-\Delta V_{\mathrm{BE},\mathrm{ideal}}={\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}\ln {\displaystyle \frac{I_{\mathrm{bias}}}{I_{\mathrm{S}}}}+I_{\mathrm{bias}}R-{\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}\ln {\displaystyle \frac{I_{\mathrm{bias}}}{I_{\mathrm{S}}}}=(N-1)I_{\mathrm{bias}}{R}_{\mathrm{P}}$$

(9)

The inaccuracies in ∆V_BE,ideal will propagate to the quantified digital temperature readings derived from Equations (3) and (4), which will eventually affect the remote temperature-sensing accuracy. To eliminate the influence of parasitic resistance R_P on the remote temperature-sensing accuracy, a parasitic resistance elimination technology is proposed in this paper, and its principle is shown in Figure 4.

The on–off of switches S1, S2, and S3 is controlled by the control signal so that the bias currents flowing through the remote triode are I_bias, 6 I_bias, and 16 I_bias, respectively, and the base–emitter voltages under the three different bias currents are V_BE1, V_BE2, and V_BE3, respectively:

$$V_{\mathrm{BE}1}={\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}\ln {\displaystyle \frac{I_{\mathrm{bias}}}{I_{\mathrm{S}}}}+I_{\mathrm{bias}}{R}_{\mathrm{P}}$$

(10)

$$V_{\mathrm{BE}2}={\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}\ln {\displaystyle \frac{6I_{\mathrm{bias}}}{I_{\mathrm{S}}}}+6I_{\mathrm{bias}}{R}_{\mathrm{P}}$$

(11)

$$V_{\mathrm{BE}3}={\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}\ln {\displaystyle \frac{16I_{\mathrm{bias}}}{I_{\mathrm{S}}}}+16I_{\mathrm{bias}}{R}_{\mathrm{P}}$$

(12)

After weighted subtraction of the base–emitter voltage obtained three times, the resulting base–emitter voltage difference ∆V_BE is:

$$\Delta V_{\mathrm{BE}}=-2V_{\mathrm{BE}1,R}+3V_{\mathrm{BE}2,\mathrm{R}}-V_{\mathrm{BE}3,\mathrm{R}}={\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}\ln \left({\displaystyle \frac{36}{1}}\ast {\displaystyle \frac{6}{16}}\right)={\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}\ln \left(13.5\right)$$

(13)

From the above equation, it can be seen that the value of ∆V_BE obtained after weighted subtraction is devoid of the error component associated with parasitic resistance (R_P). Consequently, this approach mitigates the impact of parasitic resistance R_P on the remote temperature-sensing accuracy.

3. Circuit Implementation

Figure 5 shows the overall architecture diagram of the remote temperature-sensing chip proposed in this paper. The chip is primarily comprised of several components, including a bias circuit, a bandgap reference, a reference voltage curvature compensation module, an incremental analog-to-digital converter (ADC), an oscillator, a compensation structure, and control logic. The working principle of the chip is that the bias circuit is driven by the control logic to generate different proportions of bias current, and the remote transistor generates different remote temperature signals V_BE at different proportions of bias current, and then the ADC samples it and compares it with the reference voltage V_REF generated by the bandgap reference to achieve the digitization of the remote temperature signal. Finally, a remote temperature reading D_out in degrees Celsius is obtained by digital processing. Additionally, the oscillator module within the chip supplies the necessary sampling clock for the overall circuit, while the reference voltage curvature compensation module implements second-order temperature compensation for the reference voltage. Through the compensation structure, the BETA value and the reverse Early voltage V_AR of the remote BJT can be detected and calculated so that the compensation factors 1/α_VAR and γ can be calculated to perform digital compensation for the remote temperature-sensing accuracy.

3.1. Compensation Structure Circuit

As outlined in Section 2, to mitigate the impact of Early error and BETA error on the remote temperature-sensing accuracy, it is essential for the compensation structure to effectively detect and compute the reverse Early voltage V_AR and the BETA value of the remote BJT. In the Gummel–Poon model, when the collector–base voltage V_BC of the BJT is set to zero, the DC magnification β can be approximated as:

$$\beta \approx {\beta }_0^{\prime }{(1-{\displaystyle \frac{V_{\mathrm{BE}}}{V_{\mathrm{AR}}}})}^{-1}$$

(14)

where β’₀ is the DC amplification of the triode without considering the Early effect. Thus, the inverse Early voltage V_AR of the triode can be obtained by measuring β under different V_BE. Specifically, the inverse Early voltage V_AR of the BJT can be calculated by measuring the DC amplification factor β_I1 and β_I2 of the remote BJT under two different bias currents. The calculation equation is as follows:

$$V_{\mathrm{AR}}={\displaystyle \frac{{\beta }_{\mathrm{I}1}{V}_{\mathrm{BE},\mathrm{I}1}-{\beta }_{\mathrm{I}2}{V}_{\mathrm{BE},\mathrm{I}2}}{{\beta }_{\mathrm{I}1}-{\beta }_{\mathrm{I}2}}}$$

(15)

where V_BE,I1 and V_BE,I2 are the base–emitter voltages of the remote triode under two different bias currents. The aforementioned equation indicates that V_AR can be derived from the BETA value. Therefore, the compensation structure only needs to detect the BETA value, enabling the calculation of the compensation factors 1/α_VAR and γ discussed in Section 2. The proposed compensation structure schematic diagram is shown in Figure 6.

The working principle of the compensation structure is as follows: When the chip samples and converts the remote temperature voltage signal V_BE, switches S1, S2, and S3 are closed, while switches S4 and S5 are disconnected, and the ADC samples the V_BE at different bias currents.

When the chip measures β of the remote BJT, it is measured two times. First measurement: Switches S2 and S5 are closed, while switches S1, S3, and S4 are disconnected. At this time, the bias current I_bias directly flows through the measuring resistor R_beta, and the ADC then samples the voltage (V_beta(I_E)) at both ends of R_beta, which can indirectly represent the current I_E flowing through the remote BJT emitter in the normal temperature measurement mode of the chip.

Second measurement: the base of the remote BJT is disconnected from the collector and then connected to the compensation structure circuit. At this time, switches S1, S4, and S5 are closed, while switches S2 and S3 are disconnected. At this time, the bias current I_bias flows through the remote BJT, and the base current I_B of the remote BJT flows through the measuring resistor R_beta. The ADC directly samples the voltage (V_beta(I_B)) at both ends of R_beta, which can indirectly represent the current I_B flowing through the base of the remote BJT in the normal temperature measurement mode of the chip.

Through these two sampling processes, it is possible to derive the emitter current I_E representing the voltage (V_beta(I_E)) and the base current I_B representing the voltage (V_beta(I_B)). Through these two sampling voltages, the bias current of the remote BJT’s β can be calculated at the digital backend, and the calculation equation is as follows:

$$\beta ={\displaystyle \frac{I_{\mathrm{E}}}{I_{\mathrm{B}}}}-1={\displaystyle \frac{V_{\mathrm{beta}}(I_{\mathrm{E}})}{V_{\mathrm{beta}}(I_{\mathrm{B}})}}-1$$

(16)

Based on the sampling and calculation methods, the β of the remote BJT under different bias currents can be obtained. Consequently, the compensation factors 1/α and γ can be calculated in the digital backend to digitally compensate the remote temperature-sensing accuracy.

3.2. Bias Circuit

The bias circuit is comprised of two modules. The first module is the reference current source, which is designed to produce a temperature-independent reference current that supplies current to other modules within the chip. The second module is a temperature-sensing front-end bias circuit, which is responsible for delivering bias current to the remote BJT. The operational principles of these two modules are elaborated upon in the following sections.

3.2.1. Reference Current Source

The β of the remote BJT is subject to variation in response to changes in the bias current. Additionally, the ambient temperature of the remote temperature-sensing chip does not remain constant at a specific temperature point. Consequently, it is imperative to establish a stable bias current that exhibits minimal sensitivity to temperature fluctuations in order to mitigate the impact of bias current variations on the DC magnification. The bias current within the chip is produced by a reference current source; therefore, the design of this reference current source must account for the effects of temperature changes. The objective is to generate a reference current (I_REF) characterized by low temperature drift. Figure 7 shows the specific circuit configuration of the reference current source implemented in the chip.

In this circuit, the emitter area ratio of BJT Q1 and Q2 is 1:8. The current traversing resistor R₁ demonstrates a positive temperature characteristic, which is referred to as the I_PTAT current.

$$I_{\mathrm{PTAT}}={\displaystyle \frac{\Delta V_{\mathrm{BE}}}{R_1}}$$

(17)

The current traversing resistance R2 demonstrates a negative temperature characteristic, which is referred to as the I_CTAT current.

$$I_{\mathrm{CTAT}}={\displaystyle \frac{V_{\mathrm{BE}}}{R_2}}$$

(18)

By overlaying the I_PTAT current with the I_CTAT current and appropriately selecting the resistance value of the resistor, it is possible to produce a reference current (I_REF) with a design target of 6 μA, which exhibits minimal sensitivity to variations in temperature.

$$I_{\mathrm{REF}}=I_{\mathrm{PTAT}}+I_{\mathrm{CTAT}}$$

(19)

Opamps A1 and A2 implement the conventional folding common-source–common-gate architecture, enabling a DC gain exceeding 70 dB. To mitigate the effects of offset voltage and 1/f noise on the precision of the current source, chopping technology is employed in operational amplifier A1. Compared to prior works [32,33], this paper adopts a current source structure to obtain a lower temperature drift coefficient (36 ppm/°C) over a wide temperature range (−55 °C to 125 °C).

3.2.2. Sensing Front-End Bias Circuit with Parasitic Resistance Cancellation

The main function of the temperature-sensing front-end bias module within the chip is to replicate the I_REF produced by the reference current source and subsequently supply a proportional bias current to the remote BJT. To mitigate the impact of parasitic resistance on the accuracy of remote temperature sensing, the bias module needs to provide a bias current in a ratio of 1:6:16, as outlined in the parasitic resistance elimination technique discussed in the preceding section. The specific circuit implementation scheme is shown in Figure 8.

The remote temperature-sensing chip presented in this study is designed to interface with multiple remote BJTs for the purpose of temperature monitoring. To mitigate the impact of coupling noise on the remote temperature-sensing accuracy, a differential connection method is employed between the chip and the remote BJTs. Due to the differential input configuration, parasitic resistors R₁ and R₂ are present on the two differential input lines. However, since the current passing through both resistors is identical, R₁ and R₂ can be represented as a single equivalent parasitic resistance, denoted as R_P.

$$R_{\mathrm{P}}=R_1+R_2$$

(20)

In the circuit, switches S1~S16 are utilized to modulate the magnitude of the bias current supplied to the remote BJT. The modulation is achieved through control logic signals (Ctrl1~Ctrl3), achieving a bias current ratio of 1:6:16 and thereby enabling the remote BJT to establish different V_BE. This, when combined with the ADC oversampling timing sequence, enables the ADC to sample and convert the different V_BE established by the remote BJT under three different bias conditions into digital codes and then perform weighted subtraction in the digital domain to eliminate parasitic resistance in the remote temperature signal (∆V_BE).

To minimize the impact of current ratio mismatch, dynamic element matching (DEM) technology is implemented within the circuit. After adopting DEM technology, the first-order error of the averaged remote temperature signal ΔV_BE,avg can be eliminated, leaving just the second-order error, which satisfies [31]:

$$\left|\Delta V_{\mathrm{BE},\mathrm{avg}}-\Delta V_{\mathrm{BE},\Delta \mathrm{N}=0}\right|<{\displaystyle \frac{1}{2}}{\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}{\left({\displaystyle \frac{\Delta N}{N}}\right)}^2$$

(21)

ΔN/N represents the maximum mismatch between the currents in each branch. In this circuit simulation, ΔN/N = 2%. Employing DEM technology reduces the residual inaccuracy of ΔV_BE,avg to only 2.6 μV, which may be ignored for temperature measurement.

Additionally, through the negative feedback of opamp A1, the voltage at the drain terminal of the MOS transistor in the current mirror remains consistent. This approach enhances the replication accuracy of the current mirror, thereby ensuring the precision of the current proportion flowing through the remote BJT.

3.3. Bandgap Reference Circuit

The bandgap reference module in the chip provides the reference voltage V_REF for the ADC to quantify the remote temperature signal V_BE. Because the remote temperature-sensing chip and the remote BJT are situated in distinct locations, the operating ambient temperature is also different. If the reference voltage V_REF is affected by the ambient temperature, it will affect the remote temperature-sensing accuracy. Therefore, it is essential for the bandgap reference to produce a low-temperature coefficient reference voltage. Figure 9 shows the bandgap reference and its curvature compensation circuit schematic diagram.

The I_REF current and I_PTAT current in the circuit are replicated in the reference current source, as shown in Figure 6, through the current mirror. Two I_PTAT currents with a ratio of 5:1 flow into the triodes Q_L and Q_R, and the accuracy of the replication current ratio is improved by DEM technology. At this time, the voltage across QR is V_BE, and the differential voltage between the V_BE values of the two BJTs is ΔV_BE. During the ADC sampling, V_BE and ΔV_BE are sampled in accordance with a ratio of 1:α. By adjusting the size of the sampling capacitance, the size of α can be adjusted to eliminate the first-order temperature coefficient in V_REF.

To produce a low-temperature drift reference voltage and mitigate its high-order temperature curvature, the technique of temperature-dependent current ratio reference curvature compensation is employed within the bandgap reference circuit. This is achieved by replicating the I_REF current and the I_PTAT current into two BJTs, Q_LC and Q_RC, which have an emitter area ratio of 1:5. Consequently, the voltage difference V_C between the two BJTs is expressed as follows:

$$V_{\mathrm{C}}=V_{\mathrm{BE},\mathrm{Q}1}-V_{\mathrm{BE},\mathrm{Q}2}={\displaystyle \frac{T_{\mathrm{r}}}{\mathrm{q}}}+{\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}+V_{\mathrm{T}}\ln \left({\displaystyle \frac{T}{T_{\mathrm{r}}}}\right)$$

(22)

where T_r is a reference temperature value, and there exists a curvature term analogous to V_REF in V_C. Consequently, V_C can serve as the curvature compensation signal. By superimposing the reference signal V_REF with the compensation signal V_C, it is possible to mitigate the temperature drift of the V_REF and achieve effective curvature compensation.

The generation of reference voltage and curvature compensation in this chip are realized through the process of ADC sampling. During this sampling process, V_REF is derived from the proportional accumulation of ΔV_BE and V_BE, followed by the addition of the compensation voltage V_C. The corresponding circuit schematic is shown in Figure 10. The signals φ₁, φ_1d, φ₂, and φ_2d represent two pairs of non-overlapping two-phase clock signals, which control the sampling and integration operations of the ADC. The PTAT voltage ΔV_BE, the CTAT voltage V_BE, and the curvature compensation voltage V_C are sampled using distinct capacitors. The scale coefficients α and ρ can be modified by adjusting the magnitude of the sampling capacitance. Furthermore, it is possible to eliminate the first-order temperature coefficient and the second-order temperature coefficient of the reference voltage. Consequently, the compensated reference voltage is denoted as V_REF,C.

$$V_{\mathrm{REF},\mathrm{C}}=V_{\mathrm{BE}}+\alpha \Delta V_{\mathrm{BE}}+\rho V_{\mathrm{C}}$$

(23)

To mitigate the effects of process variations on the first and second curvatures of the reference voltage compensation, the sampling capacitors of the ADC for ΔV_BE and V_C are designed as a capacitor array. The size of the sampling capacitors is adjustable via digital trimming bits, facilitating the modification of the proportional coefficients α and ρ to reduce the impact of process variations on compensation effectiveness.

3.4. Oscillator Circuit

The oscillator in the chip provides the working clock for the whole circuit. Since the operating ambient temperature of the chip is not stable, if the oscillation frequency is greatly affected by the temperature, the sampling of the remote temperature signal by the ADC will be affected, thus affecting the remote temperature-sensing accuracy. Therefore, it is imperative to design the oscillator with a low-temperature drift structure to ensure that the output clock remains minimally influenced by temperature variations.

Figure 11a shows the structure of the oscillator. The operational mechanism of the oscillator is as follows: To control the capacitor’s periodic charge and discharge through the output state and then compare it with the comparator input voltage (threshold voltage Vth of Mn1 and Mn2) so as to periodically change the output state of the comparator to achieve oscillating output. The oscillation frequency, denoted as f_OSC, is defined as follows:

$$f_{\mathrm{OSC}}={\displaystyle \frac{I_{\mathrm{charge}}}{2C{V}_{\mathrm{th}}}}$$

(24)

Figure 11b shows the I_charge current-generating circuit. The width-to-length ratio of Mn1~Mn4 is consistent, and their threshold voltage is the same. The magnitude of the current produced by the I_charge current is as follows:

$$I_{\mathrm{charge}}={\displaystyle \frac{1}{2}}{I}_2={\displaystyle \frac{V_{\mathrm{th}}}{2R}}$$

(25)

After substituting Equation (25) into Equation (26), f_OSC becomes:

$$f_{\mathrm{OSC}}={\displaystyle \frac{1}{4RC}}$$

(26)

The aforementioned equation indicates that the output frequency of the oscillator can be adjusted by adjusting the values of resistance and capacitance. The capacitor in the circuit is a metal–insulator–metal structure, and its capacitance variation with temperature is negligible. Consequently, the output frequency of the oscillator is predominantly influenced by the temperature drift of the circuit’s resistance. The low-temperature-drift output frequency of the oscillator can be realized by using the low-temperature-drift combined resistance of positive temperature coefficient and negative temperature coefficient in the circuit. By selecting the appropriate value of resistance and capacitance, the output frequency of the oscillator is approximately 500 kHz, and the temperature coefficient of the output frequency is 33 ppm/°C. To decrease the impact of process variations on oscillation frequency, the resistors in the charging circuit are designed in an array. Digital trimming bits can be used to regulate the size of the positive and negative temperature coefficient resistors, reducing the influence of process variations.

3.5. Incremental ADC

In comparison to the conventional ΔΣ ADC, the incremental ADC (IADC) is considered an improved architecture. A reset signal is introduced in the modulator and the decimation filter of the IADC. This signal triggers a reset at the beginning of each conversion cycle, allowing for the completion of a digital conversion of an analog input by the end of the cycle, thus achieving Nyquist rate conversion. The reset mechanism simplifies the design of the digital decimation filter, allowing for implementation with a straightforward accumulator. Additionally, it notably decreases design complexity, chip area, and power consumption requirements [34,35].

The ADC in the chip adopts the second-order incremental CIFF structure, as shown in Figure 12. To meet the requirements of high-precision temperature sensing, the ADC resolution should be within 0.05 °C, and the design target of the ADC’s Effective Number of Bits (ENOB) should be more than 14 bits, considering the margin. According to the design requirements, the ADC’s oversampling rate (OSR) is 256, and the sampling frequency is 500 kHz. The first-stage integrator uses a foldable common-source–common-gate amplifier to achieve a gain of 80 dB, and the second-stage integrator uses a similar structure to achieve a gain of 70 dB. To mitigate offset voltage and low-frequency flicker noise in the operational amplifier, both integrators incorporate chopping technology. Since the single-bit comparator only needs to judge the positive and negative of the input differential signal, the precision requirements for the comparator are relatively low, so the comparator in the ADC adopts the single-bit dynamic comparator structure.

Transient noise simulation was performed on the modulator. The amplitude of the input sinusoidal signal presented in the simulation environment is −3 dBFS, with a frequency of 325.52083 Hz. Figure 13 shows the simulation results of the output signal’s power spectral density (PSD) after conducting an FFT with a point count of 2¹³. According to the simulation results, the modulator’s ENOB is 14.89 bits.

To eliminate the effect of parasitic resistance, the sampling of the remote temperature signal voltage V_BE by the ADC should follow the parasitic resistance elimination principle described in Section 2. Therefore, the specific sampling process of the ADC for V_BE is as follows: initially, sampling 48 times of V_BE2, followed by sampling 16 times of −V_BE3, then sampling 64 times of −V_BE1, again sampling 16 times of −V_BE3, and finally sampling 48 times of V_BE2. The whole process is repeated 8 times to achieve 256 times of ΔV_BE sampling, which is a reset cycle (the conversion period is about 4 ms). In the whole sampling process of the ADC, there are positive sampling periods (sampling V_BE2) and negative sampling periods (sampling −V_BE1 and −V_BE3).

Through a reset cycle of positive and negative sampling processes, the ADC can achieve 256 ΔV_BE quantizations without parasitic resistance effects:

$$256{\displaystyle \frac{\Delta V_{\mathrm{BE}}}{V_{\mathrm{REF},\mathrm{C}}}}=8\ast (48{\displaystyle \frac{V_{\mathrm{BE}2}}{V_{\mathrm{REF},\mathrm{C}}}}-16{\displaystyle \frac{V_{\mathrm{BE}3}}{V_{\mathrm{REF},\mathrm{C}}}}-64{\displaystyle \frac{V_{\mathrm{BE}1}}{V_{\mathrm{REF},\mathrm{C}}}}-16{\displaystyle \frac{V_{\mathrm{BE}3}}{V_{\mathrm{REF},\mathrm{C}}}}+48{\displaystyle \frac{V_{\mathrm{BE}2}}{V_{\mathrm{REF},\mathrm{C}}}})$$

(27)

Subsequently, through the digital processing of the output signal (bs), it is possible to derive a remote digital temperature reading that is unaffected by parasitic resistance.

4. Experimental Result

The proposed remote temperature-sensing chip is designed based on a 0.18 μm CMOS process, and the layout is shown in Figure 14. The overall area of the chip is 550 μm × 600 μm, the working voltage is 1.8 V, and the digital compensation of the remote temperature-sensing accuracy is realized outside the chip.

The primary modules in the chip and the corresponding performance indicators are simulated and verified under the condition of full process angle. The simulation verification results will be shown in the following sections.

4.1. Reference Curvature Compensation Simulation Verification

The compensated reference voltage V_REF in the chip is formed by summating V_BE, ΔV_BE, and V_C through ADC sampling. The proportional coefficients α and ρ in Equation (27) can be adjusted by adjusting the sampling capacitance of the ADC in relation to ΔV_BE and V_C, so as to optimize the compensation effect of the first-order curvature and second-order curvature of the reference voltage.

Post-layout simulation was performed on the reference voltage’s variation within the temperature range of −55 °C to 125 °C using Spice simulation. Figure 15 shows the post-layout simulation results of the reference voltage V_REF,C for curvature compensation after adjusting the proportional coefficients α and ρ at the TT process angle. These post-layout simulation results show V_REF,C under the TT process angle.

It can be seen from Figure 16 that the first-order curvature and second-order curvature in the reference voltage V_REF,C have been effectively eliminated after compensation, thereby showing the characteristics of higher-order curve variations. Within the temperature range of −55 °C to 125 °C, V_REF,C exhibits a minimal variation of only 0.8 mV, which translates to an impact on remote temperature measurement accuracy of approximately ±0.1 °C, with a temperature drift coefficient of 4.4 ppm/°C. To validate the effectiveness of this compensation, the post-layout simulations of V_REF,C were conducted under a working voltage range of 1.6 V to 2 V, and the results of this simulation are presented in Figure 16.

As can be seen from Figure 16, the compensation effect of V_REF,C will be affected by the process angle. Among them, the compensation effect is the worst at the (1.6 V, SS_MOS, FF_PNP) process angle. The values of V_REF,C exhibit a variation of 6 mV within the temperature range of −55 °C to 125 °C, resulting in a temperature drift coefficient of 29.2 ppm/°C.

In this worst case, we adjusted the proportional coefficients α and ρ and subsequently conducted a post-layout simulation verification. The result of this verification is presented in Figure 17. As can be seen from Figure 17, after adjusting the proportional coefficients α and ρ, the reference voltage V_REF,C exhibits a change of only 0.7 mV across the temperature range of −55 °C to 125 °C, which affects the remote temperature measurement accuracy by at most ±0.1 °C, with the temperature drift coefficient being reduced to a lower level of 4 ppm/°C. This result substantiates the viability of the trimming design, which effectively ensures the compensation of the reference curvature after tape-out, thereby mitigating the influence of chip temperature change on the remote temperature measurement accuracy.

4.2. Simulation Verification of Parasitic Resistance Elimination Technology

To verify the effectiveness of the proposed parasitic resistance elimination technology, in the simulation environment, two resistors are connected in series on the lead between the remote BJT and the remote temperature-sensing chip to simulate the parasitic resistance. By comparing ∆V_BE,R generated by the remote BJT with ∆V_BE,ADC sampled by the ADC, we observe whether the two values are consistent to determine whether there is an influence of parasitic resistance. A post-layout simulation comparison was conducted between ∆V_BE,R and ∆V_BE,ADC in a simulation environment ranging from −55 °C to 125 °C. The post-layout simulation results for ∆V_BE,R and ∆V_BE,ADC are presented in

Table 1. Comparison of post-layout simulation results ∆V_BE,R and ∆V_BE,ADC.

Simulated Ambient Temperature	∆VBE,R (mV)	∆VBE,ADC (mV)
−55 °C	50.48	50.47
−10 °C	60.33	60.33
27 °C	68.44	68.43
85 °C	81.26	81.25
125 °C	90.15	90.13

.

As illustrated in Table 1, within a temperature range of −55 °C to 125 °C, the maximum difference between ∆V_BE,R and ∆V_BE,ADC is merely 0.02 mV, resulting in an approximate impact of 0.01 °C on the remote temperature measurement accuracy. The comparison results show that the effect of parasitic resistance on ∆V_BE,actual is basically eliminated, which verifies the effectiveness of the proposed parasitic resistance elimination technology.

4.3. Performance Simulation Verification of Remote Temperature-Sensing Chip

4.3.1. Compensation Calculation Method

Based on the quantization process of the ADC on the remote temperature voltage signal ∆V_BE, after considering the influence of the DC amplification factor β and the reverse Early voltage V_AR of the remote BJT on ∆V_BE (because the influence of parasitic resistance has been eliminated through the parasitic resistance elimination technology, it is unnecessary to consider), the digital linear output Y_final after the quantization by the ADC is as follows:

$$Y_{\mathrm{final}}={\displaystyle \frac{\Delta V_{\mathrm{BE},\mathrm{final}}}{V_{\mathrm{REF},\mathrm{C}}}}=\left(3\cdot {\displaystyle \frac{V_{\mathrm{BE}2}}{V_{\mathrm{REF},\mathrm{C}}}}-{\displaystyle \frac{V_{\mathrm{BE}3}}{V_{\mathrm{REF},\mathrm{C}}}}-2{\displaystyle \frac{V_{\mathrm{BE}1}}{V_{\mathrm{REF},\mathrm{C}}}}\right)={\alpha }_{\mathrm{VAR}}\cdot {\displaystyle \frac{\frac{\mathrm{k}T}{\mathrm{q}}\left(\ln \left({\gamma }_1^2\cdot {\gamma }_2^3\cdot {\gamma }_3\right)+\ln \left(13.5\right)\right)}{V_{\mathrm{REF},\mathrm{C}}}}$$

(28)

where γ₁, γ₂, and γ₃ are the compensation factors of the remote BJT under different bias currents (bias current ratio of 1:6:16), respectively.

Through the proposed compensation structure, the DC magnification β of the remote BJT can be measured and calculated under different bias currents. Based on this, the compensation factors 1/α_VAR, γ₁, γ₂, and γ₃ can be calculated. The compensation factor is calculated using the formula described in Equations (29)–(31).

$${\gamma }_1={\displaystyle \frac{1+{\beta }_1}{{\beta }_1}}$$

(29)

$${\gamma }_2={\displaystyle \frac{{\beta }_2}{1+{\beta }_2}}$$

(30)

$${\gamma }_3={\displaystyle \frac{1+{\beta }_3}{{\beta }_3}}$$

(31)

$${\displaystyle \frac{1}{{\alpha }_{\mathrm{VAR}}}}={\displaystyle \frac{1}{1+\frac{\mathrm{k}T}{{\mathrm{qV}}_{\mathrm{AR}}}}}$$

(32)

where β₁, β₂, and β₃ are the DC amplification factors of the remote BJT under different bias currents (bias current ratio of 1:6:16), respectively. The reverse Early voltage can be calculated using Equation (15).

These compensation factors can be used to compensate the errors introduced by β and V_AR in the digital output Y_final, thereby improving the remote temperature measurement accuracy. The compensated digital output Y_final,comp is as follows:

$$Y_{\mathrm{final},\mathrm{comp}}={\displaystyle \frac{\mathrm{k}T}{\mathrm{q}}}{\displaystyle \frac{\ln \left(13.5\right)}{V_{\mathrm{REF},\mathrm{C}}}}$$

(33)

4.3.2. Post-Layout Simulation Results of the Remote Temperature Measurement Accuracy

The post-layout simulations environment for verifying the remote temperature measurement accuracy of the chip has been established in accordance with actual testing conditions. Specifically, the remote temperature-sensing chip and the remote BJT are positioned in two different ambient temperatures. In the simulation, the environment temperature of the chip is maintained at 27 °C, while the simulation environment temperature of the remote transistor varies within the range of −55 °C to 125 °C. The temperature data of the remote transistor measured by the chip is compared with the standard temperature data, and the difference between the two is calculated to obtain the remote temperature measurement error of the chip.

Initially, the remote temperature-sensing accuracy is evaluated when the remote temperature-sensing chip is connected to the discrete BJT, which utilizes the simulation model of the commonly recommended CMPT3904. The ambient temperature of the chip is maintained at 27 °C, while the ambient temperature of the remote BJT is varied from −55 °C to 125 °C. The performance of the chip was verified under the five process angles of tt, ss, ff, snfp, and spfn, and the post-layout simulation results of the remote temperature-sensing accuracy are shown in Figure 18a. Within the temperature range of −55 °C to 125 °C, the remote temperature-sensing chip demonstrates a measurement accuracy of ±0.25 °C.

The compensation factors 1/α and γ are calculated through the chip compensation structure, and the remote temperature-sensing accuracy of the CMPT3904 connected to the chip is digitally calibrated. The calibrated results are shown in Figure 18b. Within the temperature range of −55 °C to 125 °C, the remote temperature-sensing chip demonstrates a measurement accuracy of ±0.25° C.

There was not much difference between the results with and without compensation. An in-depth analysis of this outcome was undertaken, and the reasons are as follows: In the model of the discrete BJT CMPT3904, its V_AR = 100 V and β > 100. According to the theory proposed in [31], the influence of V_AR and β on the remote temperature measurement accuracy is much less than 0.1 °C. Therefore, there is no need to compensate the Early error and Beta error with the compensation structure. Thus, the difference between results with and without compensation is very small.

Subsequently, the remote temperature-sensing accuracy when the remote temperature processing chip is connected to the parasitic BJT is verified, and the overall verification is also conducted under five process angles. The post-layout simulation results of the remote temperature-sensing accuracy are shown in Figure 19a. Within the temperature range of −55 °C to 125 °C, the remote temperature-sensing chip demonstrates a measurement accuracy of −0.7 °C to +0.6 °C.

The compensation factors 1/α and γ are calculated through the chip compensation structure, and the remote temperature-sensing accuracy of the parasitic BJT connected to the chip is digitally calibrated. The calibrated results are shown in Figure 19b. The remote temperature-sensing chip connected to discrete and parasitic triodes can reach the temperature-sensing accuracy of ±0.25 °C, which meets the demand of high-precision temperature sensing.

The remote temperature-sensing accuracy significantly improved with compensation, and the reasons are as follows. In the model of the parasitic BJT, its V_AR is 32 V. According to the theoretical calculation proposed in [31], V_AR will introduce a temperature measurement error of ±0.1 °C. The β under the μA-class bias current provided by the chip is 2.44, and it will change by 0.02 with different bias currents. According to the theoretical calculation proposed in [30], β will introduce a temperature measurement error of ±0.2 °C. The influence of β and V_AR on the remote temperature-sensing accuracy was reduced with compensation, resulting in a significant improvement in the remote temperature-sensing accuracy.

The Monte Carlo results of the post-layout simulation for the remote temperature-sensing accuracy with compensation when the chip’s environment temperature is 27 °C, and the remote BJT’s temperature environment is −55 °C, 27 °C, and 125 °C, as shown in Figure 20.

Figure 20 illustrates that remote temperature-sensing accuracy is slightly more influenced by process deviations and mismatch at −55 °C and 125 °C. This impact can be significantly decreased by adopting a two-point calibration method.

The verification of the remote temperature-sensing accuracy of the chip was performed post-simulation under the operational conditions of 27 °C and a supply voltage range of 1.6 to 2 V. Figure 21 presents the results. The chip exhibits a voltage sensitivity of approximately 0.6 °C/V.

The post-layout simulation’s operating current of the chip is about 150 μA, corresponding to an overall power consumption of 270 μW.

Table 2. Comparison with recently reported remote temperature-sensing chips.

Parameters	1 This Work	[18]	[19]	[20]	[22]
Process	180 nm	65 nm	65 nm	22 nm	32 nm
Remote device type	Parasitic/Discrete BJT	Discrete BJT	MOSFET	Parasitic BJT	Parasitic BJT
Area/mm2	0.33	0.2	0.09148	0.004264	0.02
Supply voltage/V	1.8	1.5	1	1	1.05
Temp. range/°C	−55~125	−40~130	0~95	−30~120	−10~110
Inaccuracy/°C	±0.25	±0.3	−0.35~+0.58	±1.07	±5
Resolution/°C	0.015	0.125	0.054	0.58	0.45
Power/μW	270	-	4.053	50	1600
Conversion rate/ms	4	2	1.2	0.032	0.83
2 FoMs/nJ·K2	0.24	199	0.014	0.54	268.92

¹ Post-Layout Results. ² Resolution FoM = Energy/Conversion × Resolution².

summarizes the overall performance of the proposed chip and compares it with the recently reported remote temperature-sensing chips. The proposed chip can compensate not only the precision of the remote discrete BJT but also the remote parasitic BJT, and it has significant advantages of wide temperature range and high precision, which meet the high-precision thermal management requirements of advanced computing systems. Compared with recently reported remote temperature-sensing chips, its figure of merit (FoM) remains highly competitive.

5. Conclusions

In conclusion, this paper presents a remote temperature-sensing chip adaptive for both discrete and parasitic BJTs. By employing parasitic resistance elimination technology and a compensation structure, the chip can achieve high-precision temperature measurement compensation when it is connected to remote discrete BJTs and parasitic BJTs for temperature sensing, which meets the requirements of high-precision thermal management in advanced computing systems. The proposed remote temperature-sensing chip is designed based on a 0.18 μm CMOS process; the chip area is 0.33 mm², and the working voltage is 1.8 V. The post-layout simulation results show that the chip can achieve a temperature-sensing accuracy of ±0.3 °C within the temperature range of −55 °C to 125 °C after digital compensation when sampling discrete transistors and parasitic transistors are used for remote temperature measurement. The power consumption of the chip is 270 μW, and the FoM is 0.24 nJ·K².