A 57–64 GHz Receiver Front End in 40 nm CMOS

Abstract

The global allocation of over 5 GHz of spectral bandwidth around the 60 GHz frequency band offers significant potential for ultra-high data rate wireless communication over short distances and enables the implementation of high-resolution frequency-modulated continuous-wave (FMCW) radar applications. In this study, a Front-End Receiver covering frequencies from 57 to 64 GHz was designed and characterized in a 40 nm CMOS process. The proposed architecture includes a Low-Noise Amplifier (LNA), a novel double-balanced mixer offering variable conversion gain, and a low-power class-C Voltage-Controlled Oscillator (VCO). From post-layout simulation results, the LNA presents a noise figure (NF) less than 4.8 dB and a gain more than 19 dB, while the input compression point (P1dB) reaches −15.6 dBm. The double-balanced mixer delivers a noise figure of less than 11 dB, a conversion gain of 14 dB, and an input-referred compression point of −13 dBm. The VCO achieves a phase noise of approximately −93 dBc/Hz at 1 MHz offset from 60 GHz and a tuning range of about 8 GHz, dissipating only 6.6 mW. Overall, the receiver demonstrates a maximum conversion gain of more than 39 dB, a noise figure of less than 9.2 dB, an input- referred compression point of −37 dBm, and a power dissipation of 56 mW.

1. Introduction

The rising demand for high-throughput wireless technologies has driven extensive efforts towards the design of advanced integrated circuits and systems designed to function at millimeter-wave (mm-wave) frequencies. In recent years, millimeter-wave transceivers have garnered significant attention for enabling ultra-high-speed wireless communication, especially for future 5G, 6G, and beyond applications [1,2]. The unlicensed 60 GHz ISM frequency band (57–64 GHz) offers a substantial bandwidth, making it an ideal candidate for supporting high-throughput wireless communication systems. This frequency range vastly contributes to the development of advanced communication links designed for short-range applications, such as those targeting the IEEE 802.15.3c and WiGig 802.11ad standards [2,3]. In both standards, the 60-GHz band includes four channels, each with a bandwidth of 1.76 GHz, as illustrated in Figure 1.

The very wide spectrum available in the ISM band provides the opportunity for ultra-fast communication with low latency, benefiting a wide array of devices and services. In addition to that, the 57–64 GHz frequency band has recently emerged as an appealing choice for radar applications [4,5]. The broad available bandwidth allows for achieving excellent range resolution in frequency-modulated continuous-wave (FMCW) systems [6]. Developing efficient and high-performance receivers that can operate within this band is essential for meeting the growing demands. When compared to SiGe HBT technologies, CMOS technology offers distinct advantages, including lower power consumption and a higher level of integration, particularly in the 60 GHz frequency range. These characteristics render CMOS an attractive choice for millimeter-wave applications, enabling more compact and cost-effective solutions [7]. However, challenges remain in designing Low-Noise Amplifiers, high-conversion-gain mixers, and oscillators that produce high-purity signals. These challenges stem from the limitations of CMOS transistors, which operate close to their unity gain frequency (f_T), and the reduced quality factor of passive components at these frequencies [8].

A typical architecture of a 60 GHz direct-conversion receiver is illustrated in Figure 2 below. Direct-conversion receiver architecture offers advantages over heterodyne designs at 60 GHz due to its simplified structure, enabling full CMOS integration, a reduced chip area, and lower power consumption. By eliminating intermediate frequency stages and image rejection filters, it supports wideband operation and scalability, making it ideal for compact, low-cost, and high-performance at 60 GHz [9]. At the heart of the front-end design, a Low-Noise Amplifier plays a pivotal role as the most critical component in the receiver chain. Its performance directly influences the total noise figure of the receiver, as it is the first element following the antenna. To ensure optimal receiver performance, the LNA must offer both a low-noise figure and sufficient gain to minimize the impact of noise from subsequent stages, thus maintaining the integrity of the signal throughout the receiver chain. Following the LNA, a down-converting mixer is responsible for converting the high-frequency input signal to the baseband frequency range, facilitating further processing by an Analog-to-Digital Converter (ADC). Selecting an IF frequency of roughly 1.8 GHz aligns with the standardized channel bandwidth. This frequency translation is crucial for digitizing the signal. A Voltage-Controlled Oscillator (VCO) serves as a key element of the Phase-Locked Loop (PLL), imposing the frequency range of operation and the phase noise performance of the loop. The high-frequency signal generated by the VCO is necessary for the frequency conversion process. It is instrumental in enabling the receiver to efficiently down-convert signals from the 60 GHz band to a lower intermediate frequency (IF frequency). However, mm-wave VCOs present several challenges and trade-offs that must be carefully considered. These include balancing the tuning range, phase noise, and power consumption. Achieving an optimal tuning range is essential for accommodating the wide ISM frequency spectrum, while minimizing the phase noise is critical to preserving signal integrity.

The combined performance of the LNA, down-conversion mixer, and VCO directly impacts the receiver’s performance in a direct-conversion architecture. Together, these components are the core of a direct-conversion receiver. In such a system, achieving low power consumption, high linearity, and efficient noise suppression are critical to maintaining the quality of communication, particularly at high frequencies like 60 GHz. To tackle these challenges and shed light on key unresolved issues, this paper presents the design and implementation of an energy-efficient 60 GHz receiver front end including a Voltage-Controlled Oscillator. This paper introduces a 60 GHz Low-Noise Amplifier presenting a gain of more than 20 dB, a noise figure less than 4.5 dB, and a 3 dB bandwidth of more than 7 GHz, while also showing a high-input compression point across 57–64 GHz. In addition, a down-conversion mixer with variable conversion gain featuring a double-balanced transformer-coupled topology between the Gm and the Switch stage is analyzed. The post-layout simulation results indicated a conversion gain near 14 dB for an input LO power set to −6 dBm, while the noise figure remained less than 10 dB for an IF frequency spanning 2 GHz (0–2 GHz). Furthermore, a generator spanning from 56.6 to 65.5 GHz, incorporating a fundamental class-C 30 GHz VCO, is also included. The VCO core employs an analog MOS varactor for coarse frequency tuning, complemented by a 3-bit binary-weighted capacitor bank to achieve fine-tuning resolution. This approach minimizes the gain and gain variability of the fundamental VCO (K_VCO), leading to improved phase noise levels. Phase noise values at the output span from −92.2 to −96.1 dBc/Hz at 1 MHz offset from the carrier. The total conversion gain of the receiver reached more than 39 dB, and the Single Sideband (SSM) noise figure remained below 9.2 dB, while the power consumption was 56 mW.

This paper presents the detailed design and implementation of a highly integrated receiver front end in 40 nm CMOS technology, capable of delivering high and tunable gain and a competitive noise figure without compromising linearity and preserving power consumption at low levels. A key innovation lies in the use of a fundamental Voltage-Controlled Oscillator (VCO) that directly covers the entire 57–64 GHz frequency band, eliminating the need for frequency doubling stages typically required in alternative architectures that rely on fundamental VCOs operating near 30 GHz. This not only simplifies the design but also significantly reduces area and system complexity. In addition, a high-frequency down-conversion mixer is proposed that integrates capacitive neutralization in the transconductance (Gm) stage to enhance gain, while employing a dual-tapped transformer to inductively couple the Gm and the Switch stage. This transformer not only provides DC isolation between the stages but also serves as a compact signal-transfer network. The combined approach leads to an extended 3 dB bandwidth, a higher conversion gain, and improved noise performance, making the mixer well suited for broadband mm-wave applications. The integration of the front end with the fundamental VCO results in a compact, power-efficient, and fully functional front-end solution that is ideally suited for emerging 60 GHz applications. Importantly, the architecture can support dual functionality, enabling both high-speed wireless communication and radar sensing within the same system—paving the way for versatile, next-generation millimeter-wave platforms, such as emerging joint communication and sensing (JCAS) systems, which demand both high-resolution radar capabilities and high-throughput data links within the same hardware platform [10].

The paper follows this structure: In Section 2, the main elements of the receiver are analyzed and implemented, while design considerations regarding the proposed structures are also introduced, highlighting the operational principle in each of them in the following order: (1) Low-Noise Amplifier (LNA); (2) down-conversion mixer; and (3) Voltage-Controlled-Oscillator (VCO). Furthermore, in each circuit, post-layout simulation results are given and compared with other cutting-edge designs in the 60 GHz band. Section 3 details the co-integration of the LNA, the mixer, and the VCO, while Section 4 discusses the results of the receiver front end. Finally, Section 5 concludes the paper.

2. 60 GHz Receiver Components

2.1. Low-Noise Amplifier (LNA)

The Low-Noise Amplifier is one of the most critical requirements of a receiver front end, as its noise figure and its gain mainly dictate the overall noise performance of the front end [11].

A two-stage differential transformer-coupled 60 GHz Low-Noise Amplifier (LNA) was designed as the input stage following the antenna. The electrical schematic of the proposed LNA structure is shown in Figure 3. A differential topology instead of a single-ended structure was adopted to suppress common-mode disturbances and enhance overall robustness in high-frequency operation [12].

Initially, a balun (Balun1) converts the single-ended signal from the antenna to the differential. The use of a center-tapped secondary winding for biasing the first stage eliminates the need for bulky DC-blocking capacitors, which typically degrade the noise figure at 60 GHz due to their low-quality factor at such high frequencies [11]. The first balun is a stacked configuration of two windings with the same width of 6 μm and is illustrated in Figure 4a. The primary winding is made of M8 copper metal and the secondary winding of Aluminum. The two top metals are the furthest away from the lossy silicon substrate. Thus, improved quality factor and hence total better noise and gain performance is accomplished. The simulation characteristics obtained from Cadence’s EMX of the first balun (Balun1) are illustrated in Figure 4b. The designed balun achieves a phase imbalance of just 0.9 degrees alongside an amplitude imbalance of 0.34 dB at 60 GHz. The input balun and inductor (L1) were designed to provide broad input matching alongside the pad capacitance of 30 fF.

The LNA consists of two common-source magnetically cascaded stages utilized by the transistors (M₁–M₄) and transformer T₁. Both stages utilize capacitive neutralization for improved gain and stability at mm-wave frequencies. Capacitive neutralization capacitors (C_n = 8fF) reduce the unwanted capacitance between the gate and the drain (C_GD), leading to superior voltage gain, improved stability, and reverse isolation [13,14,15]. Figure 5a illustrates the proposed topology for the core of each LNA stage, and in Figure 5b, the simplified small-signal model for calculating the effective transconductance (G_m) is illustrated.

It follows that

$${\mathrm{G}}_{\mathrm{m}}={\displaystyle \frac{{\mathrm{I}}_{\mathrm{o}\mathrm{u}\mathrm{t}+}-{\mathrm{I}}_{\mathrm{o}\mathrm{u}\mathrm{t}-}}{{\mathrm{V}}_{\mathrm{I}\mathrm{N}+}-{\mathrm{V}}_{\mathrm{I}\mathrm{N}-}}}={\displaystyle \frac{{\mathrm{I}}_{\mathrm{o}\mathrm{u}\mathrm{t}}}{{\mathrm{V}}_{\mathrm{I}\mathrm{N}}}}$$

(1)

$${\mathrm{I}}_{\mathrm{o}\mathrm{u}\mathrm{t}+}={\mathrm{V}}_{\mathrm{I}\mathrm{N}+}({\mathrm{g}}_{\mathrm{m}}-s{\mathrm{C}}_{\mathrm{G}\mathrm{D}}+\mathrm{s}{\mathrm{C}}_{\mathrm{n}})$$

(2)

$${\mathrm{I}}_{\mathrm{o}\mathrm{u}\mathrm{t}-}={\mathrm{V}}_{\mathrm{I}\mathrm{N}-}({\mathrm{g}}_{\mathrm{m}}-s{\mathrm{C}}_{\mathrm{G}\mathrm{D}}+\mathrm{s}{\mathrm{C}}_{\mathrm{n}})$$

(3)

From Equations (1)–(3):

$${\mathrm{G}}_{\mathrm{m}}={\mathrm{g}}_{\mathrm{m}}-\mathrm{s}{(\mathrm{C}}_{\mathrm{G}\mathrm{D}}-{\mathrm{C}}_{\mathrm{n}})$$

(4)

As shown in Equation (4), the effective transconductance is improved as the inserted capacitance C_n cancels a portion of C_GD, leading to a larger effective transconductance and hence an improved gain. The value of C_n is chosen as a compromise between gain improvement and instability.

The RF signal is propagated through the second stage via a dual-tapped transformer (T₁). The transformer, which is a stacked configuration of M8 and Aluminum with a width of 7 μm serves a dual purpose. It serves as a load for the first amplification stage (M_1, M₂) and provides the bias for the second stage (M₃, M₄). The output signal passes to a second balun (Balun2) to be reconverted to single-ended for measurement purposes. Inductor L₂ contributes to output matching at the output port and will be eliminated when the LNA drives the mixer. All the transistors in the proposed design are NMOS RF LVT transistors. The first amplification stage (M₁, M₂) was designed to achieve low noise. Thus, the transistors are biased around a minimum noise figure current density of 0.1 mA/μm. The widths of the transistors M₁ and M₂ were chosen to be 1 × 30 μm. The first stage draws 5 mA from a 1.1 Volt supply. The transistors of the second stage (M₃, M₄) have a width of 2 × 24 μm to provide more gain and improved linearity. The second stage draws 13 mA from the power supply. The total power consumption reached 19.8 mW. All the transistors in the LNA have a channel length of 40 nm. The capacitors C_B in Figure 3 are decoupling capacitors and contribute to the symmetry of the circuit regarding the center tap of the baluns, as they also provide a low resistance path for the AC signal to ground. Overall, the proposed LNA employs capacitive neutralization in both stages—a well-established technique for improved gain and stability—combined with a carefully designed input balun that minimizes phase and amplitude imbalance. This co-optimization enables broadband matching, high gain, and improved noise figure.

The characteristics of the proposed design are summarized in

Table 1. LNA component parameters.

Parameter	Value
WM1–M2	1 × 30 μm
WM3–M4	2 × 18 μm
Cn	8 fF
L	40 nm
T1: Lp/Ls, Qp/Qs	175/170 pH, 15/16.5
CB	5 pF
VB1	560 mV
VB2	600 mV

below.

LNA Post-Layout Simulation Results

The layout of the proposed LNA is illustrated in Figure 6. The total area of the LNA including the pads and the output matching inductor is 915 × 336 μm. The pad capacitance has been taken into account for both the input and output matching. Decoupling capacitors have been placed for the DC-bias voltages to establish a strong AC ground.

The post-layout simulation results of the LNA are demonstrated in Figure 7. They were obtained from multiport S Parameter simulation in Cadence’s EMX. The simulation captured all the resistive, capacitive and inductive parasitics that limit performance at mm-wave frequencies. The LNA has a simulated gain of 20.1 dB at 60 GHz alongside a NF of 4.3 dB at the same frequency. The −3 dB gain bandwidth exceeds 7 GHz, ranging from 56.88 to 64.1 GHz, while the NF variation stays below 0.5 dB in the same frequency range. A return loss (S11) below −10 dB was achieved for the input port across the whole bandwidth, while the output port showed a return loss (S22) better than −8.5 dB across the whole bandwidth of interest. The isolation between the input and output port (S₁₂) exceeded −50 dB across the whole bandwidth.

To verify the linearity of the designed LNA, its output power (Pout) was swept versus the input power (Pin) at 60 GHz. The results are depicted in Figure 8. As indicated, the −1 dB compression point at the input (P−1dB) reached −15.6 dB. For an SNR of 16 dB, which is reasonable for both 60 GHz communication systems [16] (e.g., high-speed wireless links) and radar sensors (e.g., short-range detection), the sensitivity at 60 GHz reached −61.8 dBm for a 2 GHz signal bandwidth.

Table 2. Comparison with state-of-the-art 60 GHz CMOS LNAs.

Reference	Hardware	FREQ (GHz)	Gain (dB)	PDC (mW)	NFMIN (dB)	IP1 (dBm)	Area (mm2)	Process
[17]	measured	50.6–67	16.8	33	4.4	−13	0.1 1	40 nm CMOS
[18]	measured	51.5–70	20	8.1	3.3	−23.9	0.2	22 nm FD-SOI
[19]	measured	55–65	19.8	18	6	−29.5	0.2	40 nm CMOS
[20]	post-layout	54–63	22.5	29.9	4.4	−16.1	0.09 1	40 nm CMOS
[21]	measured	56–61	20.2	28	5.16 2	−25	0.43	65 nm CMOS
This work	post- layout	57–64	20.1	19.8	4.2	−15.6	0.28	40 nm CMOS

¹ core area, ² simulated.

displays a comparison of the proposed LNA with state-of-the-art designs operating within the same frequency range. In general, the proposed design demonstrated a better noise figure and higher linearity when compared to similar designs, without consuming excessive power.

2.2. Down-Conversion 60 GHz Mixer

To achieve a larger conversion gain, an improved noise figure, and better isolation between the mixer ports, an active double-balanced mixer was chosen instead of a single-balanced mixer [22,23]. Several research papers have investigated active mixers at 60 GHz. In [24], a down-conversion mixer in 22 nm FD-SOI process was presented. Although the proposed design captured the whole bandwidth of interest (53–67 GHz), it offered a moderate conversion gain of 8 dB and a noise figure of 13 dB for an IF frequency between 3 and 5 GHz. The authors of [25] presented an inductorless 60 GHz down-conversion mixer integrated into a 22 nm FD-SOI CMOS technology. The mixer performed a zero-IF conversion with a −3 dB corner frequency at 1 GHz. While the required LO power was −4 dBm, the maximum differential conversion gain was limited to 6 dB. Furthermore, in [26] and in [27], two 60 GHz mixers implemented in 65 nm CMOS are cited. Both mixers presented low power consumption and moderate noise figures at near 12 dB, albeit the conversion gain was limited to near 10 dB in both designs. The aim of the proposed down-conversion mixer in this work is to deliver a conversion gain exceeding 13 dB, with the added flexibility of adjustable gain and also a moderate noise figure without a considerable increase in the overall power consumption.

Figure 9a presents the traditional double-balanced Gilbert cell mixer [11]. At the RF port, a differential pair (transistors M₁, M₂) converts the RF voltage to a current that afterwards is steered left and right by a double-balanced differential pair (transistors M₃–M₆). Finally, at the output, the IF current is converted to a voltage for further amplification and filtering by the baseband amplifier. The first stage is called the GM stage and contributes vastly to the conversion gain of the mixer. Transistors M3–M6 employ the Switch stage of the mixer.

In general, the conversion gain of this type of mixer can be expressed as [28]:

$${\mathrm{G}}_{\mathrm{c}}\cong {\mathrm{G}\mathrm{m}}_1\times {\displaystyle \frac{2}{\mathrm{\pi }}}$$

(5)

where R₁ represents the load resistance at the IF port and Gm₁ is the effective transconductance of the input transistors at the RF port. As seen from Equation (5), improving the conversion gain of the down-conversion mixer requires using a large load resistance and/or increasing the transconductance of the GM stage.

A large bias current is required for the input differential pair to provide a larger transconductance and thus larger conversion gain. The mixer illustrated in Figure 9a presents major difficulties, especially in mm-wave frequencies. First, the capacitance at the intermediate node of the GM stage and the Switch stage (node X) limits the conversion gain and increases the noise figure considerably. In addition to that, as the supply voltage is divided between the Switch stage and the GM stage, voltage headroom is limited. The GM stage requires a large drain-to-source voltage (V_DS) to achieve large transconductance and linearity. A larger DC voltage at node X would result in a Gm improvement regarding the GM stage, albeit it would necessitate a smaller resistor at the drains of the Switch stage, which would decrease the conversion gain, as evident from Equation (5). Finally, as the LO waveform differs from the ideal square wave, all the transistors (M₃–M₆) in the Switch stage remain ON simultaneously for part of the period [11]. This raises the noise figure at the IF port considerably. One remedy would be to decrease the bias current and hence the noise figure of the Switch stage, albeit the reduction in the effective transconductance of the GM stage would decrease the conversion gain. A remedy for these challenges is achieved by implementing the topology shown in Figure 9b. Two PMOS transistors (M₇, M₈) act as a current helper, providing the large DC current only for the GM stage, which is required for a large transconductance and hence a larger conversion gain. Thus, for the same resistor in the drain of the Switch stage, the conversion gain due to the larger Gm is increased [28,29]. On the other hand, the design in Figure 9c completely isolates the DC-path of the Gm stage with the DC path of the Switch stage [30]. The GM stage is inductively coupled with the Switch stage by a transformer (T1). This transformer serves a triple purpose. Firstly, it absorbs the parasitic capacitances between the stages, increasing the conversion gain and improving the noise figure. In addition, most importantly, it decouples the two stages from the same DC current and DC voltages. The two stages are biased separately, and a more proper biasing can be done. The GM stage is biased to provide a large conversion gain. The drain voltage of the GM stage is set to the supply voltage through the center tap of transformer T1, leading to a larger conversion gain. The source voltage of the Switch stage is set to ground to sink the current via the center tap of the secondary winding of the transformer. Furthermore, a small DC current is provided for the Switch stage to improve the noise figure. Finally, the isolation between the RF and the LO port is greatly enhanced. Figure 10 compares the three alternatives depicted in Figure 9 regarding the conversion gain and the noise figure. As shown, the designs depicted in Figure 9b and in Figure 9c demonstrate similar performance, while the topology in Figure 9a shows by far inferior performance.

The proposed design, illustrated in Figure 11a, builds upon the topology presented in Figure 9c by incorporating a neutralization capacitor C_N to significantly boost the total conversion gain.

A cross-coupled transistor differential pair with neutralization capacitors (C_N) is used for the GM stage to reduce the gate-drain (C_GD) parasitic capacitance and increase the effective transconductance at 60 GHz. In addition to that, the conversion gain of the mixer can be tuned by three switches implemented by PMOS transistors (M₇–M₉). These switches alter the equivalent resistance of the primary coil of transformer T₁, lowering the conversion gain when turned on. The conversion gain of the proposed structure is given in Equation (6) below, indicating that a larger coupling coefficient for the transformer connecting the GM stage with the Switch stage is beneficial for the conversion gain, albeit it will narrow the bandwidth of the mixer. In addition, the large signal transconductance Gm can be calculated as in Equation (4):

$${\mathrm{G}}_{\mathrm{c}}\cong {\displaystyle \frac{{\mathrm{G}\mathrm{m}}_1\times {\mathrm{R}}_1\times \frac{2}{\mathrm{\pi }}\times \mathrm{k}\times {\mathrm{R}}_{\mathrm{T}}}{\mathrm{\omega }\times \sqrt{{\mathrm{L}}_1{\mathrm{L}}_2}}}$$

(6)

where R_T represents the output impedance of the GM stage. L₁ and L₂ represent the inductances of the primary and secondary coils of transformer T₁. As expected, the conversion gain decreases with increasing input frequency. The inductors L₁ and L₂ are considered ideal in Equation (6). The layout of transformer T₁ is shown in Figure 12a, and its performance is illustrated in Figure 12b. The coupling coefficient reached 0.69 at 60 GHz.

The tunable gain of the proposed mixer enhances the overall linearity of the receiver. Each time, a voltage equal to the power supply is applied to the gate terminal of transistors M₇–M₉, and the conversion gain drops by roughly 3 dB.

The overall design dissipates 21 mW. The GM stage of the mixer core draws 13.4 mA from the 1.1 volt supply, while the Switch stage draws nearly 0.48 mA. The IF amplifier draws 6.2 mA. The characteristics of the proposed design are summarized in

Table 3. Mixer parameters.

Mixer Characteristics	Values
WM1–M2	1 × 18 u
WM3–M6	1 × 22 u
LM1–M6	40 nm
WM7–M9	1 × 4, 1 × 7, 1 × 11 u
LM7–M9	40 nm
Cn	11 fF
R1	700
Lp, Ls	176,165 pH
RB	8 K
CB	6 pF
VBIASRF	550 mV
VBIASLO	300 mV
WM10–M11,M12	4 × 10, 5 × 22 u
LM12,M13	120 n
WM13,M14	4 × 18, 5 × 25 u
VB1,VB2	550, 500 mV
R2	700 Ω

. Overall, the proposed mixer employs capacitive neutralization in the transconductance stage, a well-known technique used to enhance the transconductance and improve the gain by canceling a portion of the parasitic capacitance. While this method is widely adopted in RF amplifiers, this work combines it with the adaptation of a dual-tapped transformer that inductively couples the GM and the Switch stages. Notably, the transformer’s primary winding is also utilized for gain tuning, adding further flexibility to the design. This transformer enables efficient DC biasing of both stages, while also serving as a compact and robust that enhances gain, minimizes parasitic losses, and broadens bandwidth.

Mixer Post-Layout Simulation Results

The layout of the proposed 60 GHz mixer, designed in a 40 nm TSMC RF CMOS process, is illustrated in Figure 13. The integrated circuit consumes a total area of 0.45 (0.9 × 0.5) ${\mathrm{m}\mathrm{m}}^2$, including the mixer core, the matching networks, the IF amplifier, the RF pads, and the DC pads, which are located at the top of Figure 13. The area is pad limited and would be reduced when the mixer is co-integrated with the Low-Noise Amplifier.

The whole layout shown in Figure 13 was simulated in Cadence’s EMX up to 130 GHz. The output IF signal was arranged to be measured in a GSGSG configuration. The post-layout simulation results indicated that the proposed topology shows a peak conversion gain of 13.5 dB for a 60 GHz LO signal of −6 dBm, as shown in Figure 14a, while the RF frequency is set to 59 GHz. The LO power at which the gain peaks is a typical value of a mm-wave VCO followed by a buffer amplifier for isolation purposes. This gain corresponds to the case when all the switches (b₀–b₃) are turned OFF. As illustrated, each switch activation reduces the conversion gain by nearly 3 dB. Figure 14b depicts the simulated Single Sideband noise figure in all the four gain cases. The minimum simulated noise figure is less than 10.4 dB for an IF bandwidth from 10 MHz to 1.8 GHz. Evidently, as the gain reduces by each switch activation, NF rises considerably.

The simulated return losses at the RF and LO port remained below −10 dB from 55 to 65 GHz, as depicted in Figure 15a. The conversion gain versus the RF input frequency is depicted in Figure 15b.

The simulated IP1dB compression point for all four conversion gain modes is illustrated in Figure 16a. The input compression point varies between −1 dBm when all the switches are turned on (000 code) and −13 dBm in the maximum gain setting (switches OFF, 111 code) for a LO frequency of 60 GHz and an RF frequency of 59 GHz. As illustrated, as the gain reduces by activating each switch transistor, the mixer becomes more linear. Figure 16b represents the conversion gain versus IF frequency when all switches are activated. The simulated IF bandwidth is 1.8 GHz.

Table 4. Comparison with state-of-the-art 60 GHz down-conversion CMOS mixers.

Ref	Hardware	RF (GHz)	CG (dB)	PDC (mW)	IF (GHz)	LO (dBm)	Area (mm2)	NF (dB)	P1 (dBm)	Process
[24]	measured	53–67	8 1	9	3–5	−11	0.4	13 2	−13	22 nm FD-SOI
[25]	measured	56–66	6.5	18	0–1	−4	0.05 3	13.5 4	−18	22 nm FD-SOI
[26]	post- layout	56–64	10.4	6	8–16	2	0.75	11.2 2	−16	65 nm CMOS
[27]	measured	54–65	9.1	16.8	0–2	−5	0.26	12 4	−15	65 nm CMOS
This work	post- layout	57–64	13.5/4	22	0–1.8	−6	0.45	<11 4	−13/−1	40 nm CMOS

¹ voltage conversion gain, non-standard IF output impedance, ² DSB, ³ Core, ⁴ SSB.

displays a comparison of the proposed mixer with state-of-the-art designs operating within the same frequency range. In general, the proposed structure demonstrates large and tunable conversion gain combined with enhanced linearity and improved noise figure compared to similar designs.

2.3. Voltage-Controlled Oscillator (VCO)

The design of LC Voltage-Controlled Oscillators (VCOs) for millimeter-wave frequencies presents several inherent challenges. One of the primary difficulties in operating an LC VCO at fundamental mm-wave frequencies is the substantial decline in the quality factor of varactors and switched-capacitor banks as the frequency increases. To address this issue, the overall tuning range is often divided into smaller frequency bands. However, this approach introduces greater design complexity, requiring meticulous circuit optimization. Another significant challenge in mm-wave VCO design compared to RF VCOs is the pronounced impact of device parasitics and passive interconnect losses. A widely adopted strategy to mitigate these challenges is generating the VCO signal at a lower frequency and subsequently upconverting it to the desired mm-wave frequency [31,32,33]. This up-conversion can be achieved through techniques such as frequency multiplication and harmonic extraction. While these methods can be effective in certain scenarios, they often demand a significant silicon area and introduce unwanted harmonics, which require additional filtering.

The schematic of the proposed Voltage-Controlled Oscillator is illustrated in Figure 17. A fundamental mm-wave VCO operating at 60 GHz was opted for instead of utilizing a frequency multiplier to reduce the silicon area, as while the operating frequency approaches higher mm-wave ranges, the size of the inductor decreases nearly quadratically, saving area [34]. The Class-C topology was selected over the power-hungry Class-B topology. In Class-C operation, proper biasing of the cross-coupled pair is ensured. As a result, the gate voltage is set lower than the drain voltage, keeping the transistors in saturation for a greater portion of time. This configuration allows the Class-C VCO to achieve a phase noise that is typically 2 dB to 4 dB lower than that of a conventional Class-B VCO with equivalent power dissipation [35]. In the proposed design, the biasing of the gates of the cross-coupled pair (M₁,M₂) is accomplished through the center tap of the secondary coil of transformer T₁. The center tap of the primary coil of T₁ biases the drains of the cross-coupled pair to the supply voltage.

The VCO core features a three-bit binary-weighted capacitor bank (C₁–4C₁) alongside three sets of differential switches (B₁–B₃) for fine frequency tuning. Additionally, an analog varactor (Cvar) provides continuous tuning capability. As a result, the total tuning range is divided into eight sub-bands, effectively lowering the fundamental VCO gain (K_VCO) while preserving optimal phase noise characteristics. The generated RF signal is then fed into a high-frequency common-source buffer (M₃, M₄) via an RC decoupling network utilized by the bias resistor R_B and the AC-coupling capacitor Cc_C. At the drains of the common-source transistors, a stacked balun serves as an inductive load, ensuring isolation between the VCO and the subsequent mixer.

The primary factors influencing phase noise performance are described by Leeson’s formula as follows [36]:

$$\mathrm{L}\left(\mathrm{\Delta }\mathrm{f}\right)=10\mathrm{l}\mathrm{o}\mathrm{g}\left\{{\displaystyle \frac{2\mathrm{F}\mathrm{k}\mathrm{T}}{{\mathrm{P}}_{\mathrm{s}}}}\times \left[1+{\left[{\displaystyle \frac{{\mathrm{f}}_0}{2\mathrm{Q}\mathrm{\Delta }\mathrm{f}}}\right]}^2\right]\times \left(1+{\displaystyle \frac{{\mathrm{\Delta }\mathrm{f}}_{\mathrm{C}}}{\mathrm{\Delta }\mathrm{f}}}\right)\right\}$$

(7)

where ${\mathrm{f}}_0$ is the output frequency of the signal source, Q is the tank quality factor, $\mathrm{\Delta }\mathrm{f}$ is the frequency offset from the carrier frequency, Δf_C is the flicker noise corner frequency, F is the noise excess factor, an empirical parameter known for quantifying the active device noise and its up-conversion process, k is Boltzmann’s constant, T is the absolute temperature, and P_s is the oscillation power, which is proportional to the oscillation amplitude. According to Equation (7), enhancing phase noise can only be achieved by modifying the tank’s quality factor and the oscillation power through design adjustments. The quality factor of the tank can be improved by implementing higher-quality factor passive components at the expense of a limited tuning range, while the oscillation peak amplitude is increased at the cost of higher power consumption.

The total quality factor of the VCO tank is given by Equation (8) below:

$${\displaystyle \frac{1}{{\mathrm{Q}}_{\mathrm{t}\mathrm{a}\mathrm{n}\mathrm{k}}}}={\displaystyle \frac{1}{{\mathrm{Q}}_{\mathrm{L}}}}+{\displaystyle \frac{1}{{\mathrm{Q}}_{\mathrm{C}}}}$$

(8)

where Q_L stands for the quality factor of transformer T₁ and Q_C stands for the quality factor of the capacitive elements connected to the tank.

Following the analysis from [37]:

$${\mathrm{Q}}_{\mathrm{c}}=({\mathrm{C}}_{\mathrm{P}\mathrm{a}\mathrm{r}}+{\mathrm{C}}_{\mathrm{V}\mathrm{a}\mathrm{r}}+7{\mathrm{C}}_1)\times {\displaystyle \frac{2}{{\mathsf{\omega }}_0({{\mathrm{C}}_{\mathrm{V}\mathrm{a}\mathrm{r}}}^2{\mathrm{R}}_{\mathrm{V}\mathrm{a}\mathrm{r}}+7{{\mathrm{C}}_1}^2{\mathrm{R}}_{\mathrm{o}\mathrm{n}})}}$$

(9)

where C_var denotes the varactor capacitance, R_var represents its associated series parasitic resistance, C_par is the parasitic capacitance of the tank, including the parasitic capacitance of the cross-coupled pair (M₁,M₂), the series combination of gate capacitance C_GS3,4 of the buffer transistors (M₃,M₄) and the AC-coupling capacitance (C_CC),the parasitic capacitance of the buffer biasing resistors R_B to the substrate, and the parasitic capacitance of the switches (B₁,B₃). Furthermore, Ron /2 corresponds to the series parasitic resistance of the first switch unit (B₁), while C₁ is the unit capacitance of the same switch.

The quality factor described in Equation (9) corresponds to the condition when all capacitors in the capacitor bank are switched ON. When these capacitors are switched OFF, their quality factor significantly improves compared to the active state. The design involves a trade-off in selecting the switch transistor width: increasing the width lowers its ON-resistance but simultaneously introduces additional parasitic capacitance into the tank circuit, which results in a narrower tuning range and decreased frequency stability.

The following provides the formula for the transformer’s quality factor [37]:

$${\mathrm{Q}}_{\mathrm{L}}\cong {\displaystyle \frac{\mathrm{A}\{\mathrm{\omega }{\mathrm{L}}_{\mathrm{D}}-{\mathrm{C}}_{\mathrm{G}}{\mathrm{R}}_{\mathrm{s}\mathrm{d}}{\mathrm{R}}_{\mathrm{s}\mathrm{g}}\}}{\mathrm{A}\left\{{\mathrm{R}}_{\mathrm{s}\mathrm{d}}-{\mathrm{\omega }}^2{\mathrm{L}}_{\mathrm{G}}{\mathrm{C}}_{\mathrm{G}}{+\mathrm{\omega }}^2{\mathrm{L}}_{\mathrm{D}}{\mathrm{C}}_{\mathrm{G}}{\mathrm{R}}_{\mathrm{s}\mathrm{g}}\right\}+{\mathrm{\omega }}^2\mathrm{k}\sqrt{{\mathrm{L}}_{\mathrm{D}}{\mathrm{L}}_{\mathrm{G}}}}}$$

(10)

$$\mathrm{A}={(1-{\mathrm{\omega }}^2{\mathrm{L}}_{\mathrm{G}}{\mathrm{C}}_{\mathrm{G}})}^2$$

R_sd in Equation (10) is the series parasitic resistance of the primary winding (L_D) of transformer T₁. L_G is the secondary winding of transformer T₁, while R_sg represents its series parasitic resistance. C_G is the capacitance seen at the gate of the cross-coupled pair (M₁, M₂).

The layout view of the stacked transformer T₁ is shown in Figure 18a, while a more realistic layout model with the connections to the pads is illustrated in Figure 18b. The transformer is crucial for the phase noise performance of the VCO. The primary winding is connected to the drains of the cross-coupled pair and is a custom one-turn differential structure made of Aluminum at the central tap and a parallel combination of Aluminum and Metal-8 in the feed lines below. The parallel stacking of the two top metals leads to a higher-quality factor, albeit it slightly decreases the Self-Resonant-Frequency (SRF) of the transformer. The trace width is 13.1 μm. The secondary winding is connected at the gates of the cross-coupled pair and is made of Metal-7. It has a trace width of 8.5 μm. There is a trade-off between the quality factor and the loop gain regarding transformer-coupled class-C VCOs. A larger coupling coefficient between the two windings would facilitate the startup condition, albeit it would decrease the quality factor of the tank. The coupling coefficient reaches 0.6 at 60 GHz. The inductance of both windings, alongside their respective quality factors, as simulated in EMX, is illustrated in Figure 19.

The characteristics of the proposed VCO design alongside the parameters of transformer T₁ and the balun at 60 GHz are cited in

Table 5. VCO design parameters.

VCO Characteristics	Values
WM1–M2	1 × 20 u
WM3–M4	1 × 9 u
LM1–M4	40 nm
WSwitch,B1–B3	2 × 6, 2 × 12, 2 × 24 u
LSwitch,B1–B3	40 nm
CC	50 fF
VBIAS	0.6 V
Vbias1	0.84 V
RB	8 K
C1	25.4 fF
CVAR @ Vgs of 0–1.1 V	24–32 fF
T1:LD,LG, QD,QG	105 pH, 168 pH, 27, 16
Balun: LP,LS, QP,QS	140 pH, 125 pH, 15.1,13.4
Cout	24 fF

. The characteristics of the transformers have been extracted using Cadence’s EMX.

The proposed fundamental 60 GHz VCO structure was designed in a 40 nm TSMC RF CMOS process. In Figure 20, the proposed layout is demonstrated. The integrated generator consumes a total area of 0.43 (0.67 × 0.65) ${\mathrm{m}\mathrm{m}}^2$, including the VCO core, the buffer common-source amplifier, the DC pads, and the RF pads, which are located at the top of Figure 20. Overall, this work presents a fundamental 60 GHz class-C Voltage-Controlled Oscillator (VCO), avoiding the need for the frequency multiplication commonly employed in designs that operate at a lower fundamental frequency. By eliminating the doubler stage, the proposed approach reduces the silicon area, suppresses unwanted harmonic generation, and simplifies the signal chain. The VCO includes a carefully optimized transformer and capacitor bank, enabling a wide tuning range that fully covers the required 57–64 GHz band without significant degradation in phase noise. The adoption of class-C operation leads to low power consumption, with the oscillator dissipating less than 7 mW. The low-power operation also minimizes the voltage-dependent intrinsic capacitances, which further enhances the tuning range. As a result, the proposed VCO is well suited for high-performance operation in 60 GHz systems.

VCO Post-Layout Simulation Results

At millimeter-wave frequencies, parasitic inductances and capacitances arising from metal interconnections significantly affect the oscillation frequency, whereas parasitic resistances have a substantial negative impact on phase noise performance. To achieve accurate and reliable simulation outcomes, the VCO core, buffers, and essential metal interconnections were modeled in Cadence EMX as a multiport S parameter network, extending the analysis up to the fourth harmonic.

The post-layout simulation results indicated that the proposed VCO covers a frequency span from 56.60 GHz to 65.52 GHz, corresponding to an approximate tuning range of 14%. This range is segmented into eight distinct oscillation bands. The varactor control voltage varied between 0 and 1.1 V to achieve this coverage. In all following figures, the oscillation bands are arranged in descending frequency order. Figure 21a shows the complete set of frequency bands. The phase noise of the output at 1 MHz frequency offset is illustrated in Figure 21b. The phase noise of the VCO varies from −96.2 dBc/Hz to −92.5 dBc/Hz at 1 MHz offset from the carrier frequency. Figure 21c shows the output power of the VCO core, delivered to a 50-ohm port across all eight frequency bands. Across the whole bandwidth, the proposed structure delivers more than −7 dBm.

The total power dissipation of the proposed oscillator reaches 14.1 mW. The VCO core draws 6 mA from a 1.1 Volt supply, while the buffers consume 7.5 mW.

Table 6. Comparison with state-of-the-art 60 GHz CMOS VCOs.

Reference	Hardware	Type	FREQ (GHz)	PN @ 1 MHz	PDC,VCO (mW)	FTR (%)	Pout (dBm)	Area (mm2)	FOM *	FOMT *	Process
[38]	M 1	Direct	56.7	−103.6 1	9	13.28	−19	0.27	−168.6 1	−171.1 1	40 nm CMOS
[39]	M 1	Direct	61.3	−94.9	8.4	9	−10	0.09 2	−183.4	−180.5	65 nm CMOS
[40]	Post- Layout	2nd Harmonic	60	−93.2	4.2	18.2	−12	0.07 2	−183	−188	65 nm CMOS
[41]	M 1	4th Harmonic	60.85	−99.8	11.7	15.6	-	0.12 2	−184.1	−188	28 nm CMOS
This work	Post- Layout	Direct	61	−94.3	6.6	14	−6.4	0.035 2	−181.5	−184.8	40 nm CMOS

¹ measured/calculated at 10 MHz, ² core area, * FOM=$L\left({\Delta }_f\right)$−20log$\left({\displaystyle \frac{f_0}{{\Delta }_f}}\right)$ + 10log$\left({\displaystyle \frac{P_{dc}}{1mW}}\right)$, * ${\mathrm{F}\mathrm{O}\mathrm{M}}_{\mathrm{T}}$ = $L\left({\Delta }_f\right)$−20log$\left({\displaystyle \frac{f_0}{{\Delta }_f}}{\displaystyle \frac{TR[\%]}{10}}\right)$ + 10log$\left({\displaystyle \frac{P_{dc}}{1mW}}\right).$

presents a comparison between the proposed VCO design and other state-of-the-art implementations operating in the same frequency band. The proposed VCO achieves a Figure of Merit (FOM) of −181.5 dBc/Hz and a Figure of Merit with Tuning (FOM_T) of −184.8 dBc/Hz, both calculated at a 1 MHz offset from the oscillation frequency of 61 GHz, which represents the central operating frequency. In general, the proposed structure demonstrates a larger tuning range than fundamental (direct) VCOs, exhibiting competitive phase noise levels while preserving energy consumption.

3. System Considerations

The active double-balanced mixer and the LNA were coupled together through dual-tapped transformer T₂, as shown in Figure 22. The output matching inductor of the LNA and the input matching balun of the mixer were eliminated. The total silicon area was greatly reduced, as Transformer T₂ is utilized for intermediate matching between the LNA output and the mixer input. Both nodes are high-impedance nodes and do not require matching to 50 ohms. All the other design parameters remained the same and are given in the tables in the previous sections. In addition, the VCO is co-integrated with the mixer via its high-frequency buffer. The transformer serving as a load in the drains of the buffers of the VCO was made as a dual-tapped differential transformer instead of a balun and was coupled to the gates of the switch quad of the mixer by interstage matching between the two stages. The VCO and the LNA were placed at the two edges of the chip for better isolation between the LO and the antenna. The proposed design is illustrated in Figure 22.

The layout of the proposed 60 GHz receiver front end, designed in a 40 nm TSMC RF CMOS process, is illustrated in Figure 23. The integrated circuit consumes a total area of 0.88 (1.6 × 0.56) ${\mathrm{m}\mathrm{m}}^2$, including the LNA, the mixer core, the VCO, the matching network for the RF input, the buffer IF amplifier, the RF pads, and the DC pads, which are located at the top of Figure 23.

The whole layout shown in Figure 23 was simulated in Cadence’s EMX up to 120 GHz. The output signal following the buffer was arranged to be measured in a GSGSG configuration. Figure 24a depicts the conversion gain versus RF frequency for different VCO frequencies. The post-layout simulation results indicated that the proposed topology shows a peak conversion gain of 39.5 dB for a 59.41 GHz LO, which sets the VCO control-bits to 100 and the analog voltage of the varactor at 0 volts, as shown in Figure 24a, while the RF frequency is set to 59 GHz. The improved gain of the whole receiver is improved by removing the output balun of the LNA and the input balun of the mixer, which were designed for matching to 50 ohms. The gain in Figure 24a corresponds to the case where all the switches controlling the gain (b₀–b₃) are turned OFF. Figure 24b depicts the simulated noise figure in all the high- and low-gain bands versus RF frequency when the VCO is set at 59.41 GHz (code 100, V_c = 0). At maximum gain, the simulated Single Sideband (SSB) noise figure is less than 7.9 dB.

The return loss at the RF port remained below −10 dB from 54 to 65 GHz, as depicted in Figure 25a. The connection of the LNA to the mixer slightly altered the input-return loss due to the change of the load in the second amplification stage of the LNA. The simulated return loss at the IF port is illustrated in Figure 25b.

The IP1dB compression point for all four conversion gain modes is illustrated in Figure 26a. The input compression point varies between −37.1 dBm when providing maximum gain and −27.5 dBm when providing the minimum conversion gain, for a LO frequency of 59.41 GHz and an RF frequency of 59 GHz. Figure 26b represents the output differential signal for an RF input signal of −40 dBm at 58 GHz, where the VCO is set at digital code of ‘100’ and V_c = 0, which corresponds to 59.41 GHz.

The total power consumption of the proposed receiver reaches 56 mW from a 1.1 Volt supply. As illustrated in Figure 27, the most power-hungry components are the LNA and the down-conversion mixer. The high-power consumption of the LNA mixer chain is expected due to the high-gain and low-noise figure achieved. On the contrary, the VCO power dissipation counts only for 12% of the total power consumption due to the class-C configuration.

Table 7. Comparison with state-of-the-art 60 GHz CMOS receiver front ends.

Ref	Hardware	Components	RF (GHz)	CG (dB)	PDC (mW)	IF (GHz)	Area (mm2)	NF (dB)	P1 (dBm)	Process
[42]	M 1	LNA, mixer, VCO	56–61.5	30	43	0–1.5	0.55	9.2 2	−36	65 nm
[43]	M 1	LNA, mixer, VCO,	57–63	11.8	76.8	2	0.86	10.4 2	−15.8	130 nm
[44]	M 1	LNA, mixer, External LO	55.6–60	26.3	53.5	0.3–1.9	1.29	7.5–10.1 3	−31.5	65 nm
[7]	M 1	LNA, mixer, External LO	57–64	17.2–19.3	39.6	0.001	0.2 4	7.5–8.2 2,5	>−13	28 nm
[45] 6	M 1	LNA, Mixers, VCO	56–69	35.5	75	0–0.2	2.4	5.6–6.5 2	−21	65 nm
This work	Post- Layout	LNA, Mixer, VCO	57–64	39/29	56	0–1.8	0.88	7.5–9.2 3	−37.1/−27.5	40 nm CMOS

¹ Measured, ² DSB, ³ SSB,⁴ Without pads, ⁵ Measured at 10 MHz IF frequency, ⁶ Heterodyne receiver.

presents a comparative analysis of the proposed receiver front end against other state-of-the-art designs of similar complexity. The comparison underscores two major advantages of the proposed implementation: its high conversion gain and its compact footprint. The achieved conversion gain of 39 dB is comparable to the upper range of the reported values in the literature. Even in the lower gain configuration of 29 dB, the design exhibits improved linearity compared to other receivers operating in the 60 GHz frequency band. The simulated noise figure also reflects competitive noise performance. In terms of bandwidth, the proposed front end achieves an impressive 7 GHz coverage within the 60 GHz unlicensed band, surpassing many existing designs that span a portion of this spectrum. When considering the trade-off between gain and linearity, the proposed receiver front end stands out as a highly promising solution for next-generation millimeter-wave applications.

4. Discussion

The proposed receiver front end, integrating a Low-Noise Amplifier (LNA), a down-conversion mixer, a Voltage-Controlled-Oscillator, and an IF buffer to drive for measurement purposes, exhibits not only high but also tunable conversion gain, ranging from 29 to 39 dBm. This tunability of the conversion gain enhances flexibility in terms of linearity, as reflected in the input-referred compression point, which ranges from −27.5 to −37 dBm. The overall simulated noise figure remains below 9.2 dB for an IF bandwidth spanning from 0 to 1.8 GHz, while total power consumption stays under 60 mW.

To further improve linearity, the Low-Noise Amplifier could incorporate variable gain control, particularly in the second stage, allowing for enhanced performance regarding the input compression point. In addition to that, the bandwidth of the LNA could be extended to cover the full range from 57 to 66 GHz, at the cost of reduced gain. Additionally, designing a dedicated baseband circuit incorporating variable gain, while also including DC-offset cancelation structures, to remedy the DC leakage problem which manifests in direct-conversion receivers, would provide a more comprehensive evaluation of the receiver’s capabilities.

Regarding the fundamental class-C Voltage-Controlled Oscillator (VCO), it exhibits a wide tuning range and competitive phase noise levels while maintaining energy efficiency. These characteristics make it well suited for integration into the proposed receiver front end, ensuring adequate output power for peak conversion gain, as confirmed by simulations. One potential enhancement for the VCO would be the implementation of a startup circuit to mitigate startup failures, a common challenge in Class-C VCOs.

The design of ultra-low-power 60-GHz receivers must account for the power consumption of the phase-locked loop (PLL), which, in addition to the Voltage-Controlled Oscillator (VCO), also includes critical components such as the frequency divider, charge pump, loop filter, and phase detector. This falls outside the scope of the current paper and will be explored in subsequent research.

A key direction for future work is the physical implementation of the proposed chip to evaluate its performance under real conditions. While the post-layout simulation results obtained from EMX provide a useful baseline, the actual behavior of the receiver front end in silicon may differ due to a range of layout, parasitic, and process-related effects. For example, the gain of the LNA and the down-conversion mixer may degrade because of increased interconnect losses, which become more pronounced at 60 GHz. The input and output matching networks that performed well in simulation may shift in frequency, leading to reduced gain and a higher noise figure. Process variations—such as shifts in threshold voltage or gate length—can alter device biasing and transconductance, affecting gain, linearity, and impedance matching. The VCO is particularly sensitive to post-fabrication effects. Deviations in intrinsic capacitances or the varactor tuning range can shift the oscillation frequency away from its target, while increased substrate noise coupling and reduced resonator Q may worsen phase noise. Similarly, the mixer’s conversion may drop if parasitic capacitances alter switching behavior or if the LO drive is weaker than expected. These factors underscore the importance of silicon validation to fully characterize performance under practical conditions and to identify any discrepancies from the modeled behavior.

5. Conclusions

This paper introduces the design and implementation of a low-power, high-conversion gain receiver front end tailored for the unlicensed 60 GHz band, using 40 nm CMOS technology. The proposed architecture, which incorporates a Low-Noise Amplifier, a down-conversion mixer, a fundamental Voltage-Control-Oscillator, and IF buffers to drive 50-ohm loads achieves an RF bandwidth spanning 57 to 64 GHz, delivering a high conversion gain between 29 and 39 dB, with a noise figure below 9.2 dB for an IF bandwidth of 0–1.8 GHz, while consuming only 56 mW of power. A free-running 60 GHz fundamental Voltage-Controlled Oscillator (VCO) has been designed and co-integrated with the front end, indicating in post-layout simulations proper functionality. The receiver front end demonstrates state-of-the-art performance, highlighting its potential for next-generation wireless communication systems.