Digital Predictive Peak Current Control Strategy for the High-Order Superbuck Converter

Abstract

This paper proposes a digital predictive peak current control (PPCC) strategy for superbuck converters. The proposed strategy incorporates a current predictor to calculate the output current and a peak current controller to calculate the required duty ratio for the next switching cycle. The duty ratio is precalculated ahead of a switching cycle, which creates a switching cycle for signal samplings and digital calculations. At the end of the next switching cycle, the output current peak value is regulated to match the reference value. The proposed strategy regulates the output current peak value to the reference value within two switching cycles. This increases the current loop bandwidth to π/T rad/s, which optimizes the transient performance. Moreover, a new damping parameter design method based on the damping ratio is given. Furthermore, a simplified version is proposed to facilitate digital realization. This version directly calculates the required duty ratio, which significantly reduces digital calculations. Finally, the experimental results demonstrate the effectiveness of the proposed control strategy in improving the transient performance of the superbuck converter.

1. Introduction

As a Cuk-derived topology, the superbuck converter is widely used in photovoltaic applications owing to its continuous input and output currents [1,2,3]. Its steady-state operation is similar to that of a conventional buck converter, both of which step down the voltage with a duty cycle ratio. However, the dynamic behavior is quite different. While a conventional buck converter has two poles in its small-signal model, the transfer function of a superbuck converter has four poles and two RHP (right half-plane) zeros. This degrades the dynamic performance and greatly complicates the converter and feedback controller designs.

To improve the dynamic performance and maintain the stability of the high-order superbuck converter, linear control strategies are proposed due to their simplicity. In [4], a double closed-loop control system with a voltage outer loop and am input current inner loop is designed, but its dynamic performance is relatively poor due to the RHP zeros. Feedforward control is proposed in [5] to eliminate audio susceptibility at certain frequencies, but the dynamic performance is not studied. To improve the dynamic performance of switched-mode power converters, nonlinear control strategies are proposed. Considering RHP zeros, a fast response controller for boost converters using sliding mode control (SMC) is proposed in [6]. This can also be applied to superbuck converters [7]. However, the PWM-based SMC needs four control variables, which complicates the sampling and controller designs. This issue is universal when using PWM-based SMC to control high-order converters. Furthermore, a simplified hysteresis sliding mode controller with a novel sliding surface is proposed to reduce the required control variables in [8]. Model predictive control (MPC) is another typical nonlinear control. In [9,10], digital predictive current mode (PCM) control is proposed and analyzed, which shows good dynamic performance. A more practical control strategy is hybrid linear–nonlinear control [11], which is usually composed of a linear control outer loop and a nonlinear control inner loop. This approach can make full use of the simple design of linear control and the excellent performance of nonlinear control.

Digital Current Mode Control

While many control strategies are proposed for superbuck converters, the dynamic performance is mainly limited by the inherent RHP zeros (inducing a nonminimum phase system). The RHP zeros are very harmful to stability, since they increase the magnitude–frequency response while decreasing the phase–frequency response. The conventional method is to set two inductors to satisfy a certain relationship, but it is unsuitable when the duty ratio is large [12]. At present, a practical strategy to eliminate RHP zeros is adding a damping network to the main converter [13], especially in the case of a large duty ratio. With an appropriate damping network, the RHP zeros can be tuned as left half-plane zeros, which are beneficial to closed-loop stability. However, the existing research does not have a quantitative representation for the design of damping network parameters.

This paper proposes a digital predictive peak current control (PPCC) strategy for the high-order superbuck converter. The proposed strategy incorporates a current predictor to calculate the output current and a peak current controller to calculate the required duty ratio in the next switching cycle. The duty ratio is precalculated one switching cycle ahead, which creates a switching cycle for signal samplings and digital calculations. At the end of the next switching cycle, the output current peak value is regulated as the reference value. The proposed strategy regulates the output current peak value to the reference value in two switching cycles, which increases the current loop bandwidth to π/T rad/s and optimizes the transient performance. Furthermore, a simplified version is proposed to facilitate digital realization. The simplified version directly calculates the required duty ratio, which significantly reduces digital calculations. Finally, the experimental results prove the effectiveness of the proposed control strategy in improving the transient performance of the high-order superbuck converter.

The rest of this paper is organized as follows. In Section 2, the small-signal models of the superbuck converter with and without a damping network are presented. In Section 3, the PPCC strategy is proposed to improve the dynamic performance of the superbuck converter, and a damping network parameter design method along with a simplified version are provided. In Section 4, root locus analysis is conducted to investigate possible oscillation frequency and to illustrate the effects of the damping network. Finally, experimental results are given in Section 5 to verify the effectiveness of the proposed strategy. A brief conclusion is given in Section 6.

2. Superbuck Converter and the Small-Signal Model

2.1. Large-Signal Behavior of Superbuck Converter Without Damping Network

A conventional superbuck converter scheme without a damping network is given in Figure 1. Compared to a buck converter, it achieves an identical voltage conversion ratio while having an additional inductor and an additional capacitor. These added components can provide continuous input and output currents, making it suitable for photovoltaic applications.

Based on voltage-second balancing of L₁ and L₂, the voltage across C₁ is v_C1 ≈ v_in at steady state. Therefore, when the main switch S₁ is on, the diode is reverse-biased by v_C1. Furthermore, the voltage across L₁ is v_in − v_out, while the voltage across L₂ is v_C1 − v_out ≈ v_in − v_out. Meanwhile, since C₁ is nearly short-circuited at the switching frequency, both i_L1 and i_L2 flow through S1. When the main switch S1 is turned off, both i_L1 and i_L2 flow through the diode. The voltage across L₁ becomes v_in − v_C1 − v_out ≈ −v_out, while the voltage across L₂ is −v_out.

With voltage-second balancing of the inductors and charge balancing of the capacitors, the steady state operation yields the following:

$$\left\{\begin{array}{l}{v}_{in}-v_{out}-v_{C1}(1-D)=0\\ -v_{out}+v_{C1}D=0\\ -i_{L2}D+i_{L1}(1-D)=0\\ i_{L1}+i_{L2}-{\displaystyle \frac{v_{out}}{R}}=0\end{array}\right.$$

(1)

which further derives the following:

$$\left\{\begin{array}{l}{v}_{out}=D{v}_{in}\\ v_{C1}=v_{in}\\ i_{L1}={\displaystyle \frac{D{v}_{out}}{R}}\\ i_{L2}={\displaystyle \frac{(1-D)v_{out}}{R}}\end{array}\right.$$

(2)

As indicated in (2), the output voltage at steady state is identical to that of a conventional buck converter. However, the dynamic behavior is much more complex. To investigate the dynamic performance and optimize control, small-signal modeling and feedback compensation design are provided below.

2.2. Large-Signal Behavior with Damping Network

To avoid RHP zeros in a conventional superbuck converter, as shown in Figure 2, a damping network consisting of a serial R_d − C_d connection is placed in parallel at both ends of C₁.

With voltage-second balancing of inductors and charge balancing of capacitors, the steady state operation yields the following:

$$\left\{\begin{array}{l}{v}_{in}-v_{out}-v_{C1}(1-D)=0\\ -v_{out}+v_{C1}D=0\\ -i_{L2}D+i_{L1}(1-D)-{\displaystyle \frac{v_{C1}-v_{Cd}}{R_d}}=0\\ i_{L1}+i_{L2}-{\displaystyle \frac{v_{out}}{R}}=0\\ {\displaystyle \frac{v_{C1}-v_{Cd}}{R_d}}=0\end{array}\right.$$

(3)

which further derives the following:

$$\left\{\begin{array}{l}{v}_{out}=D{v}_{in}\\ v_{C1}=v_{in}\\ i_{L1}={\displaystyle \frac{D{v}_{out}}{R}}\\ i_{L2}={\displaystyle \frac{(1-D)v_{out}}{R}}\\ v_{Cd}=v_{C1}\end{array}\right.$$

(4)

Comparing Equations (2) and (4), it is obvious that the damping network has no influence on the large signal behavior. However, the small-signal model is quite different, which will be discussed in the following subsections.

2.3. Small-Signal Model Without Damping Network

For a conventional superbuck converter without a damping network, there are four delay items in the system, thus inducing a fourth-order small-signal model. Based on the total differential equation method, a small-signal model of a basic superbuck converter is derived below. With consideration of the state variables i_L1, i_L2, v_C1, and v_out, the state-averaged Laplace equations are given by the following:

$$\left\{\begin{array}{l}s{i}_{L1}={\displaystyle \frac{1}{L_1}}[v_{in}-v_{out}-v_{C1}(1-D)]\\ s{i}_{L2}={\displaystyle \frac{1}{L_2}}[-v_{out}+v_{C1}D]\\ s{v}_{C1}={\displaystyle \frac{1}{C_1}}[-i_{L2}D+i_{L1}(1-D)]\\ s{v}_{out}={\displaystyle \frac{1}{C_2}}[i_{L1}+i_{L2}-{\displaystyle \frac{v_{out}}{R}}]\end{array}\right.$$

(5)

Equation (5) reveals large-signal relationships among the state variables. Furthermore, the small-signal relationships are derived from the total differential of Equation (5), as shown below:

$$\left\{\begin{array}{l}s{\widehat{i}}_{L1}={\displaystyle \frac{1}{L_1}}[{\widehat{v}}_{in}-{\widehat{v}}_{out}-{\widehat{v}}_{C1}(1-D)+v_{C1}\widehat{D}]\\ s{\widehat{i}}_{L2}={\displaystyle \frac{1}{L_2}}[-{\widehat{v}}_{out}+{\widehat{v}}_{C1}D+v_{C1}\widehat{D}]\\ s{\widehat{v}}_{C1}={\displaystyle \frac{1}{C_1}}[-{\widehat{i}}_{L2}D+{\widehat{i}}_{L1}(1-D)-i_{L2}\widehat{D}-i_{L1}\widehat{D}]\\ s{\widehat{v}}_{out}={\displaystyle \frac{1}{C_2}}[{\widehat{i}}_{L1}+{\widehat{i}}_{L2}-{\displaystyle \frac{{\widehat{v}}_{out}}{R}}+{\displaystyle \frac{v_{out}}{R^2}}\widehat{R}]\end{array}\right.$$

(6)

This equation has seven small-signal variables, i.e., $<{\widehat{i}}_{L1}, {\widehat{i}}_{L2}, {\widehat{v}}_{C1}, {\widehat{v}}_{out}, {\widehat{v}}_{in}, \widehat{D}, \widehat{R}>$. If eliminating $<{\widehat{i}}_{L1}, {\widehat{i}}_{L2}, {\widehat{v}}_{C1}>$, the output voltage can be derived as follows:

$${\widehat{v}}_{out}=G_{vd}(s)\widehat{D}+G_{vl}(s)\widehat{R}+G_{vg}(s){\widehat{v}}_{in}$$

(7)

where G_vd(s), G_vl(s), and G_vg(s) are the transfer functions from D, R, and v_in to v_out, respectively. They are given by the following:

$$\left\{\begin{array}{l}{G}_{vd}(s)={\displaystyle \frac{{\widehat{v}}_{out}}{\widehat{D}}}=v_{in}{\displaystyle \frac{s^2[L_1+L_2]C_1-s[D^2{L}_1-D(1-D)L_2]/R+1}{s^4{L}_1{L}_2{C}_1{C}_2+s^3{L}_1{L}_2{C}_1/R+s^2[C_1{L}_1+D^2{L}_1{C}_2+C_1{L}_2+{(1-D)}^2{L}_2{C}_2]+s[D^2{L}_1+{(1-D)}^2{L}_2]/R+1}}\\ G_{vl}(s)={\displaystyle \frac{{\widehat{v}}_{out}}{\widehat{R}}}={\displaystyle \frac{v_{out}}{R^2}}{\displaystyle \frac{s{L}_1{L}_2[s^2{C}_1+D^2/L_2+{(1-D)}^2/L_1]}{s^4{L}_1{L}_2{C}_1{C}_2+s^3{L}_1{L}_2{C}_1/R+s^2[C_1{L}_1+D^2{L}_1{C}_2+C_1{L}_2+{(1-D)}^2{L}_2{C}_2]+s[D^2{L}_1+{(1-D)}^2{L}_2]/R+1}}\\ G_{vg}(s)={\displaystyle \frac{{\widehat{v}}_{out}}{{\widehat{v}}_{in}}}={\displaystyle \frac{s^2{L}_2{C}_1+D}{s^4{L}_1{L}_2{C}_1{C}_2+s^3{L}_1{L}_2{C}_1/R+s^2[C_1{L}_1+D^2{L}_1{C}_2+C_1{L}_2+{(1-D)}^2{L}_2{C}_2]+s[D^2{L}_1+{(1-D)}^2{L}_2]/R+1}}\end{array}\right.$$

(8)

The transfer functions are fourth-order, which complicates the feedback compensator design. Moreover, when $D^2{L}_1-D(1-D)L_2>0$, RHP zeros emerge in G_vd(s), which further degrades stability.

2.4. Small-Signal Model with Damping Network

As aforementioned, a superbuck converter with a damping network has a five-order small-signal model. Considering the state variables iL₁, iL2, v_C1, v_Cd, and v_out, the state-averaged Laplace equations are given by the following:

$$\left\{\begin{array}{l}s{i}_{L1}={\displaystyle \frac{1}{L_1}}[v_{in}-v_{out}-v_{C1}(1-D)]\\ s{i}_{L2}={\displaystyle \frac{1}{L_2}}[-v_{out}+v_{C1}D]\\ s{v}_{C1}={\displaystyle \frac{1}{C_1}}[-i_{L2}D+i_{L1}(1-D)-{\displaystyle \frac{v_{C1}-v_{Cd}}{R_d}}]\\ s{v}_{out}={\displaystyle \frac{1}{C_2}}[i_{L1}+i_{L2}-{\displaystyle \frac{v_{out}}{R}}]\\ s{v}_{Cd}={\displaystyle \frac{v_{C1}-v_{Cd}}{R_d{C}_d}}\end{array}\right.$$

(9)

Equation (9) reveals large-signal relationships among the state variables. Furthermore, the small-signal relationships are derived from the total differential equation of (9), as shown below:

$$\left\{\begin{array}{l}s{\widehat{i}}_{L1}={\displaystyle \frac{1}{L_1}}[{\widehat{v}}_{in}-{\widehat{v}}_{out}-{\widehat{v}}_{C1}(1-D)+v_{C1}\widehat{D}]\\ s{\widehat{i}}_{L2}={\displaystyle \frac{1}{L_2}}[-{\widehat{v}}_{out}+{\widehat{v}}_{C1}D+v_{C1}\widehat{D}]\\ s{\widehat{v}}_{C1}={\displaystyle \frac{1}{C_1}}[-{\widehat{i}}_{L2}D+{\widehat{i}}_{L1}(1-D)-i_{L2}\widehat{D}-i_{L1}\widehat{D}-{\displaystyle \frac{{\widehat{v}}_{C1}-{\widehat{v}}_{Cd}}{R_d}}]\\ s{\widehat{v}}_{out}={\displaystyle \frac{1}{C_2}}[{\widehat{i}}_{L1}+{\widehat{i}}_{L2}-{\displaystyle \frac{{\widehat{v}}_{out}}{R}}+{\displaystyle \frac{v_{out}}{R^2}}\widehat{R}]\\ s{\widehat{v}}_{Cd}={\displaystyle \frac{{\widehat{v}}_{C1}-{\widehat{v}}_{Cd}}{R_d{C}_d}}\end{array}\right.$$

(10)

This equation has eight small-signal variables, including $<{\widehat{i}}_{L1}, {\widehat{i}}_{L2}, {\widehat{v}}_{C1}, {\widehat{v}}_{Cd},{\widehat{v}}_{out}, {\widehat{v}}_{in}, \widehat{D}, \widehat{R}>$. If eliminating $<{\widehat{i}}_{L1}, {\widehat{i}}_{L2}, {\widehat{v}}_{C1}, {\widehat{v}}_{Cd}>$, and considering that $i_{out}=i_{L1}+i_{L2}={\displaystyle \frac{V_{out}}{R}}={\displaystyle \frac{V_{in}D}{R}}={\displaystyle \frac{V_{C1}D}{R}}$, the output voltage can also be expressed as Equation (7).

Substituting Equation (9) into (10), the transfer function G_vd(s) can be expressed as follows:

$$G_{vd}(s)={\displaystyle \frac{{\widehat{v}}_{out}}{\widehat{D}}}=v_{in}{\displaystyle \frac{a_3{s}^3+a_2{s}^2+a_{1}s+a_0}{b_5{s}^5+b_4{s}^4+b_3{s}^3+b_2{s}^2+b_{1}s+b_0}}$$

(11)

where the coefficients are as follows:

$$\left\{\begin{array}{l}{a}_3=C_1{C}_{d}R{R}_d(L_1+L_2)\\ a_2=\left(C_1+C_d\right)\left(L_1+L_2\right)R+D{C}_d{R}_d\left(L_2-D{L}_1-D{L}_2\right)\\ a_1=D\left(L_2-D{L}_1-D{L}_2\right)+C_{d}R{R}_d\\ a_0=R\\ b_5=C_1{C}_2{C}_d{L}_1{L}_{2}R{R}_d\\ b_4=L_1{L}_2\left(\left(C_1+C_d\right)C_{2}R+C_1{C}_d{R}_d\right)\\ b_3=\left(C_1+C_d\right)L_1{L}_2+C_{d}R{R}_d\left(C_1(L_1+L_2)+C_2(L_2{(1-D)}^2+L_1{D}^2)\right)\\ b_2=R\left(C_1+C_d\right)\left(L_1+L_2\right)+\left(C_1+C_d\right)\left(L_1+L_2\right)\left(L_2{\left(1-D\right)}^2+L_1{D}^2\right)\\ b_1=L_2{\left(1-D\right)}^2+L_1{D}^2+C_{d}R{R}_d\\ b_0=R\end{array}\right.$$

(12)

The other transfer functions G_vl(s) and G_vg(s) can be expressed as follows:

$$\left\{\begin{array}{l}{G}_{vl}(s)={\displaystyle \frac{{\widehat{v}}_{out}}{\widehat{R}}}={\displaystyle \frac{v_{out}}{R}}{\displaystyle \frac{s^4{C}_1{C}_d{L}_1{L}_2{R}_d+s^3{L}_1{L}_2(C_1+C_d)+s(s{C}_d{R}_d+1)(L_2{(1-D)}^2+L_1{D}^2)}{b_5{s}^5+b_4{s}^4+b_3{s}^3+b_2{s}^2+b_{1}s+b_0}}\\ G_{vg}(s)={\displaystyle \frac{{\widehat{v}}_{out}}{{\widehat{v}}_{in}}}=R{\displaystyle \frac{s^3{C}_1{C}_d{L}_2{R}_d+s^2{L}_2(C_1+C_d)+s{C}_{d}D{R}_d+D}{b_5{s}^5+b_4{s}^4+b_3{s}^3+b_2{s}^2+b_{1}s+b_0}}\end{array}\right.$$

(13)

2.5. Closed-Loop Model with Dual-Loop PI Feedback Control

The disturbance component is dependent on the superbuck power stage, feedback compensation, and real-time operating conditions. Since feedback compensation and operating conditions are undetermined issues for a universal design, the following analyses will focus on the potential oscillation frequency with typical operations (i.e., resistive load, voltage source, moderate compensation).

With basic proportional–integral (PI) compensation as the feedback control, a closed-loop small-signal model of the system is given in Figure 3. Hv(s) represents the outer voltage loop PI compensator, which uses the error between the reference voltage vref and output voltage v_out to generate the current reference value Iref. Additionally, Hi(s) represents the inner current loop PI compensator, which uses the error between Iref and the output current peak value Iout to generate the required duty ratio D. Considering the sampling delay in the actual controller, a zero-order hold (ZOH) is added in the closed-loop model.

The induced zero in the PI compensator can compensate for the dominant pole in G_vd(s), while the pole at the origin provides infinite DC gain, eliminating the steady-state error. To ensure adequate phase margin, the crossover frequency must be located much lower than the first non-dominant pole. However, the crossover frequency cannot be so low as to harm the dynamic performance. A moderate design is to locate it at 1/3~1/2 of the non-dominant pole, so that the phase margin is within 63~72 degrees.

However, in a superbuck converter, the dominant pole is usually conjugated, i.e., two conjugated poles are equally dominant, as shown in Figure 4. When compensating for conjugated poles, a moderate design is to place the zero near the conjugated poles, while limiting the crossover frequency to be lower than them. Even so, oscillations can be induced, and the frequency is determined by the crossover frequency and the damping factor of the conjugated poles.

Furthermore, a basic superbuck converter can induce RHP zeros, which are usually located higher than the dominant poles. The RHP zeros will increase the magnitude response while decreasing the phase response. Therefore, they will degrade stability and induce oscillations at the corresponding frequency.

In conclusion, with conventional PI compensation to control the superbuck converter, potential oscillation can occur at a frequency near the conjugated dominant poles and the RHP zeros. The root locus simulations are given in Section 4.

3. Predictive Peak Current Control for High-Order Superbuck Converter

The proposed digital PPCC strategy employs a PI compensator as the outer loop and a predictive peak current controller as the inner loop, as shown in Figure 5. The inner loop digital predictive peak current controller consists of a current predictor and a peak current controller. The current predictor calculates the predicted output current ipre, and the peak current controller calculates the required duty ratio used in the next switching cycle.

3.1. Predictive Peak Current Control Algorithm

The process of digital predictive peak current control is shown in Figure 6, where iref represents the reference current provided by the outer-loop PI compensator, iout(k) is the sampled peak current at the beginning of the [k]th period, and ipre(k) is the predicted current for the [k]th period as calculated by the current predictor, which will be the peak current target at the next period and equal to iref at steady state. In Figure 6, a perturbation Δiout is introduced before the [k]th period, and the perturbation disappears at the end of the next period. For predictive peak current control, the required duty cycle of the next period is precalculated based on the iout(k) along with the input and output voltage.

With iL₁ and iL2 defined in (5) and (9), the output current is given by the following:

$$i_{out}=i_{L1}+i_{L2}={\displaystyle \frac{1}{s{L}_1}}[v_{in}-v_{out}-v_{C1}(1-D)]+{\displaystyle \frac{1}{s{L}_2}}[-v_{out}+v_{C1}D]$$

(14)

Therefore, the variation of the output current in one switching cycle is as follows:

$$\begin{array}{l}\mathrm{\Delta }{i}_{out}={\displaystyle \frac{T}{L_1}}[v_{in}-v_{out}-v_{C1}(1-D)]+{\displaystyle \frac{T}{L_2}}[-v_{out}+v_{C1}D]\\ =T{\displaystyle \frac{v_{in}-v_{out}}{L_1}}-T{\displaystyle \frac{v_{out}}{L_2}}+v_{C1}T({\displaystyle \frac{D-1}{L_1}}+{\displaystyle \frac{D}{L_2}})\end{array}$$

(15)

Assuming the output current changes by ∆i_out = i_ref − i_out, the required duty ratio is given by the following:

$$D={\displaystyle \frac{1}{v_{C1}T}}[{\displaystyle \frac{L_1{L}_2}{L_1+L_2}}(i_{ref}-i_{out})-{\displaystyle \frac{L_2}{L_1+L_2}}{v}_{in}T+v_{out}T]+{\displaystyle \frac{L_2}{L_1+L_2}}$$

(16)

With (16), the output current can be regulated to iref in one switching cycle. This increases the current loop bandwidth and improves the dynamic response of the output voltage. However, considering sampling and calculation delays, the required duty ratio is hard to calculate on-line. To address this issue, the required duty ratio is predicted ahead of the switching cycle, which provides a time window for digital sampling and calculations.

Introducing the switching cycle in the calculations, the variation of iout in the [k + 1]th switching cycles is given by the following:

$$\mathrm{\Delta }{i}_{out}[k+1]=T{\displaystyle \frac{v_{in}[k+1]-v_{out}[k+1]}{L_1}}-T{\displaystyle \frac{v_{out}[k+1]}{L_2}}+v_{C1}[k+1]T({\displaystyle \frac{D[k+1]-1}{L_1}}+{\displaystyle \frac{D[k+1]}{L_2}})$$

(17)

Furthermore, assuming that iout is regulated to i_ref[k] at the end of the [k + 1]th switching cycle, then Δi_out[k + 1] is adjusted as follows:

$$\mathrm{\Delta }{i}_{out}[k+1]=i_{ref}\left[k\right]-i_{out}[k+1]=i_{out}\left[k+2\right]-i_{out}[k+1]$$

(18)

Moreover, variations of <v_in, v_out, v_C1> are usually slow owing to the filtering capacitors. Therefore, directly using the sampling values for the predictive calculation is effective. Substituting (18) and v_in[k + 1] ≈ v_in[k], v_out[k + 1] ≈ v_out[k], v_C1[k + 1] ≈ v_C1[k] into (17) gives the following:

$$i_{out}\left[k+2\right]-i_{out}[k+1]\approx T{\displaystyle \frac{v_{in}[k]-v_{out}[k]}{L_1}}-T{\displaystyle \frac{v_{out}[k]}{L_2}}+v_{C1}[k]T({\displaystyle \frac{D[k+1]-1}{L_1}}+{\displaystyle \frac{D[k+1]}{L_2}})$$

(19)

In (19), the output current can change very fast in a switching cycle, and thus should be predicted ahead of time for digital calculations. When the output current of the [k]th switching cycle is sampled, its value for the next cycle is predicted by the following:

$$i_{out}[k+1]=i_{out}[k]+T{\displaystyle \frac{v_{in}[k]-v_{out}[k]}{L_1}}-T{\displaystyle \frac{v_{out}[k]}{L_2}}+v_{C1}[k]T({\displaystyle \frac{D[k]-1}{L_1}}+{\displaystyle \frac{D[k]}{L_2}})$$

(20)

Substituting (19) and (20) gives the following:

$$\begin{array}{l}D[k+1]={\displaystyle \frac{1}{v_{C1}[k]T}}({\displaystyle \frac{L_1{L}_2}{L_1+L_2}}(i_{ref}[k]-i_{out}[k+1])-{\displaystyle \frac{L_2}{L_1+L_2}}{v}_{in}[k]T+v_{out}[k]T)+{\displaystyle \frac{L_2}{L_1+L_2}}\\ ={\displaystyle \frac{1}{v_{C1}[k]}}\left[{\displaystyle \frac{L_1{L}_2}{L_1+L_2}}{\displaystyle \frac{(i_{ref}[k]-i_{out}[k])}{T}}-{\displaystyle \frac{2L_2}{L_1+L_2}}{v}_{in}[k]+2v_{out}[k]\right]+{\displaystyle \frac{2L_2}{L_1+L_2}}-D[k]\end{array}$$

(21)

3.2. Closed-Loop Modeling for the Digital PPCC System

In order to verify the stability under the proposed digital PPCC strategy, based on Equation (21), closed-loop small-signal modeling for the converter and controller is provided below.

$$D(z+1)={\displaystyle \frac{1}{v_{C1}}}[{\displaystyle \frac{L_1{L}_2}{L_1+L_2}}{\displaystyle \frac{(i_{ref}-i_{out})}{T}}-{\displaystyle \frac{2L_2}{L_1+L_2}}{v}_{in}+2v_{out}]+{\displaystyle \frac{2L_2}{L_1+L_2}}$$

(22)

Letting D_z = D results in the following:

$$D={\displaystyle \frac{1}{v_{C1}}}[{\displaystyle \frac{L_1{L}_2}{L_1+L_2}}{\displaystyle \frac{(i_{ref}-i_{out})}{2T}}-{\displaystyle \frac{L_2}{L_1+L_2}}{v}_{in}+v_{out}]+{\displaystyle \frac{L_2}{L_1+L_2}}$$

(23)

Differentiating D_z yields the following:

$$\widehat{D}={\displaystyle \frac{1}{v_{C1}}}[{\displaystyle \frac{L_1{L}_2}{2(L_1+L_2)T}}({\widehat{i}}_{ref}-{\widehat{i}}_{out})-{\displaystyle \frac{L_2}{L_1+L_2}}{\widehat{v}}_{in}+{\widehat{v}}_{out}]-{\displaystyle \frac{\frac{L_1{L}_2}{L_1+L_2}\frac{(i_{ref}-i_{out})}{2T}-\frac{L_2}{L_1+L_2}{v}_{in}+v_{out}}{{v_{C1}}^2}}{\widehat{v}}_{C1}$$

(24)

Substituting (24) into the steady-state expression (10), the following can be obtained:

$$\left\{\begin{array}{l}{\widehat{v}}_{out}={\displaystyle \frac{1}{1+2sT}}{\displaystyle \frac{R}{(sR{C}_2+1)}}{\widehat{i}}_{ref}+{\displaystyle \frac{v_{out}}{R}}{\displaystyle \frac{1}{(sR{C}_2+1)}}\widehat{R}\\ {\widehat{v}}_{C1}={\displaystyle \frac{(R+sD{L}_2){\widehat{v}}_{in}+\frac{s(aR-sD{L}_{eq}(L_1+L_2))}{1+2sT}{\widehat{i}}_{ref}-sD{\widehat{v}}_{out}}{s^{2}R(L_1+L_2)C_1+aDs+R}}\end{array}\right.$$

(25)

where $L_{eq}={\displaystyle \frac{L_1{L}_2}{(L_1+L_2)}}$ and $a=(1-D)L_2-D{L}_1$. If a = 0, which means D = Leq/L₁, the following can be obtained:

$$\left\{\begin{array}{l}{\widehat{v}}_{out}={\displaystyle \frac{1}{1+2sT}}{\displaystyle \frac{R}{(sR{C}_2+1)}}{\widehat{i}}_{ref}+{\displaystyle \frac{v_{out}}{R}}{\displaystyle \frac{1}{(sR{C}_2+1)}}\widehat{R}\\ {\widehat{v}}_{C1}={\displaystyle \frac{(R+Ds{L}_2){\widehat{v}}_{in}-\frac{s^{2}D{L}_1{L}_2{\widehat{i}}_{ref}}{1+2sT}-sD{\widehat{v}}_{out}}{s^{2}R(L_1+L_2)C_1+R}}\end{array}\right.$$

(26)

The closed-loop small-signal modeling for the system is illustrated in Figure 7.

3.3. Damping Design to Stabilize v_C1

In large signal behavior analysis, v_C1 is equal to v_in. However, the ripple on v_C1 may affect system stability, as Figure 8 depicts. Therefore, a damping network should be used to stabilize v_C1 with certain parameters.

The basic idea for stabilizing v_C1 is to maintain the same port characteristics across C₁. Denoting the complex impedance of C₁ without the damping network as 1/sC_{1_nd}, and that with the damping network as 1/sC₁, the following can be expressed:

$${\displaystyle \frac{1}{s{C}_{1\_nd}}}={\displaystyle \frac{R_d+\frac{1}{s{C}_d}}{R_d+\frac{1}{s{C}_d}+\frac{1}{s{C}_1}}}{\displaystyle \frac{1}{s{C}_1}}={\displaystyle \frac{s{C}_1{C}_d{R}_d+C_1}{s{C}_1{C}_d{R}_d+C_1+C_d}}{\displaystyle \frac{1}{s{C}_1}}$$

(27)

Substituting C_{1_nd} for C₁ in Equation (25), the following can be derived:

$${\displaystyle \frac{s^{2}R(L_1+L_2)C_1(s{C}_d{C}_1{R}_d+C_d+C_1)+(aDs+R)(s{C}_d{C}_1{R}_d+C_1)}{(s{C}_d{C}_1{R}_d+C_1)}}{\widehat{v}}_{C1}=(R+Ds{L}_2){\widehat{v}}_{in}+{\displaystyle \frac{s(aR-Ds{L}_1{L}_2){\widehat{i}}_{ref}}{1+2sT}}-sD{\widehat{v}}_{out}$$

(28)

If C_d is much higher than C₁, then at high frequencies, the following applies:

$$\left\{\begin{array}{l}{\widehat{v}}_{out}={\displaystyle \frac{1}{1+2sT}}{\displaystyle \frac{R}{(sR{C}_2+1)}}{\widehat{i}}_{ref}+{\displaystyle \frac{v_{out}}{R}}{\displaystyle \frac{1}{(sR{C}_2+1)}}\widehat{R}\\ {\widehat{v}}_{C1}={\displaystyle \frac{(R+sD{L}_2){\widehat{v}}_{in}+\frac{s(aR-sD{L}_1{L}_2)}{1+2sT}{\widehat{i}}_{ref}-sD{\widehat{v}}_{out}}{s^{2}R(L_1+L_2)C_1+s[R(L_1+L_2)/R_d+aD]+R}}\end{array}\right.$$

(29)

According to the numerator of Equation (29), it can be regarded as the expression of the second-order damped network:

$$\left\{\begin{array}{l}{s}^2+s{\displaystyle \frac{[R(L_1+L_2)/R_d+aD]}{R(L_1+L_2)C_1}}+{\displaystyle \frac{R}{R(L_1+L_2)C_1}}\\ s^2+2\zeta {\omega }_{n}s+{\omega }_n^2\end{array}\right.$$

(30)

where ωn is the natural frequency and ζ is the damping ratio. Comparing the parameters, the following can be obtained:

$${\displaystyle \frac{[R(L_1+L_2)/R_d+aD]}{R(L_1+L_2)C_1}}=2\zeta \sqrt{{\displaystyle \frac{R}{R(L_1+L_2)C_1}}}$$

(31)

From (31), R_d can be derived as follows:

$$R_d={\displaystyle \frac{R(L_1+L_2)}{2\zeta R\sqrt{(L_1+L_2)C_1}-aD}}$$

(32)

When a = 0, R_d can be simplified as follows:

$$R_d={\displaystyle \frac{1}{2\zeta }}\sqrt{{\displaystyle \frac{L_1+L_2}{C_1}}}$$

(33)

According to the stability condition of the second-order system, generally let 0 < ζ < 1 to ensure the system is underdamped. When ζ is closer to 1, the response speed of the system is faster, but the overshoot will also increase. There is a trade-off between response speed and overshoot when designing circuit parameters.

The transfer function can be expressed as follows:

$$[{\mathrm{sC}}_1+{\displaystyle \frac{{\mathrm{D}}^2}{{\mathrm{sL}}_2}}+{\displaystyle \frac{{(1-D)}^2}{s{L}_1}}]{\widehat{v}}_{\mathrm{C}1}=[{\displaystyle \frac{(1-D)}{s{L}_1}}+{\displaystyle \frac{D}{R}}{\displaystyle \frac{2sT}{1+2sT}}({\displaystyle \frac{L_{eq}}{2s{L}_{1}T}}+D)]{\widehat{v}}_{in}-{\displaystyle \frac{D}{R}}{\widehat{v}}_{out}-{\displaystyle \frac{D}{R}}{\displaystyle \frac{s{L}_{eq}}{1+2sT}}{\widehat{i}}_{ref}$$

(34)

3.4. Simplified Algorithm

The calculation requires sampling four state variables, i.e., <v_in, v_out, i_out, v_C1>, which complicates the sampling circuit design. To simplify the algorithm, substituting v_in for v_C1 in Equation (21) gives the following:

$$D[k+1]={\displaystyle \frac{1}{v_{in}[k]}}[{\displaystyle \frac{L_1{L}_2}{L_1+L_2}}{\displaystyle \frac{(i_{ref}[k]-i_{out}[k])}{T}}+2v_{out}[k]]-D[k]$$

(35)

Using (35) for control can significantly simplify the algorithm. Since v_C1 approximates v_in, the simplified algorithm is valid for control, which will be proved by the following small-signal models.

From Equation (22), if we assume v_C1 = v_in, we obtain the following:

$$D(z+1)={\displaystyle \frac{1}{v_{in}}}[{\displaystyle \frac{L_1{L}_2}{L_1+L_2}}{\displaystyle \frac{(i_{ref}-i_{out})}{T}}+2v_{out}]$$

(36)

Setting D_z = D again results in the following:

$$D={\displaystyle \frac{1}{v_{in}}}[{\displaystyle \frac{L_1{L}_2}{L_1+L_2}}{\displaystyle \frac{(i_{ref}-i_{out})}{2T}}+v_{out}]$$

(37)

Differentiating D_z yields the following:

$$\widehat{D}={\displaystyle \frac{1}{v_{in}}}[{\displaystyle \frac{L_1{L}_2}{2T(L_1+L_2)}}({\widehat{i}}_{ref}-{\widehat{i}}_{out})+{\widehat{v}}_{out}]-{\displaystyle \frac{\frac{L_1{L}_2}{L_1+L_2}\frac{(i_{ref}-i_{out})}{2T}+v_{out}}{{v_{in}}^2}}{\widehat{v}}_{in}$$

(38)

Considering ${\widehat{i}}_{out}={\widehat{i}}_{L1}+{\widehat{i}}_{L2}$ and substituting Equation (38) into the steady-state expression (6), the following can be derived:

$$\left\{\begin{array}{l}(s{C}_2+{\displaystyle \frac{1}{R}}){\widehat{v}}_{out}=({\displaystyle \frac{L_{eq}}{L_1}}-D){\displaystyle \frac{2sT}{1+2sT}}{\displaystyle \frac{1}{s{L}_{eq}}}({\widehat{v}}_{in}-{\widehat{v}}_{C1})+{\displaystyle \frac{1}{1+2sT}}{\widehat{i}}_{ref}+{\displaystyle \frac{v_{out}}{R^2}}\widehat{R}\\ [s{C}_1+{\displaystyle \frac{D^2}{s{L}_2}}+{\displaystyle \frac{{(1-D)}^2}{s{L}_1}}-({\displaystyle \frac{1}{s{L}_1}}-{\displaystyle \frac{D}{s{L}_{eq}}}-{\displaystyle \frac{D}{R}}){\displaystyle \frac{1}{1+2sT}}({\displaystyle \frac{L_{eq}}{L_1}}-D)]{\widehat{v}}_{C1}\\ =[{\displaystyle \frac{(1-D)}{s{L}_1}}-({\displaystyle \frac{1}{s{L}_1}}-{\displaystyle \frac{D}{s{L}_{eq}}}-{\displaystyle \frac{D}{R}}){\displaystyle \frac{2sT}{1+2sT}}({\displaystyle \frac{L_{eq}}{2s{L}_{1}T}}+D)]{\widehat{v}}_{in}-{\displaystyle \frac{D}{R}}{\widehat{v}}_{out}+({\displaystyle \frac{1}{sD{L}_1}}-{\displaystyle \frac{1}{s{L}_{eq}}}-{\displaystyle \frac{1}{R}})D{\displaystyle \frac{s{L}_{eq}}{1+2sT}}{\widehat{i}}_{ref}\end{array}\right.$$

(39)

When the converter operates in the state D = Leq/L₁, it yields the following:

$$\left\{\begin{array}{l}{\widehat{v}}_{out}={\displaystyle \frac{R}{(sR{C}_2+1)}}{\displaystyle \frac{1}{1+2sT}}{\widehat{i}}_{ref}+{\displaystyle \frac{1}{(sR{C}_2+1)}}{\displaystyle \frac{v_{out}}{R}}\widehat{R}\\ {\widehat{v}}_{C1}={\displaystyle \frac{R+s{L_2}^2/(L_1+L_2)}{s^{2}R(L_1+L_2)C_1+R}}{\widehat{v}}_{in}-{\displaystyle \frac{s{L}_2}{s^{2}R(L_1+L_2)C_1+R}}{\widehat{v}}_{out}-{\displaystyle \frac{1}{s^{2}R(L_1+L_2)C_1+R}}{\displaystyle \frac{s^2{L}_1{L_2}^2}{(L_1+L_2)}}{\displaystyle \frac{1}{1+2sT}}{\widehat{i}}_{ref}\end{array}\right.$$

(40)

Since the zeros and poles frequencies of the transfer function from v_in to v_C1 are orders of magnitude higher compared to the switching frequency, this means that the small-signal difference between v_in and v_C1 can be neglected.

4. Root Locus Simulations

To investigate possible oscillation frequency, pole/zero maps of the small-signal model are provided below. The simulations are based on the same specifications as the experiments, and the maps are plotted with changes in duty ratio and load resistance. The influence of the damping network is also considered.

The small-signal model of the superbuck converter without a damping network is given by (8). These functions change with D, and the simulated pole/zero maps are plotted in Figure 9. These functions have the same denominator and present four poles. Two dominant poles are conjugated and change from (31.9 k rad/s, 0.05) to (25.3 k rad/s, 0.21). Two non-dominant poles are also conjugated and change from (52.4 k rad/s, 0.17) to (67.4 k rad/s, 0.07). The numerators of G_vl(s) and G_vg(s) are similar and present two conjugate zeros located on the imaginary axis, and G_vl(s) presents a spare zero located at the origin. The numerator of G_vd(s) presents two conjugate RHP zeros, which are very harmful to stability. However, all zeros have higher frequencies than the dominant poles. Therefore, with appropriate compensation, they will have a minor influence on the closed-loop response.

With respect to frequency compensation, considering RHP zeros and non-dominant poles, the system will become unstable if the crossover frequency is higher than that of the dominant poles. On the other hand, minor oscillations occur if the crossover frequency is much lower than that of the dominant poles. With moderate compensation, potential oscillations can occur near the frequency of the dominant poles. When D changes from 0.45 to 0.85, the minimum oscillation frequency is around 25.3 k rad/s under the simulation conditions described here.

The functions in (8) also change with load resistance, and the simulated pole/zero maps are plotted in Figure 10. All functions still have the same denominator and present four poles. Two dominant poles are conjugated and change from (32.6 k rad/s, 0.34) to (28.5 k rad/s, 0.04). Two non-dominant poles are also conjugated and change from (52.3 k rad/s, 0.27) to (59.9 k rad/s, 0.04). The numerators of G_vl(s) and G_vg(s) are similar and present two conjugate zeros located on the imaginary axis, and G_vl(s) presents a spare zero located at the origin. The numerator of G_vd(s) presents two conjugate RHP zeros, which are very harmful to stability. With moderate compensation, potential oscillations can occur near the frequency of the dominant poles. When R changes from 4 to 28 Ω, the minimum oscillation frequency is around 28.5 k rad/s.

The small-signal model of the superbuck converter with a damping network is given by (10), an extra zero and an additional pole is introduced. These functions change with D, and the simulated pole/zero maps are plotted in Figure 11, where one pair of zeros and poles cancel each other out. These functions have the same denominator and present five poles. Two dominant poles are conjugated and change from (33 k rad/s, 0.53) to (24.4 k rad/s, 0.40). Two non-dominant poles are also conjugated and change from (49.1 k rad/s, 0.34) to (67.6 k rad/s, 0.37). The numerators of G_vl(s) and G_vg(s) are similar and present two conjugate zeros that have higher frequencies than the dominant poles, and G_vl(s) presents a spare zero located at the origin. The numerator of G_vd(s) presents two conjugate zeros near the dominant poles. When D is around 0.5, the presented zeros can offset the dominant poles, improving stability and bandwidth. However, as D increases, the dominant poles and zeros separate from each other, degrading stability. To ensure stability across the entire operation range, a moderate design is to set the crossover frequency near the dominant poles. When D changes from 0.45 to 0.85, the minimum oscillation frequency is around 24.4 k rad/s.

The functions in (10) also change with R, and the simulated pole/zero maps are plotted in Figure 12. These functions have the same denominator and present five poles. Two dominant poles are conjugated and change from (23.8 k rad/s, 0.29) to (29.3 k rad/s, 0.58). Two non-dominant poles are also conjugated and change from (70.6 k rad/s, 0.60) to (55.0 k rad/s, 0.20). The extra pole introduced by the damping network is canceled out by an extra zero. The numerators of G_vl(s) and G_vg(s) are similar and present two conjugate zeros that have higher frequencies than the dominant poles. Additionally, G_vl(s) presents a spare zero located at the origin. The numerator of G_vd(s) presents two conjugate zeros that also have higher frequencies than the dominant poles, which is beneficial to the loop stability. To ensure stability across the entire operation range, a moderate design is to set the crossover frequency near the dominant poles. When R changes from 4 to 28 Ω, the minimum oscillation frequency is around 23.8 k rad/s.

5. Experiments

To verify the effectiveness of the proposed digital PPCC strategy, a superbuck converter prototype with a damping network is tested. A photograph of the prototype with a digital controller is given in Figure 13, while the main specifications are given in

Table 1. Specifications of the superbuck converter.

Component	Parameter
L1	250 μH
L2	110 μH
C1	2.5 μF
C2	5 μF
Cd	47 μF
Rd	8.2 Ω
vin	42 V
vout	28 V
fsw	100 kHz

.

The digital controller is implemented using a STMicroelectronics STM32F334 Micro Controller Unit (MCU). This MCU features high-resolution pulse width modulation (HRPWM) with a maximum resolution of 217 ps and an on-chip 5 Msps 12-bit analog-to-digital converter (ADC). The equivalent timer frequency of HRPWM can reach up to 4.608 GHz, which means the counter value is 46,080 when the driving frequency is 100 kHz. Compared with the 12-bit ADC resolution, the resolution of HRPWM is higher, which can avoid limit cycle oscillations.

The compensator’s parameters are the same as those of the simulation in Section 4. The digital PPCC strategy has a voltage outer loop which adopts a conventional PI controller, and the coefficients are set as p = 0.75 and I = 0.13 (considering the control frequency is 100 kHz). The dual-loop PI control strategy has a voltage outer loop and a current inner loop, both of which adopt conventional PI compensation. The inner loop coefficients are set as p = 0.2 and I = 0.02, and the coefficients of the outer loop are set as p = 0.20 and I = 0.06 (ensuring the same system phase margin as the PPCC).

The settling time of the output voltage is the main criterion for evaluating the step response performance of the converter. In order to unify the evaluation criteria, the deviation of the output voltage does not exceed 10% of the steady-state value, which is to enter the steady state. For example, assuming that the reference voltage is set to a constant 28 V, when a disturbance is introduced, the output voltage is considered to be back to steady state if the output voltage returns to the 28 ± 0.28 V range.

5.1. Load Step Response

In this subsection, the reference voltage and line voltage are set to constant values of 28 V and 42 V, respectively. Firstly, a resistive load is implemented to vary from 28 Ω to 14 Ω, which means the output current is changed from 1 A to 2 A in steady sate. Figure 14 depicts the load step response difference between the dual-loop PI control and digital PPCC strategy when the resistive load steps from 28 Ω to 14 Ω. As a result, Figure 14a shows that the output voltage restabilizes in 177.6 μs under dual-loop PI control, while the output voltage restabilizes in 93.2 μs in Figure 14b. The proposed digital PPCC strategy improves the resistive load response by 47.3% under these conditions.

Secondly, the electronic load is connected to the output and set to constant current (CC) mode, and the output current steps from 1 A to 2 A at the rate of 0.25 A/μs. Figure 15a shows that the output voltage restabilizes in 177.6 μs under dual-loop PI control, while the output voltage in Figure 15b return to stability within 111.6 μs. The proposed digital PPCC strategy improves the resistive load response by 37.2% under these conditions.

5.2. Reference Voltage Step Response

In this subsection, a 28 Ω resistive load is used, and the input line voltage is set to a constant 42 V. Figure 16 depicts the reference step response difference between the dual-loop PI control and digital PPCC strategy, when the reference voltage is programmed to step from 20 V to 28 V. Figure 16a shows that the output voltage stabilizes at 28 V within 311.6 μs and has an overshoot of about 3 V. Figure 16b shows that the output voltage stabilizes at 28 V in 159.6 μs and has the same overshoot of around 3 V. The proposed digital PPCC strategy improves the reference load response by 48.8% under these conditions.

5.3. Line Voltage Step Response

In this subsection, a 28 Ω resistive load is used, and the reference voltage is set to a constant 28 V. Figure 17 depicts the input line voltage step response difference between the dual-loop PI control and digital PPCC strategy when the line voltage rapidly steps from 42 V to 36 V. Figure 17a shows that the output voltage restabilizes at 28 V within 309.6 μs and has a maximum overshoot of about 0.8 V. Figure 17b shows that the output voltage returns to stability in 67.62 μs and reduces the overshoot to about 0.4 V. Owing to the digital PPCC strategy employing the line voltage sampling value as a calculation term, its line step response is reduced by 78.2% compared to conventional dual-loop PI control.

5.4. Single Current Loop Step Response

To demonstrate the difference in inner current loop performance between the dual-loop PI control and digital PPCC, the outer loops of both controllers are left open in this subsection. The line voltage is set to a constant 42 V, and a 14 Ω resistive load is used. Figure 18 depicts the dynamic response when the inner loop reference current steps from 1.2 A to 1.6 A. Figure 18a shows that the output current stabilizes at 1.6 A within 578.0 μs under conventional PI control. Figure 18b shows that the output current returns to stability in 390.0 μs under the PPCC strategy. The proposed digital PPCC strategy improves the inner current loop step response by 32.5% under these conditions.

5.5. Closed-Loop System Bode Plot

Using the Bode100 vector network analyzer, the system’s amplitude–frequency and phase–magnitude responses are measured under traditional working conditions (42 V line voltage, 28 V output, and 14 Ω resistive load).The measured dual-loop PI closed-loop Bode plot is shown in Figure 19, and the simulated dual-loop PI closed-loop Bode plot is presented in Figure 20.

6. Conclusions

In this paper, a digital PPCC strategy for the superbuck converter is proposed. Small-signal models of the superbuck converter with and without a damping network are derived to analyze stability and design the controller. Considering digital sampling and calculation delays, the PPCC strategy is proposed to achieve high dynamic response performance, and a simplified version is given to reduce the number of sampling variables. The damping network parameter is designed based on the desired damping ratio. Moreover, root locus simulations are performed to investigate the potential oscillation frequency and verify the stability with the designed damping parameter. Finally, the effectiveness of the proposed digital PPCC strategy is validated by various step responses.