An 11-Bit Single-Slope/Successive Approximation Register Analog-to-Digital Converters with On-Chip Fine Step Range Calibration for CMOS Image Sensors

Abstract

This paper presents a novel high-precision 11-bit single-slope/successive approximation register analog-to-digital converter (SS/SAR ADC) architecture specifically designed for CMOS image sensors (CISs). The proposed design solves critical challenges in conventional ADCs by utilizing only two reference voltages, thereby minimizing voltage mismatch and completely eliminating the need for complex switch arrays. This unique approach reduces the transistor count by 64 per column ADC, significantly enhancing area efficiency and circuit simplicity. Furthermore, a groundbreaking on-chip fine step range calibration technique is introduced to mitigate the impact of parasitic capacitance, ensuring the precise alignment between coarse and fine steps and achieving exceptional linearity. Fabricated using a 0.18-µm CMOS process, the ADC demonstrates superior performance metrics, including a differential nonlinearity (DNL) of −1/+1.86 LSB, an integral nonlinearity (INL) of −2.74/+2.79 LSB, an effective number of bits (ENOB) of 8.3 bits, and a signal-to-noise and distortion ratio (SNDR) of 51.77 dB. Operating at 240 kS/s with a power consumption of 22.16 µW, the ADC achieves an outstanding figure-of-merit (${\mathrm{FOM}}_W$) of 0.291 pJ/step. These results demonstrate the proposed architecture’s potential as a transformative solution for high-speed, energy-efficient CIS applications.

1. Introduction

CMOS image sensors (CISs) are essential for a wide range of applications, including mobile devices, automotive systems, security, and virtual reality. These applications demand CIS designs that simultaneously achieve high resolution, low power consumption, and high-speed operation. To address these diverse requirements, column-parallel analog-to-digital converters (ADCs) such as cyclic ADCs [1,2], single-slope (SS) ADCs [3,4,5,6,7,8], and successive approximation register (SAR) ADCs [9,10] have been extensively explored.

Among these architectures, SS ADCs are particularly favored for their inherent simplicity, allowing for compact implementations ideal for sensor arrays. However, their reliance on $2^B$ conversion steps for B-bit resolution imposes significant speed limitations. To overcome these limitations, numerous two-step SS ADC architectures have been proposed.

A prominent approach involves a multi-ramp two-step SS ADC [3], which, while faster, suffers from increased area and power consumption. Another design employs a single ramp signal with a holding capacitor to enhance efficiency [4], but variations in parasitic capacitance compromise the linearity of fine steps. An alternative approach eliminates the holding capacitor altogether to address these parasitic effects [5], yet the large switch arrays required for compensation introduce new linearity challenges. Other methods attempt to refine coarse–fine DAC structures or integrate calibration techniques [6,7,8], though these typically necessitate $2^M+2^N$ conversion phases for M-bit coarse and N-bit fine resolutions, resulting in slower operation compared to SAR ADCs.

Hybrid SS/SAR ADC architectures have also emerged as a solution, combining the strengths of SS and SAR designs [11,12]. One such approach uses SS for the coarse stage and SAR for the fine stage, reducing conversion phases to $M+2^N$ [11]. However, this method requires multiple reference voltages, and parasitic capacitance in the CDAC degrades the fine step range, ultimately reducing the linearity of the ADC. Alternatively, SAR is used for the coarse stage and SS for the fine stage [12], achieving high speed but introducing asymmetry due to mismatches in the CDACs among column ADCs during the coarse stage.

This paper introduces a breakthrough SS/SAR ADC architecture that requires only two reference voltages, thereby significantly reducing mismatch and eliminating the need for switching arrays. The result is a reduction of 64 transistors per column ADC, accompanied by a substantial improvement in linearity and area efficiency. Furthermore, a novel on-chip fine step range calibration is implemented to effectively counteract parasitic capacitance effects, ensuring optimal alignment between coarse and fine steps.

Section 2 details the proposed SS/SAR ADC architecture, while Section 3 explains the on-chip calibration method for fine step range alignment. Section 4 provides experimental results demonstrating the superior performance of the proposed design, and Section 5 concludes the paper with a summary of the key contributions.

2. Proposed SS/SAR ADC Scheme

2.1. Previous SS/SAR ADC

Figure 1 shows the architecture of a previous SS/SAR ADC [11], designed to leverage the speed advantage of combining SS and SAR ADCs. Each column ADC consists of an SS ADC and a SAR ADC, incorporating a comparator, a capacitor-based digital-to-analog converter (CDAC), logic circuits, and a switch array for selecting reference voltages. Global components shared across all columns include a ramp generator, a reference voltage generator, and a counter for control operations.

The timing diagram in Figure 2 outlines the operation of this architecture. During the coarse phase, the SS ADC generates a ramp signal using the global ramp generator. When the ramp signal equals the input voltage ($V_{IN}$), the comparator outputs transitions, signaling the selection of two reference voltages, $V_L$ and $V_H$. These voltages are subsequently used in the fine phase by the SAR ADC to complete the conversion process and achieve the required resolution.

Despite its innovative hybrid structure, this architecture suffers from critical limitations. The use of multiple reference voltages introduces significant mismatch risks due to process variations, degrading the linearity of the ADC. Additionally, the switch array required to select among these voltages increases the circuit complexity and area overhead. Implemented with 32 transmission gates (64 transistors) per column ADC, the switch array not only occupies a considerable silicon area but also contributes to higher power consumption and additional parasitic effects. These parasitics, in turn, reduce the accuracy of fine step resolution, undermining the architecture’s ability to achieve high precision.

The reduced cycle count of $2^M+N$ for M-bit coarse and N-bit fine resolutions, compared to the $2^M+2^N$ cycles in typical designs [3], represents a significant speed improvement. However, this advantage is offset by the increased design complexity and degraded performance caused by the aforementioned challenges. Addressing these limitations requires a fundamentally new approach to the SS/SAR ADC architecture—one that eliminates the reliance on numerous reference voltages and complex switch arrays while maintaining high speed, precision, and area efficiency.

These challenges motivate the design of the proposed SS/SAR ADC, which redefines the hybrid architecture by minimizing the number of reference voltages, eliminating switch arrays, and introducing an innovative calibration technique to compensate for parasitic effects. Details of this novel approach are presented in the following sub-sections.

2.2. Proposed SS/SAR ADC Architecture

The proposed SS/SAR ADC architecture is shown in Figure 3. Compared to the previous design in Figure 1, the column ADC block has been significantly simplified by eliminating the switch array that was previously used for reference voltage selection. This modification reduces circuit complexity, as the switch array, comprising 32 transmission gates (64 transistors), is no longer required. Instead, the proposed architecture uses only two reference voltages, $SA{R}_L$ and $SA{R}_H$, effectively mitigating mismatch issues that typically arise when multiple reference voltages are used.

Figure 4 presents the detailed schematic of the proposed SS/SAR ADC. The architecture achieves an overall 11-bit resolution by employing a 4-bit SS coarse step and an 8-bit SAR fine step. To address potential asymmetry in the two-step structure, an additional 1-bit redundancy is introduced, ensuring improved accuracy. When the difference between the comparator inputs, $I{N}_P$ and $I{N}_N$, becomes extremely small, noise or other disturbances may cause the comparator to malfunction. The redundant bit mitigates this issue, enhancing the robustness and reliability of comparator operation.

Each column ADC consists of a comparator, a CDAC, logic circuits, memory, and associated switches and capacitors. The global block integrates essential components such as a ramp generator, a reference generator, and a clock/signal generator, which provide sampling clocks, counters, and other control signals.

To ensure consistent operation across all columns, the comparator employs a robust two-stage design, as illustrated in Figure 5. This design consists of a pre-amplifier followed by a StrongArm latch and incorporates an output offset storage (OOS) technique [13] to mitigate the offset variations between column ADCs. The OOS technique operates through the switches $S_{CM}$, $S_{AZ}$, and the capacitor $C_A$, which stores the comparator’s offset when $I{N}_P$ and $I{N}_N$ are set to the same voltage. The pre-amplifier adopts a five-transistor diode-connected structure, further enhanced with cross-coupled capacitors. This configuration ensures balanced coupling and accurate signal amplification, improving overall the comparator performance.

Figure 6 shows the ramp generator, which utilizes a current-steering DAC structure with 16 I-cells for 4-bit SS operation. Each I-cell is designed with a cascade configuration featuring stacked PMOS transistors, enhancing the output impedance and ensuring a stable ramp signal. A supply voltage of 3.3 V has been utilized to ensure adequate voltage headroom for the ramp signal. The ramp generator is further supported by a biasing circuit, a decoder, and a DAC driver, which enable the precise control of the MOSFETs in the current source. In contrast, the reference generator adopts a similar structure but excludes the decoder and DAC driver, as it does not require I-cell switching. To ensure isolation and maintain signal integrity, both the ramp and reference generators interface with the column ADC through a unity-gain buffer, as illustrated in Figure 7.

The unity-gain buffer features a two-stage design optimized for both high gain and stability. The first stage is a seven-transistor (7T) amplifier, which extends the conventional five-transistor (5T) structure by incorporating a cascode transistor at the input PMOS stage. This enhancement ensures a wide input range and significantly increases the gain. The second stage consists of a common-source (CS) amplifier, which further boosts the overall gain. To maintain stability, a compensation network is incorporated, achieving a phase margin of 65 degrees. Consequently, the buffer achieves a total gain of 87.7 dB.

Using only two reference voltages and eliminating the switch array, the proposed architecture enhances area efficiency and reduces power consumption for each column ADC. Additionally, the dynamic offset in the comparator is minimized by confining its operation to the vicinity of $V_L$, as detailed in Section 2.3. Furthermore, this design addresses mismatches between steps caused by parasitic capacitances at the $I{N}_P$ and $I{N}_N$ nodes, thereby improving linearity, which will be thoroughly discussed in Section 3. This design achieves a significant reduction in mismatch and parasitic effects, ensuring high linearity, compactness, and energy efficiency.

2.3. Operation of the Proposed SS/SAR ADC

The timing diagram of the proposed SS/SAR ADC is shown in Figure 8, illustrating its efficient and systematic operation. The process begins with the comparator’s output offset storage (OOS) phase, designed to minimize offset variations across column ADCs and enhance overall accuracy. During this phase, switch $S_C$ is closed to apply the voltage $V_L$, defined as half a coarse step ($\Delta V_{COARSE}$) above $SA{R}_L$, supplied via the reference generator. Switches $S_{CM}$ and $S_{AZ}$ are simultaneously engaged to set the pre-amplifier inputs $I{N}_P$ and $I{N}_N$ to $V_L$, while the capacitor $C_A$ is pre-charged to $V_{CM}$. When $S_{AZ}$ and $S_{CM}$ open, the comparator’s offset is stored in $C_A$, enabling precise offset compensation in subsequent phases.

To maximize efficiency, the sampling phase overlaps with the OOS phase. During this phase, the input signal $V_{IN}$ is applied via switch $S_S$ and sampled onto capacitor $C_S$ as $S_S$ opens. The voltage across capacitor $C_H$ becomes $V_{IN}-V_L$. Timing control ensures that $S_{AZ}$ and $S_S$ operate concurrently, followed by a slight delay for $S_{CM}$, and another delay before $S_R$ is activated. Once $S_R$ closes, the ramp signal $V_{RAMP}$ is applied, initiating the coarse phase.

In the coarse phase, the comparator operates with $I{N}_P=V_L-V_{IN}+V_{RAMP}$ and $I{N}_N=V_L$. As $V_{RAMP}$ increases linearly, the comparator detects the intersection of $V_{RAMP}$ and $V_{IN}$, causing its output to transition. This transition of the comparator output causes the opening of switch $S_R$, preventing the ramp signal from being further applied. The counter value corresponding to $V_{RAMP}$ at that moment is stored in the memory block.

The fine phase begins with a brief engagement of $S_C$, allowing $SA{R}_L$ to be sampled at the top of the CDAC, while the CDAC bottom is aligned with $SA{R}_L$. The SAR algorithm then toggles the CDAC bottom between $SA{R}_L$ and $SA{R}_H$, refining the resolution to determine $V_{RAMP}-V_{IN}$. This refined result is stored in the memory block, and the final input voltage $V_{IN}$ is calculated by combining the coarse and fine phase results.

A significant innovation of the proposed design lies in its comparator operation. During the coarse phase, $I{N}_N$ is fixed at $V_L$, ensuring a stable reference for consistent operation. In the fine phase, $I{N}_P$ is constrained to $V_L\le I{N}_P<V_L+\Delta V_{COARSE}$, keeping all operations within a controlled error range $\Delta V_{COARSE}$ around $V_L$. Unlike previous designs, where comparisons span the entire input range, this approach reduces the comparator’s dynamic offset [14], enhancing linearity and precision.

The proposed timing sequence, constrained operational range, and innovative comparator design address key limitations of the previous SS/SAR ADCs. These features enable high precision, efficiency, and robust performance, making the architecture well suited for high-resolution CIS applications.

3. Fine Step Range Calibration

In conventional SAR ADCs, parasitic capacitance in the CDAC reduces the effective input range, negatively impacting linearity. For an 8-bit top sampling SAR ADC with a unit capacitance of C and parasitic capacitance $C_p$, the total capacitance is given by $C_t=128C+64C+\cdots +2C+C=256C$. The input range is effectively reduced by a factor of ${\displaystyle \frac{C_t}{C_t+C_p}}$. Figure 9a illustrates this phenomenon, showing how parasitic capacitance shrinks the operating range of the fine step. In an ideal case without parasitic capacitance, the full-scale range is $V_{FS}=2\Delta V_{COARSE}$. However, with parasitic capacitance, the range decreases to $V_{PAR}={\displaystyle \frac{C_t}{C_t+C_p}}{V}_{FS}$, introducing a mismatch between the coarse and fine steps and degrading the linearity of the ADC.

Furthermore, the parasitic capacitance at the $I{N}_P$ node causes voltage division between $C_H$ and the parasitic capacitance, which reduces the $V_{R}AMP$ signal. This issue introduces mismatches between the coarse and fine steps, ultimately degrading the overall linearity.

This section proposes a novel calibration method to overcome these limitations by dynamically compensating for parasitic capacitance in each column ADC. The method introduces an additional reference voltage, $SA{R}_{HCAL}$, set higher than $SA{R}_H$ by a quarter of $\Delta V_{COARSE}$. As shown in Figure 9b, the calibrated fine step range, $V_{PARCAL}$, is expanded to offset the effects of parasitic capacitance and ensure alignment with the coarse step range. This is achieved using a dummy capacitor array, as depicted in Figure 10. The array consists of binary-weighted capacitors connected via switches, enabling fine adjustments to parasitic capacitance and precise calibration.

Figure 11 illustrates the timing diagram of the proposed fine step range calibration process. The method employs a calibration approach performed once prior to normal operation, minimizing the runtime impact. During the calibration phase, the existing column ADC comparator is reused to reduce the overhead area.

First, the $I{N}_P$ and $I{N}_N$ nodes are initialized to $SA{R}_L$ through switches $S_C$ and $S_{CM}$, while a specific DC voltage point on the ramp signal is applied via switch $S_R$. Next, after opening switch $S_{CM}$, switch $S_R$ is used to apply a DC voltage corresponding to two steps higher on the ramp signal. This process introduces a voltage $SA{R}_{Hp}$ at the $I{N}_P$ node, which reflects the degradation caused by parasitic capacitance at the $I{N}_P$ node. By incorporating the voltage division effect caused by the parasitic capacitance at the $I{N}_P$ node under normal operating conditions, the proposed calibration effectively compensates for the parasitic effects at the $I{N}_P$ node. The $I{N}_P$ node is set to $SA{R}_{Hp}$, and $I{N}_N$ is compared with $SA{R}_{Hp}$.

A reset phase initializes $I{N}_N$ and the CDAC bottom nodes to $SA{R}_L$. Subsequently, the MSB switch of the dummy capacitor array is activated and the bottom plate of the CDAC is switched to $SA{R}_{HCAL}$. If the comparator output indicates $I{N}_N>SA{R}_{Hp}$, the MSB switch remains connected; otherwise, it is disconnected. This process is iteratively repeated for the MSB-1 and subsequent bits, with a reset phase before each adjustment.

The calibration completes in five cycles, during which the dummy capacitor array is fine-tuned to ensure $I{N}_N$ aligns closely with $SA{R}_{Hp}$. This process achieves an alignment of coarse and fine step ranges with an error margin within 1.12 LSB. Moreover, the method is applied independently to each column ADC, enabling precise compensation for random mismatches and parasitic effects unique to each ADC. This independent per-column calibration ensures uniformity and improves the overall linearity of the ADC array.

The proposed calibration method not only resolves the mismatch between the coarse and fine step ranges caused by the parasitic capacitance at the $I{N}_P$ and $I{N}_N$ nodes, but also enhances the robustness and accuracy of the ADC in high-resolution applications.

4. Measurement Results

Figure 12 presents the chip micrograph of the proposed ADC, fabricated using a 1P 6M TSMC 0.18-µm process with analog voltages of 3.3 V and 1.8 V, and a digital voltage of 1.8 V.

The global block occupies an area of 150 µm × 686 µm, while each column ADC spans 14.5 µm × 856 µm. Within the column ADC, the CDAC occupies 14.5 µm × 275 µm (32.1% of the total ADC area), and the calibration dummy capacitor array uses 14.5 µm × 43 µm (5.0%). The digital logic occupies 14.5 µm × 215 µm (25.1%), while the comparator, including OOS components, spans 14.5 µm × 157 µm (18.3%). High-density metal–insulator–metal (MIM) capacitors are used for $C_S$, $C_H$, and $C_A$, and custom metal–oxide–metal (MOM) capacitors in the CDAC ensure precise binary weighting.

The proposed ADC achieves a sampling rate of 240 kS/s with a total power consumption of 22.2 µW. Of this, analog components such as the comparator, CDAC, and switches consume 20.1 µW, while the digital components (e.g., memory and logic) consume 2.1 µW. The global block, which includes the clock/signal generator, consumes 43.1 µW, and the ramp and reference generators account for 4.47 mW. In array sensor applications, the global block’s power is shared among all column ADCs, highlighting the importance of low per-column power consumption.

Figure 13 illustrates the differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC without calibration. The DNL and INL values are measured at −1/+2.12 LSB and −5.43/+2.52 LSB, respectively. After applying the proposed fine step range calibration, as shown in Figure 14, the DNL improves to −1/+1.86 LSB, and the INL improves to −2.74/+2.79 LSB. These enhancements validate the calibration method’s ability to correct mismatches caused by parasitic capacitance and random errors in the CDAC, significantly improving the static performance. The fast Fourier transform (FFT) plot of the ADC without calibration is shown in Figure 15. Measured at a 240 kS/s sampling rate with an input at the Nyquist frequency using 16,384 points, the results show an SNDR of 47.3 dB, an SFDR of 64.5 dB, and an ENOB of 7.5 bits. After calibration, as depicted in Figure 16, the SNDR improves to 51.77 dB, the SFDR increases to 71.4 dB, and the ENOB enhances to 8.3 bits. These improvements—4.47 dB in SNDR, 6.9 dB in SFDR, and 0.8 bits in ENOB—highlight the calibration method’s significant impact on dynamic performance.

The improvement in static and dynamic performance has been validated to reduce step mismatches and enhance linearity through calibration. However, the CDAC was designed with a conventional binary-weighted structure for the proposed calibration verification, resulting in increased size, increased gradient mismatch, and extended routing paths. These factors contributed to a larger DNL in the fine phase, negatively affecting overall circuit performance, as indicated by relatively high DNL and INL values, along with a slightly low ENOB. To address these issues, employing a CDAC with an attenuation capacitor can not only reduce the size of the CDAC and the overall circuit but also minimize gradient mismatch and shorten routing path lengths, thereby improving linearity.

Table 1. Performance comparison of ADC architectures.

Parameter	[11]	[5]	[7]	[6]	This Work
Architecture	SS/SAR	TS-SS	TS-SS	TS-SS	SS/SAR
Process (nm)	180	130	90	130	180
Supply (V)	3.3/1.8	2.8/1.5	2.8/1.5	3.3/1.2	3.3/1.8
Resolution (bit)	11	12	12	12	11
Conversion time (µs)	12	6.4	39.7	10	3.2
Fs (kS/s)	83.33	156	25.2	100	240
SNDR (dB)	-	-	-	60.78	51.77
ENOB (bit)	-	10.7 *	9.13 *	9.8	8.3
SFDR (dB)	-	-	-	76.47	71.4
DNL (LSB)	−1.45/+1.65	−0.49/+1.34	−1/+4.25	−1/+0.83	−1/+1.86
INL (LSB)	-	−2.47/+2.44	−7/+5.73	−3.31/+4.78	−2.74/+2.79
PSRR (dB)	-	-	-	-	50.5@11.7 kHz ** 38.6@117 kHz **
Power (µW)	-	90	6.35	62	22.16
ADC size (µm2)	7 × 1100	11.2 × 590	5.6 × 1007	7.5 × 675	14.5 × 856
${\mathrm{FOM}}_W$ (pJ/step)	-	0.346	0.45	0.695	0.291
${\mathrm{FOM}}_S$ (dB)	-	155.6	149.7	149.85	149.1

* ENOB is calculated as log2(2b/ϵ), where 2b is the measured ADC input range and ϵ is the maximum between worst-case INL and input-referred RMS noise [15]. ** PSRR is a simulated results.

presents the performance comparison of the proposed ADC with previous designs. Compared to [11], the DNL is similar, while the area is somewhat larger. This is attributed to the use of a conventional binary structure for the CDAC to validate the calibration, as previously mentioned. If a structure incorporating an attenuation capacitor, similarly to that in [11], is employed, it is anticipated that improvements in both the area and DNL performance will be achieved.

The figures of merit (FOM) are calculated using the following formulas:

$${\mathrm{FOM}}_W={\displaystyle \frac{\mathrm{Power}}{2\times \mathrm{BW}\times 2^{\mathrm{ENOB}}}}$$

(1)

$${\mathrm{FOM}}_S=\mathrm{SNDR}+10{log}_{10}\left({\displaystyle \frac{\mathrm{BW}}{\mathrm{Power}}}\right)$$

(2)

The proposed ADC achieves an ${\mathrm{FOM}}_W$ of 0.291 pJ/step and an ${\mathrm{FOM}}_S$ of 149.1 dB. Compared to other two-step SS ADCs [5,6,7], the design achieves a lower power consumption and a higher speed (240 kS/s). Although the area is larger due to the SAR integration and the long bottom plate routing of the CDAC, which introduces additional overhead, the ${\mathrm{FOM}}_W$ surpasses all other designs in the comparison. The ${\mathrm{FOM}}_S$ is comparable to state-of-the-art designs [6,7].

5. Conclusions

This work presents an 11-bit SS/SAR ADC that leverages a simplified architecture with only two reference voltages. By minimizing the mismatch between reference voltages and eliminating the switch array for reference voltage selection, the proposed design significantly reduces circuit complexity and improves area efficiency in column ADCs. Additionally, the operation of the comparator within a constrained voltage range effectively reduces the dynamic offset, enhancing linearity and precision.

To address fine step range variations caused by parasitic capacitance in the CDAC, an on-chip calibration circuit is introduced. This calibration method aligns the coarse and fine step ranges, resolving linearity degradation issues and ensuring robust performance. The proposed approach demonstrates a practical solution to mitigate the challenges of parasitic effects and mismatches in high-resolution ADC designs.

The measurement results validate the effectiveness of the proposed ADC. At a sampling rate of 240 kS/s, the ADC achieves an SNDR of 51.77 dB, an SFDR of 71.4 dB, and an ENOB of 8.3 bits. The DNL and INL are measured at −1/+1.86 LSB and −2.74/+2.79 LSB, respectively. Furthermore, the ADC achieves an excellent ${\mathrm{FOM}}_W$ of 0.291 pJ/step, outperforming many state-of-the-art designs.

The proposed ADC’s high performance, low power consumption, and simplified architecture make it highly suitable for high-speed CMOS image sensor (CIS) applications. Its robust calibration method and efficient design demonstrate significant advancements in achieving precision, speed, and energy efficiency in modern ADC architectures.